[PATCH 01/14] dt-bindings: soc: Document Renesas RZ/T2H (R9A09G077) SoC

[PATCH 01/14] dt-bindings: soc: Document Renesas RZ/T2H (R9A09G077) SoC

[Thierry Bultel]

Add RZ/T2H (R9A09G077) and variants in documentation.

Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
---
 .../devicetree/bindings/soc/renesas/renesas.yaml          | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
index b7acb65bdecd..33f9e37a3d3d 100644
--- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
+++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
@@ -535,6 +535,14 @@ properties:
               - renesas,r9a09g057h44 # RZ/V2HP with Mali-G31 + Mali-C55 support
           - const: renesas,r9a09g057
 
+      - description: RZ/T2H (R9A09G077)
+        items:
+          - enum:
+            - renesas,r9a09g077 # RZ/T2H with Quad Cortex-A55 + Dual Cortex-R52
+            - renesas,r9a09g077m04 # RZ/T2H with Single Cortex-A55 + Dual Cortex-R52 - no security
+            - renesas,r9a09g077m24 # RZ/T2H with Dual Cortex-A55 + Dual Cortex-R52 - no security
+            - renesas,r9a09g077m44 # RZ/T2H with Quad Cortex-A55 + Dual Cortex-R52 - no security
+
 additionalProperties: true
 
 ...
-- 
2.43.0

[PATCH 02/14] dt-bindings: serial: Document sci bindings for the Renesas RZ/T2H (a.k.a r9a09g077) SoC

[Thierry Bultel]

Document RZ/T2H (a.k.a r9a09g077) in SCI binding.

Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
---
 .../bindings/serial/renesas,rzsci.yaml        | 100 ++++++++++++++++++
 1 file changed, 100 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/serial/renesas,rzsci.yaml

diff --git a/Documentation/devicetree/bindings/serial/renesas,rzsci.yaml b/Documentation/devicetree/bindings/serial/renesas,rzsci.yaml
new file mode 100644
index 000000000000..70e83bbcc79d
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/renesas,rzsci.yaml
@@ -0,0 +1,100 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/serial/renesas,rzsci.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas Serial Communication Interface
+
+maintainers:
+  - Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
+  - Geert Uytterhoeven <geert+renesas@glider.be>
+
+allOf:
+  - $ref: serial.yaml#
+
+description: |
+  The SCI is configurable to asynchronous and synchronous serial
+  interfaces:
+  - Asynchronous interfaces (UART and Asynchronous Communications Interface
+    Adapter (ACIA))
+  - 8-bit clock synchronous interface
+  - Simple I2C (master-only)
+  - Simple SPI
+  - Smart card interface
+  - Manchester mode
+  - Asynchronous interfaces (UART, RS485 and Asynchronous Communications
+    Interface Adapter (ACIA))
+  The smart card interface complies with the ISO/IEC 7816-3 standard for
+  electronic signals and transmission protocol. Each SCI has FIFO buffers to
+  enable continuous and full-duplex communication, and the data transfer speed
+  can be configured independently using a baud rate generator.
+
+properties:
+  compatible:
+    const: renesas,r9a09g077-sci     # RZ/T2H
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    items:
+      - description: Error interrupt
+      - description: Receive buffer full interrupt
+      - description: Transmit buffer empty interrupt
+      - description: Transmit end interrupt
+
+  interrupt-names:
+    items:
+      - const: eri
+      - const: rxi
+      - const: txi
+      - const: tei
+
+  clocks:
+    minItems: 1
+    maxItems: 2
+
+  clock-names:
+    minItems: 1
+    maxItems: 2
+    items:
+      enum:
+        - fck # UART functional clock
+        - sck # optional external clock input
+
+  power-domains:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - interrupt-names
+  - clocks
+  - clock-names
+  - power-domains
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/r9a09g077-cpg.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    aliases {
+        serial0 = &sci0;
+    };
+
+    sci0: serial@80005000 {
+        compatible = "renesas,r9a09g077-sci";
+        reg = <0x80005000 0x400>;
+        interrupts = <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>;
+        interrupt-names = "eri", "rxi", "txi", "tei";
+        clocks = <&cpg CPG_MOD R9A09G077_SCI0_CLK>;
+        clock-names = "fck";
+        power-domains = <&cpg>;
+    };
-- 
2.43.0

[PATCH 03/14] dt-bindings: soc: Document the Renesas RZ/T2H Evaluation board for the R9A09G077 SoC

[Thierry Bultel]

Add the RZ/T2H Evaluation board (r9a9g077m44-dev) in documentation.

Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
---
 Documentation/devicetree/bindings/soc/renesas/renesas.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
index 33f9e37a3d3d..331a007dbe35 100644
--- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
+++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
@@ -537,6 +537,8 @@ properties:
 
       - description: RZ/T2H (R9A09G077)
         items:
+          - enum:
+            - renesas,r9a9g077m44-dev # RZ/T2H Evaluation Board
           - enum:
             - renesas,r9a09g077 # RZ/T2H with Quad Cortex-A55 + Dual Cortex-R52
             - renesas,r9a09g077m04 # RZ/T2H with Single Cortex-A55 + Dual Cortex-R52 - no security
-- 
2.43.0

[PATCH 04/14] dt-bindings: clock: Document cpg bindings for the Renesas RZ/T2H SoC

[Thierry Bultel]

Document RZ/T2H (a.k.a r9a09g077) CPG (Clock Pulse Generator) binding.
Add the header file for the resets and clocks definitions.

Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
---
 .../bindings/clock/renesas,rzt2h-cpg.yaml     |  73 +++++++++
 include/dt-bindings/clock/r9a09g077-cpg.h     | 144 ++++++++++++++++++
 2 files changed, 217 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/renesas,rzt2h-cpg.yaml
 create mode 100644 include/dt-bindings/clock/r9a09g077-cpg.h

diff --git a/Documentation/devicetree/bindings/clock/renesas,rzt2h-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzt2h-cpg.yaml
new file mode 100644
index 000000000000..9a3a00126d2b
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/renesas,rzt2h-cpg.yaml
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/renesas,rzt2h-cpg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/T2H(P) Clock Pulse Generator (CPG)
+
+maintainers:
+  - Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
+
+description:
+  On Renesas RZ/T2H SoCs, the CPG (Clock Pulse Generator) handles generation
+  and control of clock signals for the IP modules, generation and control of resets,
+  and control over booting, low power consumption and power supply domains.
+
+properties:
+  compatible:
+    const: renesas,r9a09g077-cpg
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: EXTAL clock input
+      - description: LOCO clock input
+
+  clock-names:
+    items:
+      - const: extal
+      - const: loco
+
+  '#clock-cells':
+    description: |
+      - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
+        and a core clock reference, as defined in
+        <dt-bindings/clock/renesas,r9a09g077-cpg.h>,
+      - For module clocks, the two clock specifier cells must be "CPG_MOD" and
+        a module number, also defined <dt-bindings/clock/r9a09g077-cpg.h>,
+    const: 2
+
+  '#power-domain-cells':
+    const: 0
+
+  '#reset-cells':
+    description:
+      The single reset specifier cell must be the reset number, as defined in
+      <dt-bindings/clock/r9a09g077-cpg.h>.
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - '#clock-cells'
+  - '#power-domain-cells'
+  - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    clock-controller@10420000 {
+        compatible = "renesas,r9a09g077-cpg";
+        reg = <0x10420000 0x10000>;
+        clocks = <&extal>, <&loco>;
+        clock-names = "extal", "loco";
+        #clock-cells = <2>;
+        #power-domain-cells = <0>;
+        #reset-cells = <1>;
+    };
diff --git a/include/dt-bindings/clock/r9a09g077-cpg.h b/include/dt-bindings/clock/r9a09g077-cpg.h
new file mode 100644
index 000000000000..413c428478df
--- /dev/null
+++ b/include/dt-bindings/clock/r9a09g077-cpg.h
@@ -0,0 +1,144 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+ *
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__
+#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* R9A09G077 CPG Core Clocks */
+#define R9A09G077_CA55C0		0
+#define R9A09G077_CA55C1		1
+#define R9A09G077_CA55C2		2
+#define R9A09G077_CA55C3		3
+#define R9A09G077_SDHIHS		4
+#define R9A09G077_CLK_PLL1_ETH_PHY	5
+#define R9A09G077_CLK_OSC_ETH_PHY	6
+#define R9A09G077_CLK_ETHPHY		7
+#define R9A09G077_PCLKAH		8
+#define R9A09G077_PCLKAM		9
+#define R9A09G077_PCLKAL		10
+#define R9A09G077_CLK_SEL_ETH_PHY	11
+#define R9A09G077_DFI			12
+#define R9A09G077_PCLKH			13
+#define R9A09G077_PCLKM			14
+#define R9A09G077_PCLKL			15
+#define R9A09G077_PCLKGPTL		16
+#define R9A09G077_PCLKSHOST		17
+#define R9A09G077_PCLKRTC		18
+#define R9A09G077_USB			19
+#define R9A09G077_SPI0			20
+#define R9A09G077_SPI1			21
+#define R9A09G077_SPI2			22
+#define R9A09G077_SPI3			23
+#define R9A09G077_ETCLKA		24
+#define R9A09G077_ETCLKB		25
+#define R9A09G077_ETCLKC		26
+#define R9A09G077_ETCLKD		27
+#define R9A09G077_ETCLKE		28
+#define R9A09G077_ETHCLKE		29
+#define R9A09G077_ETHCLK_EXTAL		30
+#define R9A09G077_ETH_REFCLK		31
+#define R9A09G077_LCDC_CLKA		32
+#define R9A09G077_LCDC_CLKP		33
+#define R9A09G077_CA55			34
+#define R9A09G077_LCDC_CLKD		35
+
+/* R9A09G077 Module Clocks */
+#define R9A09G077_SCI0_CLK		0
+#define R9A09G077_CA55_CORE0_CLK	1
+#define R9A09G077_CA55_CORE1_CLK	2
+#define R9A09G077_CA55_CORE2_CLK	3
+#define R9A09G077_CA55_CORE3_CLK	4
+#define R9A09G077_PCIE_CLK		5
+#define R9A09G077_USB_CLK		6
+#define R9A09G077_SDHI0_CLK		7
+#define R9A09G077_SDHI1_CLK		8
+#define R9A09G077_MTU3_CLK		9
+#define R9A09G077_GPT0_CLK		10
+#define R9A09G077_GPT1_CLK		11
+#define R9A09G077_ACD0_CLK		12
+#define R9A09G077_ACD1_CLK		13
+#define R9A09G077_ACD2_CLK		14
+#define R9A09G077_GMAC0_CLK		15
+#define R9A09G077_GMAC1_CLK		16
+#define R9A09G077_GMAC2_CLK		17
+#define R9A09G077_SHOSTIF_CLK		18
+#define R9A09G077_IIC0_CLK		19
+#define R9A09G077_IIC1_CLK		20
+#define R9A09G077_IIC2_CLK		21
+#define R9A09G077_DOC_CLK		22
+#define R9A09G077_CMT0_CLK		23
+#define R9A09G077_CMT1_CLK		24
+#define R9A09G077_CMT2_CLK		25
+#define R9A09G077_CMTW0_CLK		26
+#define R9A09G077_CMTW1_CLK		27
+#define R9A09G077_SPI0_CLK		28
+#define R9A09G077_SPI1_CLK		29
+#define R9A09G077_SPI2_CLK		30
+#define R9A09G077_SPI3_CLK		31
+#define R9A09G077_SCI1_CLK		32
+#define R9A09G077_SCI2_CLK		33
+#define R9A09G077_SCI3_CLK		34
+#define R9A09G077_SCI4_CLK		35
+#define R9A09G077_SCI5_CLK		36
+#define R9A09G077_SCIE0_CLK		37
+#define R9A09G077_SCIE1_CLK		38
+#define R9A09G077_SCIE2_CLK		39
+#define R9A09G077_SCIE3_CLK		40
+#define R9A09G077_SCIE4_CLK		41
+#define R9A09G077_SCIE5_CLK		42
+#define R9A09G077_SCIE6_CLK		43
+#define R9A09G077_SCIE7_CLK		44
+#define R9A09G077_SCIE8_CLK		45
+#define R9A09G077_SCIE9_CLK		46
+#define R9A09G077_SCIE10_CLK		47
+#define R9A09G077_SCIE11_CLK		48
+#define R9A09G077_RTC_CLK		49
+#define R9A09G077_ETHSS_CLK		50
+#define R9A09G077_ETHSW_CLK		51
+#define R9A09G077_GPT2_CLK		52
+#define R9A09G077_GPT3_CLK		53
+#define R9A09G077_GPT4_CLK		54
+#define R9A09G077_GPT5_CLK		55
+#define R9A09G077_GPT6_CLK		56
+#define R9A09G077_GPT7_CLK		57
+#define R9A09G077_GPT8_CLK		58
+#define R9A09G077_GPT9_CLK		59
+#define R9A09G077_GPT10_CLK		60
+#define R9A09G077_CANFD_CLK		61
+#define R9A09G077_TSU_CLK		62
+#define R9A09G077_LCDC_CLK		63
+
+/* R9A09G077 Resets */
+#define R9A09G077_xSPI0_RST		0
+#define R9A09G077_xSPI1_RST		1
+#define R9A09G077_GMAC0_PCLKH_RST	2
+#define R9A09G077_GMAC0_PCLKM_RST	3
+#define R9A09G077_ETHSW_RST		4
+#define R9A09G077_ESC_BUS_RST		5
+#define R9A09G077_ESC_IP_RST		6
+#define R9A09G077_ETH_SUBSYSTEM_RST	7
+#define R9A09G077_MII_CONVERT_RST	8
+#define R9A09G077_GMAC1_PCLKAH_RST	9
+#define R9A09G077_GMAC1_PCLKAM_RST	10
+#define R9A09G077_GMAC2_PCLKAH_RST	11
+#define R9A09G077_GMAC2_PCLKAM_RST	12
+#define R9A09G077_SHOSTIF_MASTER_RST	13
+#define R9A09G077_SHOSTIF_SLAVE_RST	14
+#define R9A09G077_SHOSTIF_IP_RST	15
+#define R9A09G077_DDRSS_RST_N_RST	16
+#define R9A09G077_DDRSS_PWROKIN_RST	17
+#define R9A09G077_DDRSS_RST_RST		18
+#define R9A09G077_DDRSS_AXI0_RST	19
+#define R9A09G077_DDRSS_AXI1_RST	20
+#define R9A09G077_DDRSS_AXI2_RST	21
+#define R9A09G077_DDRSS_AXI3_RST	22
+#define R9A09G077_DDRSS_AXI4_RST	23
+#define R9A09G077_DDRSS_MC_RST		24
+#define R9A09G077_PCIE_RST		25
+#define R9A09G077_DDRSS_PHY_RST		26
+
+#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ */
\ No newline at end of file
-- 
2.43.0

[PATCH 05/14] soc: renesas: Add RZ/T2H (R9A09G077) config option

[Thierry Bultel]

Add a configuration option for the RZ/T2H SoC.

Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
---
 drivers/soc/renesas/Kconfig | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index 9f7fe02310b9..058ac0b53ffe 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -351,6 +351,11 @@ config ARCH_R9A09G057
 	help
 	  This enables support for the Renesas RZ/V2H(P) SoC variants.
 
+config ARCH_R9A09G077
+	bool "ARM64 Platform support for RZ/T2H"
+	help
+	  This enables support for the Renesas RZ/T2H SoC variants.
+
 endif # ARM64
 
 if RISCV
-- 
2.43.0

[PATCH 06/14] clk: renesas: Add support for RZ/T2H family clock

[Thierry Bultel]

Add the CPG driver for T2H family.

Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
---
 drivers/clk/renesas/Kconfig     |   4 +
 drivers/clk/renesas/Makefile    |   1 +
 drivers/clk/renesas/rzt2h-cpg.c | 549 ++++++++++++++++++++++++++++++++
 drivers/clk/renesas/rzt2h-cpg.h | 201 ++++++++++++
 4 files changed, 755 insertions(+)
 create mode 100644 drivers/clk/renesas/rzt2h-cpg.c
 create mode 100644 drivers/clk/renesas/rzt2h-cpg.h

diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index ff01f5f0ed20..7ad59be2099d 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -237,6 +237,10 @@ config CLK_RZV2H
 	bool "RZ/V2H(P) family clock support" if COMPILE_TEST
 	select RESET_CONTROLLER
 
+config CLK_RZT2H
+	bool "RZ/T2H family clock support" if COMPILE_TEST
+	select RESET_CONTROLLER
+
 config CLK_RENESAS_VBATTB
 	tristate "Renesas VBATTB clock controller"
 	depends on ARCH_RZG2L || COMPILE_TEST
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index 82efaa835ac7..bd9f0b54fcda 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -47,6 +47,7 @@ obj-$(CONFIG_CLK_RCAR_GEN3_CPG)		+= rcar-gen3-cpg.o
 obj-$(CONFIG_CLK_RCAR_GEN4_CPG)		+= rcar-gen4-cpg.o
 obj-$(CONFIG_CLK_RCAR_USB2_CLOCK_SEL)	+= rcar-usb2-clock-sel.o
 obj-$(CONFIG_CLK_RZG2L)			+= rzg2l-cpg.o
+obj-$(CONFIG_CLK_RZT2H)			+= rzt2h-cpg.o
 obj-$(CONFIG_CLK_RZV2H)			+= rzv2h-cpg.o
 
 # Generic
diff --git a/drivers/clk/renesas/rzt2h-cpg.c b/drivers/clk/renesas/rzt2h-cpg.c
new file mode 100644
index 000000000000..79dacbd2b186
--- /dev/null
+++ b/drivers/clk/renesas/rzt2h-cpg.c
@@ -0,0 +1,549 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * RZ/T2H Clock Pulse Generator
+ *
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ *
+ */
+
+#include <linux/bitfield.h>
+#include <linux/cleanup.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/iopoll.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pm_clock.h>
+#include <linux/pm_domain.h>
+#include <linux/reset-controller.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+#include "rzt2h-cpg.h"
+
+#ifdef DEBUG
+#define WARN_DEBUG(x)	WARN_ON(x)
+#else
+#define WARN_DEBUG(x)	do { } while (0)
+#endif
+
+#define GET_SHIFT(val)		FIELD_GET(GENMASK(19, 12), val)
+#define GET_WIDTH(val)		FIELD_GET(GENMASK(11, 8), val)
+#define GET_REG_OFFSET(val)	FIELD_GET(GENMASK(31, 20), val)
+
+/**
+ * struct rzt2h_cpg_priv - Clock Pulse Generator Private Data
+ *
+ * @rcdev: Reset controller entity
+ * @info: Pointer to platform data
+ * @dev: CPG device
+ * @cpg_base0: CPG register block base address 0
+ * @cpg_base1: CPG register block base address 1
+ * @clks: Array containing all Core and Module Clocks
+ * @rmw_lock: protects register accesses
+ * @hw: clock hw
+ * @num_core_clks: Number of Core Clocks in clks[]
+ * @num_mod_clks: Number of Module Clocks in clks[]
+ * @num_resets: Number of Module Resets in info->resets[]
+ * @last_dt_core_clk: ID of the last Core Clock exported to DT
+ */
+struct rzt2h_cpg_priv {
+	struct reset_controller_dev rcdev;
+	const struct rzt2h_cpg_info *info;
+	struct device *dev;
+	void __iomem *cpg_base0, *cpg_base1;
+	struct clk **clks;
+	spinlock_t rmw_lock;
+	struct clk_hw hw;
+	unsigned int num_core_clks;
+	unsigned int num_mod_clks;
+	unsigned int num_resets;
+	unsigned int last_dt_core_clk;
+};
+
+#define rcdev_to_priv(x)	container_of(x, struct rzt2h_cpg_priv, rcdev)
+
+static void rzt2h_cpg_del_clk_provider(void *data)
+{
+	of_clk_del_provider(data);
+}
+
+static struct clk * __init
+rzt2h_cpg_div_clk_register(const struct cpg_core_clk *core,
+			   void __iomem *base,
+			   struct rzt2h_cpg_priv *priv)
+{
+	struct device *dev = priv->dev;
+	struct clk **clks = priv->clks;
+	const struct clk *parent;
+	const char *parent_name;
+	struct clk_hw *clk_hw;
+
+	parent = clks[core->parent];
+	if (IS_ERR(parent))
+		return ERR_CAST(parent);
+
+	parent_name = __clk_get_name(parent);
+
+	if (core->dtable) {
+		clk_hw = clk_hw_register_divider_table(dev, core->name,
+						       parent_name, 0,
+						       base + GET_REG_OFFSET(core->conf),
+						       GET_SHIFT(core->conf),
+						       GET_WIDTH(core->conf),
+						       core->flag,
+						       core->dtable,
+						       &priv->rmw_lock);
+	} else {
+		clk_hw = clk_hw_register_divider(dev, core->name,
+						 parent_name, 0,
+						 base + GET_REG_OFFSET(core->conf),
+						 GET_SHIFT(core->conf),
+						 GET_WIDTH(core->conf),
+						 core->flag, &priv->rmw_lock);
+	}
+	if (IS_ERR(clk_hw))
+		return ERR_CAST(clk_hw);
+
+	return clk_hw->clk;
+}
+
+static struct clk * __init
+rzt2h_cpg_mux_clk_register(const struct cpg_core_clk *core,
+			   void __iomem *base,
+			   struct rzt2h_cpg_priv *priv)
+{
+	const struct clk_hw *clk_hw;
+
+	clk_hw = devm_clk_hw_register_mux(priv->dev, core->name,
+					  core->parent_names, core->num_parents,
+					  core->flag,
+					  base + GET_REG_OFFSET(core->conf),
+					  GET_SHIFT(core->conf),
+					  GET_WIDTH(core->conf),
+					  core->mux_flags, &priv->rmw_lock);
+	if (IS_ERR(clk_hw))
+		return ERR_CAST(clk_hw);
+
+	return clk_hw->clk;
+}
+
+struct pll_clk {
+	void __iomem *base;
+	struct rzt2h_cpg_priv *priv;
+	struct clk_hw hw;
+	unsigned int conf;
+	unsigned int type;
+};
+#define to_pll(_hw)	container_of(_hw, struct pll_clk, hw)
+
+static struct clk
+*rzt2h_cpg_clk_src_twocell_get(struct of_phandle_args *clkspec,
+			       void *data)
+{
+	unsigned int clkidx = clkspec->args[1];
+	struct rzt2h_cpg_priv *priv = data;
+	struct device *dev = priv->dev;
+	const char *type;
+	struct clk *clk;
+
+	switch (clkspec->args[0]) {
+	case CPG_CORE:
+		type = "core";
+		if (clkidx > priv->last_dt_core_clk) {
+			dev_err(dev, "Invalid %s clock index %u\n", type, clkidx);
+			return ERR_PTR(-EINVAL);
+		}
+		clk = priv->clks[clkidx];
+		break;
+
+	case CPG_MOD:
+		type = "module";
+		if (clkidx >= priv->num_mod_clks) {
+			dev_err(dev, "Invalid %s clock index %u\n", type,
+				clkidx);
+			return ERR_PTR(-EINVAL);
+		}
+		clk = priv->clks[priv->num_core_clks + clkidx];
+		break;
+
+	default:
+		dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]);
+		return ERR_PTR(-EINVAL);
+	}
+
+	if (IS_ERR(clk))
+		dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx,
+			PTR_ERR(clk));
+	else
+		dev_dbg(dev, "clock (%u, %u) is %pC at %lu Hz\n",
+			clkspec->args[0], clkspec->args[1], clk,
+			clk_get_rate(clk));
+	return clk;
+}
+
+static void __init
+rzt2h_cpg_register_core_clk(const struct cpg_core_clk *core,
+			    const struct rzt2h_cpg_info *info,
+			    struct rzt2h_cpg_priv *priv)
+{
+	struct clk *clk = ERR_PTR(-EOPNOTSUPP), *parent;
+	unsigned int id = core->id, div = core->div;
+	struct device *dev = priv->dev;
+	const char *parent_name;
+
+	WARN_DEBUG(id >= priv->num_core_clks);
+	WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
+
+	/* Skip NULLified clock */
+	if (!core->name)
+		return;
+
+	switch (core->type) {
+	case CLK_TYPE_IN:
+		clk = of_clk_get_by_name(priv->dev->of_node, core->name);
+		break;
+	case CLK_TYPE_FF:
+		WARN_DEBUG(core->parent >= priv->num_core_clks);
+		parent = priv->clks[core->parent];
+		if (IS_ERR(parent)) {
+			clk = parent;
+			goto fail;
+		}
+
+		parent_name = __clk_get_name(parent);
+		clk = clk_register_fixed_factor(NULL, core->name,
+						parent_name, CLK_SET_RATE_PARENT,
+						core->mult, div);
+		break;
+	case CLK_TYPE_DIV:
+		if (core->sel_base > 0)
+			clk = rzt2h_cpg_div_clk_register(core,
+							 priv->cpg_base1, priv);
+		else
+			clk = rzt2h_cpg_div_clk_register(core,
+							 priv->cpg_base0, priv);
+		break;
+	case CLK_TYPE_MUX:
+		clk = rzt2h_cpg_mux_clk_register(core, priv->cpg_base0, priv);
+		break;
+	default:
+		goto fail;
+	}
+
+	if (IS_ERR_OR_NULL(clk))
+		goto fail;
+
+	priv->clks[id] = clk;
+	return;
+
+fail:
+	dev_err(dev, "Failed to register %s clock %s: %ld\n", "core",
+		core->name, PTR_ERR(clk));
+}
+
+/**
+ * struct mstp_clock - MSTP gating clock
+ *
+ * @hw: handle between common and hardware-specific interfaces
+ * @priv: CPG/MSTP private data
+ * @sibling: pointer to the other coupled clock
+ * @baseaddr: register base address
+ * @enabled: soft state of the clock, if it is coupled with another clock
+ * @off: register offset
+ * @bit: ON/MON bit
+ */
+struct mstp_clock {
+	struct rzt2h_cpg_priv *priv;
+	struct mstp_clock *sibling;
+	void __iomem *baseaddr;
+	struct clk_hw hw;
+	bool enabled;
+	u32 off;
+	u8 bit;
+};
+#define to_mod_clock(_hw) container_of(_hw, struct mstp_clock, hw)
+static int rzt2h_mod_clock_is_enabled(struct clk_hw *hw)
+{
+	struct mstp_clock *clock = to_mod_clock(hw);
+	struct rzt2h_cpg_priv *priv = clock->priv;
+	u32 bitmask = BIT(clock->bit);
+	u32 value;
+
+	if (!clock->off) {
+		dev_dbg(priv->dev, "%pC does not support ON/OFF\n",  hw->clk);
+		return 1;
+	}
+	value = readl(clock->baseaddr + clock->off);
+
+	/* For all Module Stop registers, read bit meaning is as such:
+	 * 0: Release from the module-stop state
+	 * 1: Transition to the module-stop state is made
+	*/
+
+	return !(value & bitmask);
+}
+
+static const struct clk_ops rzt2h_mod_clock_ops = {
+	.is_enabled = rzt2h_mod_clock_is_enabled,
+};
+
+static void __init
+rzt2h_cpg_register_mod_clk(const struct rzt2h_mod_clk *mod,
+			   const struct rzt2h_cpg_info *info,
+			   struct rzt2h_cpg_priv *priv)
+{
+	struct mstp_clock *clock = NULL;
+	struct device *dev = priv->dev;
+	unsigned int id = mod->id;
+	struct clk_init_data init;
+	struct clk *parent, *clk;
+	const char *parent_name;
+	unsigned int i;
+
+	WARN_DEBUG(id < priv->num_core_clks);
+	WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks);
+	WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks);
+	WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
+
+	/* Skip NULLified clock */
+	if (!mod->name)
+		return;
+
+	parent = priv->clks[mod->parent];
+	if (IS_ERR(parent)) {
+		clk = parent;
+		goto fail;
+	}
+
+	clock = devm_kzalloc(dev, sizeof(*clock), GFP_KERNEL);
+	if (!clock) {
+		clk = ERR_PTR(-ENOMEM);
+		goto fail;
+	}
+
+	init.name = mod->name;
+	init.ops = &rzt2h_mod_clock_ops;
+	init.flags = CLK_SET_RATE_PARENT;
+	for (i = 0; i < info->num_crit_mod_clks; i++)
+		if (id == info->crit_mod_clks[i]) {
+			dev_dbg(dev, "CPG %s setting CLK_IS_CRITICAL\n",
+				mod->name);
+			init.flags |= CLK_IS_CRITICAL;
+			break;
+		}
+
+	parent_name = __clk_get_name(parent);
+	init.parent_names = &parent_name;
+	init.num_parents = 1;
+
+	clock->off = mod->addr;
+	clock->bit = mod->bit;
+	clock->baseaddr = mod->sel_base ? priv->cpg_base1 : priv->cpg_base0;
+	clock->priv = priv;
+	clock->hw.init = &init;
+
+	clk = devm_clk_register(dev, &clock->hw);
+	if (IS_ERR(clk))
+		goto fail;
+
+	priv->clks[id] = clk;
+
+	return;
+
+fail:
+	dev_err(dev, "Failed to register %s clock %s: %ld\n", "module",
+		mod->name, PTR_ERR(clk));
+}
+
+static bool rzt2h_cpg_is_pm_clk(const struct of_phandle_args *clkspec)
+{
+	if (clkspec->args_count != 2)
+		return false;
+
+	switch (clkspec->args[0]) {
+	case CPG_MOD:
+		return true;
+
+	default:
+		return false;
+	}
+}
+
+static int rzt2h_cpg_attach_dev(struct generic_pm_domain *unused, struct device *dev)
+{
+	struct device_node *np = dev->of_node;
+	struct of_phandle_args clkspec;
+	unsigned int i = 0;
+	bool once = true;
+	struct clk *clk;
+	int error;
+
+	while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
+					   &clkspec)) {
+		if (!rzt2h_cpg_is_pm_clk(&clkspec)) {
+			of_node_put(clkspec.np);
+			continue;
+		}
+
+		if (once) {
+			once = false;
+			error = pm_clk_create(dev);
+			if (error) {
+				of_node_put(clkspec.np);
+				goto err;
+			}
+		}
+		clk = of_clk_get_from_provider(&clkspec);
+		of_node_put(clkspec.np);
+		if (IS_ERR(clk)) {
+			error = PTR_ERR(clk);
+			goto fail_destroy;
+		}
+		error = pm_clk_add_clk(dev, clk);
+		if (error) {
+			dev_err(dev, "pm_clk_add_clk failed %d\n", error);
+			goto fail_put;
+		}
+		i++;
+	}
+
+	return 0;
+
+fail_put:
+	clk_put(clk);
+
+fail_destroy:
+	pm_clk_destroy(dev);
+err:
+	return error;
+}
+
+static void rzt2h_cpg_detach_dev(struct generic_pm_domain *unused, struct device *dev)
+{
+	if (!pm_clk_no_clocks(dev))
+		pm_clk_destroy(dev);
+}
+
+static void rzt2h_cpg_genpd_remove(void *data)
+{
+	pm_genpd_remove(data);
+}
+
+static int __init rzt2h_cpg_add_clk_domain(struct device *dev)
+{
+	struct device_node *np = dev->of_node;
+	struct generic_pm_domain *genpd;
+	int ret;
+
+	genpd = devm_kzalloc(dev, sizeof(*genpd), GFP_KERNEL);
+	if (!genpd)
+		return -ENOMEM;
+
+	genpd->name = np->name;
+	genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON |
+		       GENPD_FLAG_ACTIVE_WAKEUP;
+	genpd->attach_dev = rzt2h_cpg_attach_dev;
+	genpd->detach_dev = rzt2h_cpg_detach_dev;
+	ret = pm_genpd_init(genpd, &pm_domain_always_on_gov, false);
+	if (ret)
+		return ret;
+
+	ret = devm_add_action_or_reset(dev, rzt2h_cpg_genpd_remove, genpd);
+	if (ret)
+		return ret;
+
+	return of_genpd_add_provider_simple(np, genpd);
+}
+
+static int __init rzt2h_cpg_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
+	const struct rzt2h_cpg_info *info;
+	struct rzt2h_cpg_priv *priv;
+	unsigned int nclks, i;
+	struct clk **clks;
+	int error;
+
+	info = of_device_get_match_data(dev);
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->dev = dev;
+	priv->info = info;
+	spin_lock_init(&priv->rmw_lock);
+
+	priv->cpg_base0 = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(priv->cpg_base1))
+		return PTR_ERR(priv->cpg_base0);
+
+	priv->cpg_base1 = devm_platform_ioremap_resource(pdev, 1);
+	if (IS_ERR(priv->cpg_base1))
+		return PTR_ERR(priv->cpg_base1);
+
+	nclks = info->num_total_core_clks + info->num_hw_mod_clks;
+	clks = devm_kmalloc_array(dev, nclks, sizeof(*clks), GFP_KERNEL);
+	if (!clks)
+		return -ENOMEM;
+
+	dev_set_drvdata(dev, priv);
+	priv->clks = clks;
+	priv->num_core_clks = info->num_total_core_clks;
+	priv->num_mod_clks = info->num_hw_mod_clks;
+	priv->num_resets = info->num_resets;
+	priv->last_dt_core_clk = info->last_dt_core_clk;
+
+	for (i = 0; i < nclks; i++)
+		clks[i] = ERR_PTR(-ENOENT);
+
+	for (i = 0; i < info->num_core_clks; i++)
+		rzt2h_cpg_register_core_clk(&info->core_clks[i], info, priv);
+
+	for (i = 0; i < info->num_mod_clks; i++)
+		rzt2h_cpg_register_mod_clk(&info->mod_clks[i], info, priv);
+
+	error = of_clk_add_provider(np, rzt2h_cpg_clk_src_twocell_get, priv);
+	if (error)
+		return error;
+
+	error = devm_add_action_or_reset(dev, rzt2h_cpg_del_clk_provider, np);
+	if (error)
+		return error;
+
+	return rzt2h_cpg_add_clk_domain(dev);
+}
+
+static const struct of_device_id rzt2h_cpg_match[] = {
+#ifdef CONFIG_CLK_R9A09G077
+	{
+		.compatible = "renesas,r9a09g077-cpg",
+		.data = &r9a09g077_cpg_info,
+	},
+#endif
+	{ /* sentinel */ }
+};
+
+static struct platform_driver rzt2h_cpg_driver = {
+	.driver		= {
+		.name	= "rzt2-cpg",
+		.of_match_table = rzt2h_cpg_match,
+	},
+};
+
+static int __init rzt2h_cpg_init(void)
+{
+	return platform_driver_probe(&rzt2h_cpg_driver, rzt2h_cpg_probe);
+}
+
+subsys_initcall(rzt2h_cpg_init);
diff --git a/drivers/clk/renesas/rzt2h-cpg.h b/drivers/clk/renesas/rzt2h-cpg.h
new file mode 100644
index 000000000000..d9d28608e4c3
--- /dev/null
+++ b/drivers/clk/renesas/rzt2h-cpg.h
@@ -0,0 +1,201 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * RZ/T2H Clock Pulse Generator
+ *
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ *
+ */
+
+#ifndef __RENESAS_RZT2H_CPG_H__
+#define __RENESAS_RZT2H_CPG_H__
+
+#define SCKCR		0x00
+#define SCKCR2		0x04
+#define SCKCR3		0x08
+#define SCKCR4		0x0C
+#define PMSEL		0x10
+#define PMSEL_PLL0	BIT(0)
+#define PMSEL_PLL2	BIT(2)
+#define PMSEL_PLL3	BIT(3)
+#define PLL0EN		BIT(0)
+#define PLL2EN		BIT(0)
+#define PLL3EN		BIT(0)
+#define PLL0MON		0x20
+#define PLL0EN_REG	0x30
+#define PLL0_SSC_CTR	0x34
+#define PLL1MON		0x40
+#define LOCOCR		0x70
+#define HIZCTRLEN	0x80
+#define PLL2MON		0x90
+#define PLL2EN_REG	0xA0
+#define PLL2_SSC_CTR	0xAC
+#define PLL3MON		0xB0
+#define PLL3EN_REG	0xC0
+#define PLL3_VCO_CTR0	0xC4
+#define PLL3_VCO_CTR1	0xC8
+#define PLL4MON		0xD0
+#define PHYSEL		BIT(21)
+
+
+#define MRCTLA		0x240
+#define MRCTLE		0x250
+#define MRCTLI		0x260
+#define MRCTLM		0x270
+
+#define DDIV_PACK(offset, bitpos, size) \
+		(((offset) << 20) | ((bitpos) << 12) | ((size) << 8))
+
+#define DIVCA55		DDIV_PACK(SCKCR2, 8, 4)
+#define DIVCA55S	DDIV_PACK(SCKCR2, 12, 1)
+#define DIVCR520	DDIV_PACK(SCKCR2, 2, 2)
+#define DIVCR521	DDIV_PACK(SCKCR2, 0, 2)
+#define DIVLCDC		DDIV_PACK(SCKCR3, 20, 3)
+#define DIVCKIO		DDIV_PACK(SCKCR, 16, 3)
+#define DIVETHPHY	DDIV_PACK(SCKCR, 21, 1)
+#define DIVCANFD	DDIV_PACK(SCKCR, 20, 1)
+#define DIVSPI0		DDIV_PACK(SCKCR3, 0, 2)
+#define DIVSPI1		DDIV_PACK(SCKCR3, 2, 2)
+#define DIVSPI2		DDIV_PACK(SCKCR3, 4, 2)
+#define DIVSPI3		DDIV_PACK(SCKCR2, 16, 2)
+
+#define SEL_PLL_PACK(offset, bitpos, size) \
+	(((offset) << 20) | ((bitpos) << 12) | ((size) << 8))
+
+#define	SEL_PLL		SEL_PLL_PACK(SCKCR, 22, 1)
+
+/**
+ * Definitions of CPG Core Clocks
+ *
+ * These include:
+ *   - Clock outputs exported to DT
+ *   - External input clocks
+ *   - Internal CPG clocks
+ */
+struct cpg_core_clk {
+	const char *name;
+	const struct clk_div_table *dtable;
+	const char * const *parent_names;
+	unsigned int id;
+	unsigned int parent;
+	unsigned int div;
+	unsigned int mult;
+	unsigned int type;
+	unsigned int conf;
+	int flag;
+	int mux_flags;
+	int num_parents;
+	int sel_base;
+};
+
+enum clk_types {
+	/* Generic */
+	CLK_TYPE_IN,		/* External Clock Input */
+	CLK_TYPE_MAIN,
+	CLK_TYPE_FF,		/* Fixed Factor Clock */
+	CLK_TYPE_PLL,
+	CLK_TYPE_SAM_PLL,
+
+	/* Clock with divider */
+	CLK_TYPE_DIV,
+
+	/* Clock with clock source selector */
+	CLK_TYPE_MUX,
+
+	/* Clock with SD clock source selector */
+	CLK_TYPE_SD_MUX,
+};
+
+#define DEF_TYPE(_name, _id, _type...) \
+	{ .name = _name, .id = _id, .type = _type }
+#define DEF_BASE(_name, _id, _type, _parent...) \
+	DEF_TYPE(_name, _id, _type, .parent = _parent)
+#define DEF_INPUT(_name, _id) \
+	DEF_TYPE(_name, _id, CLK_TYPE_IN)
+#define DEF_FIXED(_name, _id, _parent, _mult, _div) \
+	DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
+#define DEF_DIV(_name, _id, _parent, _conf, _dtable, _flag, _sel_base) \
+	DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, .sel_base = _sel_base, \
+		 .parent = _parent, .dtable = _dtable, .flag = _flag)
+#define DEF_MUX(_name, _id, _conf, _parent_names, _num_parents, _flag, \
+		_mux_flags) \
+	DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \
+		 .parent_names = _parent_names, .num_parents = _num_parents, \
+		 .flag = _flag, .mux_flags = _mux_flags)
+
+/**
+ * struct rzt2h_mod_clk - Module Clocks definitions
+ *
+ * @name: handle between common and hardware-specific interfaces
+ * @id: clock index in array containing all Core and Module Clocks
+ * @parent: id of parent clock
+ * @addr: register address
+ * @sel_base: selects base address
+ * @is_coupled: flag to indicate coupled clock
+ * @bit: ON/OFF bit
+ */
+struct rzt2h_mod_clk {
+	const char *name;
+	unsigned int id;
+	unsigned int parent;
+	u32 addr;
+	int sel_base;
+	bool is_coupled;
+	u8 bit;
+};
+
+#define DEF_MOD_BASE(_name, _id, _parent, _addr, _bit, _sel_base, _is_coupled) { \
+	.name = (_name), \
+	.id = MOD_CLK_BASE + (_id), \
+	.parent = (_parent), \
+	.addr = (_addr), \
+	.bit = (_bit), \
+	.sel_base = (_sel_base), \
+	.is_coupled = (_is_coupled) \
+}
+
+#define DEF_MOD(_name, _id, _parent, _addr, _bit, _sel_base) \
+	DEF_MOD_BASE(_name, _id, _parent, _addr, _bit, _sel_base, false)
+
+/**
+ * struct rzt2_cpg_info - SoC-specific CPG Description
+ *
+ * @core_clks: Array of Core Clock definitions
+ * @num_core_clks: Number of entries in core_clks[]
+ * @last_dt_core_clk: ID of the last Core Clock exported to DT
+ * @num_total_core_clks: Total number of Core Clocks (exported + internal)
+ *
+ * @mod_clks: Array of Module Clock definitions
+ * @num_mod_clks: Number of entries in mod_clks[]
+ * @num_hw_mod_clks: Number of Module Clocks supported by the hardware
+ *
+ * @resets: Array of Module Reset definitions
+ * @num_resets: Number of entries in resets[]
+ *
+ * @crit_mod_clks: Array with Module Clock IDs of critical clocks that
+ *                 should not be disabled without a knowledgeable driver
+ * @num_crit_mod_clks: Number of entries in crit_mod_clks[]
+ */
+struct rzt2h_cpg_info {
+	/* Core Clocks */
+	const struct cpg_core_clk *core_clks;
+	unsigned int num_core_clks;
+	unsigned int last_dt_core_clk;
+	unsigned int num_total_core_clks;
+
+	/* Module Clocks */
+	const struct rzt2h_mod_clk *mod_clks;
+	unsigned int num_mod_clks;
+	unsigned int num_hw_mod_clks;
+
+	/* Resets */
+	const struct rzt2h_reset *resets;
+	unsigned int num_resets;
+
+	/* Critical Module Clocks that should not be disabled */
+	const unsigned int *crit_mod_clks;
+	unsigned int num_crit_mod_clks;
+};
+
+extern const struct rzt2h_cpg_info r9a09g077_cpg_info;
+
+#endif
-- 
2.43.0

[PATCH 07/14] clk: renesas: Add support for R9A09G077 SoC

[Thierry Bultel]

Add the R9A09G077 SoC specific definitions to the CPG driver.

Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
---
 drivers/clk/renesas/Kconfig         |   5 ++
 drivers/clk/renesas/Makefile        |   1 +
 drivers/clk/renesas/r9a09g077-cpg.c | 100 ++++++++++++++++++++++++++++
 3 files changed, 106 insertions(+)
 create mode 100644 drivers/clk/renesas/r9a09g077-cpg.c

diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index 7ad59be2099d..017ae990d50c 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -41,6 +41,7 @@ config CLK_RENESAS
 	select CLK_R9A08G045 if ARCH_R9A08G045
 	select CLK_R9A09G011 if ARCH_R9A09G011
 	select CLK_R9A09G057 if ARCH_R9A09G057
+	select CLK_R9A09G077 if ARCH_R9A09G077
 	select CLK_SH73A0 if ARCH_SH73A0
 
 if CLK_RENESAS
@@ -198,6 +199,10 @@ config CLK_R9A09G057
        bool "RZ/V2H(P) clock support" if COMPILE_TEST
        select CLK_RZV2H
 
+config CLK_R9A09G077
+	bool "RZ/T2H clock support" if COMPILE_TEST
+	select CLK_RZT2H
+
 config CLK_SH73A0
 	bool "SH-Mobile AG5 clock support" if COMPILE_TEST
 	select CLK_RENESAS_CPG_MSTP
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index bd9f0b54fcda..fe11b10bc451 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -38,6 +38,7 @@ obj-$(CONFIG_CLK_R9A07G054)		+= r9a07g044-cpg.o
 obj-$(CONFIG_CLK_R9A08G045)		+= r9a08g045-cpg.o
 obj-$(CONFIG_CLK_R9A09G011)		+= r9a09g011-cpg.o
 obj-$(CONFIG_CLK_R9A09G057)		+= r9a09g057-cpg.o
+obj-$(CONFIG_CLK_R9A09G077)		+= r9a09g077-cpg.o
 obj-$(CONFIG_CLK_SH73A0)		+= clk-sh73a0.o
 
 # Family
diff --git a/drivers/clk/renesas/r9a09g077-cpg.c b/drivers/clk/renesas/r9a09g077-cpg.c
new file mode 100644
index 000000000000..0b2895c796d1
--- /dev/null
+++ b/drivers/clk/renesas/r9a09g077-cpg.c
@@ -0,0 +1,100 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * r9a09g077 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ *
+ */
+
+#include <linux/device.h>
+#include <linux/clk-provider.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+
+#include <dt-bindings/clock/r9a09g077-cpg.h>
+
+#include "rzt2h-cpg.h"
+
+enum clk_ids {
+	/* Core Clock Outputs exported to DT */
+	/* External Input Clocks */
+	LAST_DT_CORE_CLK = R9A09G077_LCDC_CLKD,
+	CLK_EXTAL,
+	CLK_LOCO,
+
+	/* Internal Core Clocks */
+	CLK_PLL0,
+	CLK_PLL1,
+	CLK_PLL2,
+	CLK_PLL3,
+	CLK_PLL4,
+	CLK_SEL_PLL0,
+	CLK_SEL_CLK_PLL0,
+	CLK_SEL_PLL1,
+	CLK_SEL_CLK_PLL1,
+	CLK_SEL_PLL2,
+	CLK_SEL_CLK_PLL2,
+	CLK_SEL_PLL4,
+	CLK_SEL_CLK_PLL4,
+	CLK_SEL_CLK_SRC,
+	CLK_SEL_EXTAL,
+	CLK_SEL_LOCO,
+	CLK_PLL3_INPUT,
+
+	/* Module Clocks */
+	MOD_CLK_BASE,
+};
+
+static const struct clk_div_table dtable_1_2[] = {
+	{0, 2},
+	{15, 1},
+	{0, 0},
+};
+
+/* Mux clock tables */
+static const char * const sel_clk_pll0[] = { ".sel_loco", ".sel_pll0" };
+static const char * const sel_clk_pll1[] = { ".sel_loco", ".sel_pll1" };
+static const char * const sel_clk_pll4[] = { ".sel_loco", ".sel_pll4" };
+
+static const struct cpg_core_clk r9a09g077_core_clks[] __initconst = {
+	/* External Clock Inputs */
+	DEF_INPUT("extal", CLK_EXTAL),
+	DEF_INPUT("loco", CLK_LOCO),
+
+	/* Internal Core Clocks */
+	DEF_FIXED(".pll0", CLK_PLL0, CLK_EXTAL, 48, 1),
+	DEF_FIXED(".pll1", CLK_PLL1, CLK_EXTAL, 40, 1),
+	DEF_FIXED(".pll4", CLK_PLL4, CLK_EXTAL, 96, 1),
+	DEF_FIXED(".sel_pll0", CLK_SEL_PLL0, CLK_PLL0, 1, 1),
+	DEF_MUX(".sel_clk_pll0", CLK_SEL_CLK_PLL0, SEL_PLL,
+		sel_clk_pll0, ARRAY_SIZE(sel_clk_pll0), 0, CLK_MUX_READ_ONLY),
+	DEF_FIXED(".sel_pll1", CLK_SEL_PLL1, CLK_PLL1, 1, 1),
+	DEF_MUX(".sel_clk_pll1", CLK_SEL_CLK_PLL1, SEL_PLL,
+		sel_clk_pll1, ARRAY_SIZE(sel_clk_pll1), 0, CLK_MUX_READ_ONLY),
+	DEF_FIXED(".sel_pll4", CLK_SEL_PLL4, CLK_PLL4, 1, 1),
+	DEF_MUX(".sel_clk_pll4", CLK_SEL_CLK_PLL4, SEL_PLL,
+		sel_clk_pll4, ARRAY_SIZE(sel_clk_pll4), 0, CLK_MUX_READ_ONLY),
+
+	/* Core output clk */
+	DEF_DIV("CA55", R9A09G077_CA55, CLK_SEL_CLK_PLL0, DIVCA55,
+		dtable_1_2, CLK_DIVIDER_HIWORD_MASK, 1),
+	DEF_FIXED("PCLKM", R9A09G077_PCLKM, CLK_SEL_CLK_PLL1, 1, 8),
+	DEF_FIXED("PCLKGPTL", R9A09G077_PCLKGPTL, CLK_SEL_CLK_PLL1, 1, 2),
+};
+
+static const struct rzt2h_mod_clk r9a09g077_mod_clks[] __initconst = {
+	DEF_MOD("sci0", R9A09G077_SCI0_CLK, R9A09G077_PCLKM, 0x300, 8, 0),
+};
+
+const struct rzt2h_cpg_info r9a09g077_cpg_info = {
+	/* Core Clocks */
+	.core_clks = r9a09g077_core_clks,
+	.num_core_clks = ARRAY_SIZE(r9a09g077_core_clks),
+	.last_dt_core_clk = LAST_DT_CORE_CLK,
+	.num_total_core_clks = MOD_CLK_BASE,
+
+	/* Module Clocks */
+	.mod_clks = r9a09g077_mod_clks,
+	.num_mod_clks = ARRAY_SIZE(r9a09g077_mod_clks),
+	.num_hw_mod_clks = R9A09G077_LCDC_CLK + 1,
+};
-- 
2.43.0

[PATCH 08/14] serial: sh-sci: Fix a comment about SCIFA

[Thierry Bultel]

RZ/T1 has SCIFA, 'T' is not relevant.

Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
---
 drivers/tty/serial/sh-sci.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index 924b803af440..5ba25a6a5432 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -291,7 +291,7 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
 	},
 
 	/*
-	 * The "SCIFA" that is in RZ/A2, RZ/G2L and RZ/T.
+	 * The "SCIFA" that is in RZ/A2, RZ/G2L and RZ/T1
 	 * It looks like a normal SCIF with FIFO data, but with a
 	 * compressed address space. Also, the break out of interrupts
 	 * are different: ERI/BRI, RXI, TXI, TEI, DRI.
-- 
2.43.0

[PATCH 09/14] serial: sh-sci: Introduced function pointers

[Thierry Bultel]

The aim here is to prepare support for new sci controllers like
the T2H/RSCI whose registers are too much different for being
handled in common code.

This named serial controller also has 32 bits register,
so some return types had to be changed.

The needed generic functions are no longer static, with prototypes
defined in sh-sci-common.h so that they can be used from specific
implementation in a separate file, to keep this driver as little
changed as possible.

For doing so, a set of 'ops' is added to struct sci_port.

Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
---
 drivers/tty/serial/sh-sci.c        | 339 +++++++++++++++--------------
 drivers/tty/serial/sh-sci_common.h | 178 +++++++++++++++
 2 files changed, 349 insertions(+), 168 deletions(-)
 create mode 100644 drivers/tty/serial/sh-sci_common.h

diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index 5ba25a6a5432..1b83a246c7ed 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -56,19 +56,7 @@
 
 #include "serial_mctrl_gpio.h"
 #include "sh-sci.h"
-
-/* Offsets into the sci_port->irqs array */
-enum {
-	SCIx_ERI_IRQ,
-	SCIx_RXI_IRQ,
-	SCIx_TXI_IRQ,
-	SCIx_BRI_IRQ,
-	SCIx_DRI_IRQ,
-	SCIx_TEI_IRQ,
-	SCIx_NR_IRQS,
-
-	SCIx_MUX_IRQ = SCIx_NR_IRQS,	/* special case */
-};
+#include "sh-sci_common.h"
 
 #define SCIx_IRQ_IS_MUXED(port)			\
 	((port)->irqs[SCIx_ERI_IRQ] ==	\
@@ -76,101 +64,39 @@ enum {
 	((port)->irqs[SCIx_ERI_IRQ] &&	\
 	 ((port)->irqs[SCIx_RXI_IRQ] < 0))
 
-enum SCI_CLKS {
-	SCI_FCK,		/* Functional Clock */
-	SCI_SCK,		/* Optional External Clock */
-	SCI_BRG_INT,		/* Optional BRG Internal Clock Source */
-	SCI_SCIF_CLK,		/* Optional BRG External Clock Source */
-	SCI_NUM_CLKS
-};
-
-/* Bit x set means sampling rate x + 1 is supported */
-#define SCI_SR(x)		BIT((x) - 1)
 #define SCI_SR_RANGE(x, y)	GENMASK((y) - 1, (x) - 1)
 
 #define SCI_SR_SCIFAB		SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
 				SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
 				SCI_SR(19) | SCI_SR(27)
 
-#define min_sr(_port)		ffs((_port)->sampling_rate_mask)
-#define max_sr(_port)		fls((_port)->sampling_rate_mask)
-
 /* Iterate over all supported sampling rates, from high to low */
 #define for_each_sr(_sr, _port)						\
 	for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--)	\
 		if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
 
-struct plat_sci_reg {
-	u8 offset, size;
-};
-
-struct sci_port_params {
-	const struct plat_sci_reg regs[SCIx_NR_REGS];
-	unsigned int fifosize;
-	unsigned int overrun_reg;
-	unsigned int overrun_mask;
-	unsigned int sampling_rate_mask;
-	unsigned int error_mask;
-	unsigned int error_clear;
-};
-
-struct sci_port {
-	struct uart_port	port;
-
-	/* Platform configuration */
-	const struct sci_port_params *params;
-	const struct plat_sci_port *cfg;
-	unsigned int		sampling_rate_mask;
-	resource_size_t		reg_size;
-	struct mctrl_gpios	*gpios;
-
-	/* Clocks */
-	struct clk		*clks[SCI_NUM_CLKS];
-	unsigned long		clk_rates[SCI_NUM_CLKS];
-
-	int			irqs[SCIx_NR_IRQS];
-	char			*irqstr[SCIx_NR_IRQS];
-
-	struct dma_chan			*chan_tx;
-	struct dma_chan			*chan_rx;
-
-#ifdef CONFIG_SERIAL_SH_SCI_DMA
-	struct dma_chan			*chan_tx_saved;
-	struct dma_chan			*chan_rx_saved;
-	dma_cookie_t			cookie_tx;
-	dma_cookie_t			cookie_rx[2];
-	dma_cookie_t			active_rx;
-	dma_addr_t			tx_dma_addr;
-	unsigned int			tx_dma_len;
-	struct scatterlist		sg_rx[2];
-	void				*rx_buf[2];
-	size_t				buf_len_rx;
-	struct work_struct		work_tx;
-	struct hrtimer			rx_timer;
-	unsigned int			rx_timeout;	/* microseconds */
-#endif
-	unsigned int			rx_frame;
-	int				rx_trigger;
-	struct timer_list		rx_fifo_timer;
-	int				rx_fifo_timeout;
-	u16				hscif_tot;
-
-	bool has_rtscts;
-	bool autorts;
-	bool tx_occurred;
-};
-
 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
 
 static struct sci_port sci_ports[SCI_NPORTS];
 static unsigned long sci_ports_in_use;
 static struct uart_driver sci_uart_driver;
 
-static inline struct sci_port *
-to_sci_port(struct uart_port *uart)
-{
-	return container_of(uart, struct sci_port, port);
-}
+static const struct sci_port_params_bits sci_sci_port_params_bits = {
+	.rxtx_enable = SCSCR_RE | SCSCR_TE,
+	.te_clear = SCSCR_TE | SCSCR_TEIE,
+	.poll_sent_bits = SCI_FER | SCI_TEND
+};
+
+static const struct sci_port_params_bits sci_scix_port_params_bits = {
+	.rxtx_enable = SCSCR_RE | SCSCR_TE,
+	.te_clear = SCSCR_TE | SCSCR_TEIE,
+	.poll_sent_bits = SCIF_TDFE | SCIF_TEND
+};
+
+static const struct sci_common_regs sci_common_regs = {
+	.status = SCxSR,
+	.control = SCSCR,
+};
 
 static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
 	/*
@@ -192,6 +118,8 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
 		.sampling_rate_mask = SCI_SR(32),
 		.error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
 		.error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
+		.param_bits = sci_sci_port_params_bits,
+		.common_regs = &sci_common_regs,
 	},
 
 	/*
@@ -214,6 +142,8 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
 		.sampling_rate_mask = SCI_SR(32),
 		.error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
 		.error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
+		.param_bits = sci_scix_port_params_bits,
+		.common_regs = &sci_common_regs,
 	},
 
 	/*
@@ -238,6 +168,8 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
 		.sampling_rate_mask = SCI_SR_SCIFAB,
 		.error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
 		.error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
+		.param_bits = sci_scix_port_params_bits,
+		.common_regs = &sci_common_regs,
 	},
 
 	/*
@@ -263,6 +195,8 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
 		.sampling_rate_mask = SCI_SR_SCIFAB,
 		.error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
 		.error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
+		.param_bits = sci_scix_port_params_bits,
+		.common_regs = &sci_common_regs,
 	},
 
 	/*
@@ -288,6 +222,8 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
 		.sampling_rate_mask = SCI_SR(32),
 		.error_mask = SCIF_DEFAULT_ERROR_MASK,
 		.error_clear = SCIF_ERROR_CLEAR,
+		.param_bits = sci_scix_port_params_bits,
+		.common_regs = &sci_common_regs,
 	},
 
 	/*
@@ -316,6 +252,8 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
 		.sampling_rate_mask = SCI_SR(32),
 		.error_mask = SCIF_DEFAULT_ERROR_MASK,
 		.error_clear = SCIF_ERROR_CLEAR,
+		.param_bits = sci_scix_port_params_bits,
+		.common_regs = &sci_common_regs,
 	},
 
 	/*
@@ -347,6 +285,8 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
 		.sampling_rate_mask = SCI_SR(32),
 		.error_mask = SCIF_DEFAULT_ERROR_MASK,
 		.error_clear = SCIF_ERROR_CLEAR,
+		.param_bits = sci_scix_port_params_bits,
+		.common_regs = &sci_common_regs,
 	},
 
 	/*
@@ -369,6 +309,8 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
 		.sampling_rate_mask = SCI_SR(32),
 		.error_mask = SCIF_DEFAULT_ERROR_MASK,
 		.error_clear = SCIF_ERROR_CLEAR,
+		.param_bits = sci_scix_port_params_bits,
+		.common_regs = &sci_common_regs,
 	},
 
 	/*
@@ -393,6 +335,8 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
 		.sampling_rate_mask = SCI_SR(32),
 		.error_mask = SCIF_DEFAULT_ERROR_MASK,
 		.error_clear = SCIF_ERROR_CLEAR,
+		.param_bits = sci_scix_port_params_bits,
+		.common_regs = &sci_common_regs,
 	},
 
 	/*
@@ -420,6 +364,8 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
 		.sampling_rate_mask = SCI_SR(32),
 		.error_mask = SCIF_DEFAULT_ERROR_MASK,
 		.error_clear = SCIF_ERROR_CLEAR,
+		.param_bits = sci_scix_port_params_bits,
+		.common_regs = &sci_common_regs,
 	},
 
 	/*
@@ -449,6 +395,8 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
 		.sampling_rate_mask = SCI_SR_RANGE(8, 32),
 		.error_mask = SCIF_DEFAULT_ERROR_MASK,
 		.error_clear = SCIF_ERROR_CLEAR,
+		.param_bits = sci_scix_port_params_bits,
+		.common_regs = &sci_common_regs,
 	},
 
 	/*
@@ -473,6 +421,8 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
 		.sampling_rate_mask = SCI_SR(32),
 		.error_mask = SCIF_DEFAULT_ERROR_MASK,
 		.error_clear = SCIF_ERROR_CLEAR,
+		.param_bits = sci_scix_port_params_bits,
+		.common_regs = &sci_common_regs,
 	},
 
 	/*
@@ -500,6 +450,8 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
 		.sampling_rate_mask = SCI_SR(32),
 		.error_mask = SCIF_DEFAULT_ERROR_MASK,
 		.error_clear = SCIF_ERROR_CLEAR,
+		.param_bits = sci_scix_port_params_bits,
+		.common_regs = &sci_common_regs,
 	},
 
 	/*
@@ -523,6 +475,8 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
 		.sampling_rate_mask = SCI_SR(16),
 		.error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
 		.error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
+		.param_bits = sci_scix_port_params_bits,
+		.common_regs = &sci_common_regs,
 	},
 };
 
@@ -560,7 +514,7 @@ static void sci_serial_out(struct uart_port *p, int offset, int value)
 		WARN(1, "Invalid register access\n");
 }
 
-static void sci_port_enable(struct sci_port *sci_port)
+void sci_port_enable(struct sci_port *sci_port)
 {
 	unsigned int i;
 
@@ -576,7 +530,7 @@ static void sci_port_enable(struct sci_port *sci_port)
 	sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
 }
 
-static void sci_port_disable(struct sci_port *sci_port)
+void sci_port_disable(struct sci_port *sci_port)
 {
 	unsigned int i;
 
@@ -713,15 +667,16 @@ static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
     defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
 
 #ifdef CONFIG_CONSOLE_POLL
-static int sci_poll_get_char(struct uart_port *port)
+int sci_poll_get_char(struct uart_port *port)
 {
 	unsigned short status;
+	struct sci_port *s = to_sci_port(port);
 	int c;
 
 	do {
 		status = sci_serial_in(port, SCxSR);
 		if (status & SCxSR_ERRORS(port)) {
-			sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
+			s->ops->clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
 			continue;
 		}
 		break;
@@ -734,7 +689,7 @@ static int sci_poll_get_char(struct uart_port *port)
 
 	/* Dummy read */
 	sci_serial_in(port, SCxSR);
-	sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
+	s->ops->clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
 
 	return c;
 }
@@ -742,14 +697,16 @@ static int sci_poll_get_char(struct uart_port *port)
 
 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
 {
-	unsigned short status;
+	struct sci_port *s = to_sci_port(port);
+	const struct sci_common_regs *regs = s->params->common_regs;
+	unsigned int status;
 
 	do {
-		status = sci_serial_in(port, SCxSR);
+		status = s->ops->read_reg(port, regs->status);
 	} while (!(status & SCxSR_TDxE(port)));
 
 	sci_serial_out(port, SCxTDR, c);
-	sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
+	s->ops->clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
 }
 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE ||
 	  CONFIG_SERIAL_SH_SCI_EARLYCON */
@@ -892,7 +849,7 @@ static void sci_transmit_chars(struct uart_port *port)
 		port->icount.tx++;
 	} while (--count > 0);
 
-	sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
+	s->ops->clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
 
 	if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
 		uart_write_wakeup(port);
@@ -911,6 +868,7 @@ static void sci_transmit_chars(struct uart_port *port)
 static void sci_receive_chars(struct uart_port *port)
 {
 	struct tty_port *tport = &port->state->port;
+	struct sci_port *s = to_sci_port(port);
 	int i, count, copied = 0;
 	unsigned short status;
 	unsigned char flag;
@@ -965,7 +923,7 @@ static void sci_receive_chars(struct uart_port *port)
 		}
 
 		sci_serial_in(port, SCxSR); /* dummy read */
-		sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
+		s->ops->clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
 
 		copied += count;
 		port->icount.rx += count;
@@ -978,16 +936,17 @@ static void sci_receive_chars(struct uart_port *port)
 		/* TTY buffers full; read from RX reg to prevent lockup */
 		sci_serial_in(port, SCxRDR);
 		sci_serial_in(port, SCxSR); /* dummy read */
-		sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
+		s->ops->clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
 	}
 }
 
 static int sci_handle_errors(struct uart_port *port)
 {
 	int copied = 0;
-	unsigned short status = sci_serial_in(port, SCxSR);
-	struct tty_port *tport = &port->state->port;
 	struct sci_port *s = to_sci_port(port);
+	const struct sci_common_regs *regs = s->params->common_regs;
+	unsigned int status = s->ops->read_reg(port, regs->status);
+	struct tty_port *tport = &port->state->port;
 
 	/* Handle overruns */
 	if (status & s->params->overrun_mask) {
@@ -1146,7 +1105,7 @@ static void rx_fifo_timer_fn(struct timer_list *t)
 	struct uart_port *port = &s->port;
 
 	dev_dbg(port->dev, "Rx timed out\n");
-	scif_set_rtrg(port, 1);
+	s->ops->set_rtrg(port, 1);
 }
 
 static ssize_t rx_fifo_trigger_show(struct device *dev,
@@ -1171,9 +1130,9 @@ static ssize_t rx_fifo_trigger_store(struct device *dev,
 	if (ret)
 		return ret;
 
-	sci->rx_trigger = scif_set_rtrg(port, r);
+	sci->rx_trigger = sci->ops->set_rtrg(port, r);
 	if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
-		scif_set_rtrg(port, 1);
+		sci->ops->set_rtrg(port, 1);
 
 	return count;
 }
@@ -1216,7 +1175,7 @@ static ssize_t rx_fifo_timeout_store(struct device *dev,
 		sci->hscif_tot = r << HSSCR_TOT_SHIFT;
 	} else {
 		sci->rx_fifo_timeout = r;
-		scif_set_rtrg(port, 1);
+		sci->ops->set_rtrg(port, 1);
 		if (r > 0)
 			timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0);
 	}
@@ -1341,7 +1300,7 @@ static void sci_dma_rx_reenable_irq(struct sci_port *s)
 	    s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
 		enable_irq(s->irqs[SCIx_RXI_IRQ]);
 		if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE)
-			scif_set_rtrg(port, s->rx_trigger);
+			s->ops->set_rtrg(port, s->rx_trigger);
 		else
 			scr &= ~SCSCR_RDRQE;
 	}
@@ -1623,7 +1582,7 @@ static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
 	return chan;
 }
 
-static void sci_request_dma(struct uart_port *port)
+void sci_request_dma(struct uart_port *port)
 {
 	struct sci_port *s = to_sci_port(port);
 	struct tty_port *tport = &port->state->port;
@@ -1711,7 +1670,7 @@ static void sci_request_dma(struct uart_port *port)
 	}
 }
 
-static void sci_free_dma(struct uart_port *port)
+void sci_free_dma(struct uart_port *port)
 {
 	struct sci_port *s = to_sci_port(port);
 
@@ -1721,7 +1680,7 @@ static void sci_free_dma(struct uart_port *port)
 		sci_dma_rx_release(s);
 }
 
-static void sci_flush_buffer(struct uart_port *port)
+void sci_flush_buffer(struct uart_port *port)
 {
 	struct sci_port *s = to_sci_port(port);
 
@@ -1750,11 +1709,11 @@ static void sci_dma_check_tx_occurred(struct sci_port *s)
 		s->tx_occurred = true;
 }
 #else /* !CONFIG_SERIAL_SH_SCI_DMA */
-static inline void sci_request_dma(struct uart_port *port)
+inline void sci_request_dma(struct uart_port *port)
 {
 }
 
-static inline void sci_free_dma(struct uart_port *port)
+inline void sci_free_dma(struct uart_port *port)
 {
 }
 
@@ -1762,7 +1721,9 @@ static void sci_dma_check_tx_occurred(struct sci_port *s)
 {
 }
 
-#define sci_flush_buffer	NULL
+inline void sci_flush_buffer(struct uart_port *port)
+{
+}
 #endif /* !CONFIG_SERIAL_SH_SCI_DMA */
 
 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
@@ -1780,7 +1741,7 @@ static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
 		    s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
 			disable_irq_nosync(s->irqs[SCIx_RXI_IRQ]);
 			if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
-				scif_set_rtrg(port, 1);
+				s->ops->set_rtrg(port, 1);
 				scr |= SCSCR_RIE;
 			} else {
 				scr |= SCSCR_RDRQE;
@@ -1806,8 +1767,8 @@ static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
 #endif
 
 	if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) {
-		if (!scif_rtrg_enabled(port))
-			scif_set_rtrg(port, s->rx_trigger);
+		if (!s->ops->rtrg_enabled(port))
+			s->ops->set_rtrg(port, s->rx_trigger);
 
 		mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP(
 			  s->rx_frame * HZ * s->rx_fifo_timeout, 1000000));
@@ -1817,7 +1778,7 @@ static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
 	 * of whether the I_IXOFF is set, otherwise, how is the interrupt
 	 * to be disabled?
 	 */
-	sci_receive_chars(port);
+	s->ops->receive_chars(port);
 
 	return IRQ_HANDLED;
 }
@@ -1826,9 +1787,10 @@ static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
 {
 	struct uart_port *port = ptr;
 	unsigned long flags;
+	struct sci_port *s = to_sci_port(port);
 
 	uart_port_lock_irqsave(port, &flags);
-	sci_transmit_chars(port);
+	s->ops->transmit_chars(port);
 	uart_port_unlock_irqrestore(port, flags);
 
 	return IRQ_HANDLED;
@@ -1837,16 +1799,19 @@ static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
 static irqreturn_t sci_tx_end_interrupt(int irq, void *ptr)
 {
 	struct uart_port *port = ptr;
+	struct sci_port *s = to_sci_port(port);
+	const struct sci_common_regs *regs = s->params->common_regs;
 	unsigned long flags;
-	unsigned short ctrl;
+	u32 ctrl;
 
 	if (port->type != PORT_SCI)
 		return sci_tx_interrupt(irq, ptr);
 
 	uart_port_lock_irqsave(port, &flags);
-	ctrl = sci_serial_in(port, SCSCR);
-	ctrl &= ~(SCSCR_TE | SCSCR_TEIE);
-	sci_serial_out(port, SCSCR, ctrl);
+	ctrl = s->ops->read_reg(port, regs->control);
+
+	ctrl &= ~(s->params->param_bits.te_clear);
+	s->ops->write_reg(port, regs->control, ctrl);
 	uart_port_unlock_irqrestore(port, flags);
 
 	return IRQ_HANDLED;
@@ -1855,6 +1820,7 @@ static irqreturn_t sci_tx_end_interrupt(int irq, void *ptr)
 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
 {
 	struct uart_port *port = ptr;
+	struct sci_port *s = to_sci_port(port);
 
 	/* Handle BREAKs */
 	sci_handle_breaks(port);
@@ -1862,7 +1828,7 @@ static irqreturn_t sci_br_interrupt(int irq, void *ptr)
 	/* drop invalid character received before break was detected */
 	sci_serial_in(port, SCxRDR);
 
-	sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
+	s->ops->clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
 
 	return IRQ_HANDLED;
 }
@@ -1890,15 +1856,15 @@ static irqreturn_t sci_er_interrupt(int irq, void *ptr)
 		if (sci_handle_errors(port)) {
 			/* discard character in rx buffer */
 			sci_serial_in(port, SCxSR);
-			sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
+			s->ops->clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
 		}
 	} else {
 		sci_handle_fifo_overrun(port);
 		if (!s->chan_rx)
-			sci_receive_chars(port);
+			s->ops->receive_chars(port);
 	}
 
-	sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
+	s->ops->clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
 
 	/* Kick the transmission */
 	if (!s->chan_tx)
@@ -2059,7 +2025,7 @@ static int sci_request_irq(struct sci_port *port)
 	return ret;
 }
 
-static void sci_free_irq(struct sci_port *port)
+void sci_free_irq(struct sci_port *port)
 {
 	int i, j;
 
@@ -2232,7 +2198,7 @@ static unsigned int sci_get_mctrl(struct uart_port *port)
 	return mctrl;
 }
 
-static void sci_enable_ms(struct uart_port *port)
+void sci_enable_ms(struct uart_port *port)
 {
 	mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
 }
@@ -2268,7 +2234,17 @@ static void sci_break_ctl(struct uart_port *port, int break_state)
 	uart_port_unlock_irqrestore(port, flags);
 }
 
-static int sci_startup(struct uart_port *port)
+static void sci_shutdown_complete(struct uart_port *port)
+{
+	struct sci_port *s = to_sci_port(port);
+	u16 scr;
+
+	scr = sci_serial_in(port, SCSCR);
+	sci_serial_out(port, SCSCR,
+		       scr & (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot));
+}
+
+int sci_startup(struct uart_port *port)
 {
 	struct sci_port *s = to_sci_port(port);
 	int ret;
@@ -2291,7 +2267,6 @@ static void sci_shutdown(struct uart_port *port)
 {
 	struct sci_port *s = to_sci_port(port);
 	unsigned long flags;
-	u16 scr;
 
 	dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
 
@@ -2301,13 +2276,7 @@ static void sci_shutdown(struct uart_port *port)
 	uart_port_lock_irqsave(port, &flags);
 	sci_stop_rx(port);
 	sci_stop_tx(port);
-	/*
-	 * Stop RX and TX, disable related interrupts, keep clock source
-	 * and HSCIF TOT bits
-	 */
-	scr = sci_serial_in(port, SCSCR);
-	sci_serial_out(port, SCSCR,
-		       scr & (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot));
+	s->ops->shutdown_complete(port);
 	uart_port_unlock_irqrestore(port, flags);
 
 #ifdef CONFIG_SERIAL_SH_SCI_DMA
@@ -2383,9 +2352,9 @@ static int sci_brg_calc(struct sci_port *s, unsigned int bps,
 }
 
 /* calculate sample rate, BRR, and clock select */
-static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
-			  unsigned int *brr, unsigned int *srr,
-			  unsigned int *cks)
+int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
+		   unsigned int *brr, unsigned int *srr,
+		   unsigned int *cks)
 {
 	unsigned long freq = s->clk_rates[SCI_FCK];
 	unsigned int sr, br, prediv, scrate, c;
@@ -2462,9 +2431,9 @@ static void sci_reset(struct uart_port *port)
 	if (reg->size)
 		sci_serial_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
 
-	sci_clear_SCxSR(port,
-			SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) &
-			SCxSR_BREAK_CLEAR(port));
+	s->ops->clear_SCxSR(port,
+			    SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) &
+			    SCxSR_BREAK_CLEAR(port));
 	if (sci_getreg(port, SCLSR)->size) {
 		status = sci_serial_in(port, SCLSR);
 		status &= ~(SCLSR_TO | SCLSR_ORER);
@@ -2473,14 +2442,14 @@ static void sci_reset(struct uart_port *port)
 
 	if (s->rx_trigger > 1) {
 		if (s->rx_fifo_timeout) {
-			scif_set_rtrg(port, 1);
+			s->ops->set_rtrg(port, 1);
 			timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0);
 		} else {
 			if (port->type == PORT_SCIFA ||
 			    port->type == PORT_SCIFB)
-				scif_set_rtrg(port, 1);
+				s->ops->set_rtrg(port, 1);
 			else
-				scif_set_rtrg(port, s->rx_trigger);
+				s->ops->set_rtrg(port, s->rx_trigger);
 		}
 	}
 }
@@ -2740,7 +2709,7 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
 		sci_enable_ms(port);
 }
 
-static void sci_pm(struct uart_port *port, unsigned int state,
+void sci_pm(struct uart_port *port, unsigned int state,
 		   unsigned int oldstate)
 {
 	struct sci_port *sci_port = to_sci_port(port);
@@ -2803,7 +2772,7 @@ static int sci_remap_port(struct uart_port *port)
 	return 0;
 }
 
-static void sci_release_port(struct uart_port *port)
+void sci_release_port(struct uart_port *port)
 {
 	struct sci_port *sport = to_sci_port(port);
 
@@ -2815,7 +2784,7 @@ static void sci_release_port(struct uart_port *port)
 	release_mem_region(port->mapbase, sport->reg_size);
 }
 
-static int sci_request_port(struct uart_port *port)
+int sci_request_port(struct uart_port *port)
 {
 	struct resource *res;
 	struct sci_port *sport = to_sci_port(port);
@@ -2837,7 +2806,7 @@ static int sci_request_port(struct uart_port *port)
 	return 0;
 }
 
-static void sci_config_port(struct uart_port *port, int flags)
+void sci_config_port(struct uart_port *port, int flags)
 {
 	if (flags & UART_CONFIG_TYPE) {
 		struct sci_port *sport = to_sci_port(port);
@@ -2847,7 +2816,7 @@ static void sci_config_port(struct uart_port *port, int flags)
 	}
 }
 
-static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
+int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
 {
 	if (ser->baud_base < 2400)
 		/* No paper tape reader for Mitch.. */
@@ -2856,6 +2825,18 @@ static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
 	return 0;
 }
 
+static u32 sci_get_ctrl_temp(struct uart_port *port, unsigned int ctrl)
+{
+	struct sci_port *s = to_sci_port(port);
+	unsigned int ctrl_temp;
+
+	ctrl_temp = s->params->param_bits.rxtx_enable;
+	ctrl_temp |=
+		(s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
+		(ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
+	return ctrl_temp;
+}
+
 static const struct uart_ops sci_uart_ops = {
 	.tx_empty	= sci_tx_empty,
 	.set_mctrl	= sci_set_mctrl,
@@ -2881,6 +2862,19 @@ static const struct uart_ops sci_uart_ops = {
 #endif
 };
 
+static const struct sci_port_ops sci_port_ops = {
+	.read_reg		= sci_serial_in,
+	.write_reg		= sci_serial_out,
+	.receive_chars		= sci_receive_chars,
+	.transmit_chars		= sci_transmit_chars,
+	.poll_put_char		= sci_poll_put_char,
+	.clear_SCxSR		= sci_clear_SCxSR,
+	.set_rtrg		= scif_set_rtrg,
+	.rtrg_enabled		= scif_rtrg_enabled,
+	.shutdown_complete	= sci_shutdown_complete,
+	.get_ctrl_temp		= sci_get_ctrl_temp,
+};
+
 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
 {
 	const char *clk_names[] = {
@@ -2974,6 +2968,7 @@ static int sci_init_single(struct platform_device *dev,
 	int ret;
 
 	sci_port->cfg	= p;
+	sci_port->ops	= &sci_port_ops;
 
 	port->ops	= &sci_uart_ops;
 	port->iotype	= UPIO_MEM;
@@ -3095,7 +3090,7 @@ static void sci_cleanup_single(struct sci_port *port)
     defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
 static void serial_console_putchar(struct uart_port *port, unsigned char ch)
 {
-	sci_poll_put_char(port, ch);
+	to_sci_port(port)->ops->poll_put_char(port, ch);
 }
 
 /*
@@ -3107,7 +3102,9 @@ static void serial_console_write(struct console *co, const char *s,
 {
 	struct sci_port *sci_port = &sci_ports[co->index];
 	struct uart_port *port = &sci_port->port;
-	unsigned short bits, ctrl, ctrl_temp;
+	const struct sci_common_regs *regs = sci_port->params->common_regs;
+	unsigned int bits;
+	u32 ctrl, ctrl_temp;
 	unsigned long flags;
 	int locked = 1;
 
@@ -3119,21 +3116,22 @@ static void serial_console_write(struct console *co, const char *s,
 		uart_port_lock_irqsave(port, &flags);
 
 	/* first save SCSCR then disable interrupts, keep clock source */
-	ctrl = sci_serial_in(port, SCSCR);
-	ctrl_temp = SCSCR_RE | SCSCR_TE |
-		    (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
-		    (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
-	sci_serial_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot);
+	ctrl = sci_port->ops->read_reg(port, regs->control);
+	ctrl_temp = sci_port->ops->get_ctrl_temp(port, ctrl);
+
+	sci_port->ops->write_reg(port, regs->control, ctrl_temp | sci_port->hscif_tot);
 
 	uart_console_write(port, s, count, serial_console_putchar);
 
 	/* wait until fifo is empty and last bit has been transmitted */
-	bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
-	while ((sci_serial_in(port, SCxSR) & bits) != bits)
+
+	bits = sci_ports->params->param_bits.poll_sent_bits;
+
+	while ((sci_port->ops->read_reg(port, regs->status) & bits) != bits)
 		cpu_relax();
 
 	/* restore the SCSCR */
-	sci_serial_out(port, SCSCR, ctrl);
+	sci_port->ops->write_reg(port, regs->control, ctrl);
 
 	if (locked)
 		uart_port_unlock_irqrestore(port, flags);
@@ -3268,7 +3266,6 @@ static void sci_remove(struct platform_device *dev)
 		device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout);
 }
 
-
 #define SCI_OF_DATA(type, regtype)	(void *)((type) << 16 | (regtype))
 #define SCI_OF_TYPE(data)		((unsigned long)(data) >> 16)
 #define SCI_OF_REGTYPE(data)		((unsigned long)(data) & 0xffff)
@@ -3564,9 +3561,11 @@ sh_early_platform_init_buffer("earlyprintk", &sci_driver,
 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
 static struct plat_sci_port port_cfg __initdata;
 
-static int __init early_console_setup(struct earlycon_device *device,
+int __init early_console_setup(struct earlycon_device *device,
 				      int type)
 {
+	const struct sci_common_regs *regs;
+
 	if (!device->port.membase)
 		return -ENODEV;
 
@@ -3574,10 +3573,14 @@ static int __init early_console_setup(struct earlycon_device *device,
 	memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
 	port_cfg.type = type;
 	sci_ports[0].cfg = &port_cfg;
+	sci_ports[0].ops = &sci_port_ops;
 	sci_ports[0].params = sci_probe_regmap(&port_cfg);
-	port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR);
-	sci_serial_out(&sci_ports[0].port, SCSCR,
-		       SCSCR_RE | SCSCR_TE | port_cfg.scscr);
+	regs = sci_ports[0].params->common_regs;
+
+	port_cfg.scscr = sci_ports[0].ops->read_reg(&sci_ports[0].port, regs->control);
+	sci_ports[0].ops->write_reg(&sci_ports[0].port,
+				    regs->control,
+				    sci_ports[0].params->param_bits.rxtx_enable | port_cfg.scscr);
 
 	device->con->write = serial_console_write;
 	return 0;
diff --git a/drivers/tty/serial/sh-sci_common.h b/drivers/tty/serial/sh-sci_common.h
new file mode 100644
index 000000000000..cbfacdc1a836
--- /dev/null
+++ b/drivers/tty/serial/sh-sci_common.h
@@ -0,0 +1,178 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __SH_SCI_COMMON_H__
+#define __SH_SCI_COMMON_H__
+
+#define SCI_MAJOR	204
+#define SCI_MINOR_START	8
+
+#include <linux/serial_core.h>
+
+enum SCI_CLKS {
+	SCI_FCK,		/* Functional Clock */
+	SCI_SCK,		/* Optional External Clock */
+	SCI_BRG_INT,		/* Optional BRG Internal Clock Source */
+	SCI_SCIF_CLK,		/* Optional BRG External Clock Source */
+	SCI_NUM_CLKS
+};
+
+/* Offsets into the sci_port->irqs array */
+enum {
+	SCIx_ERI_IRQ,
+	SCIx_RXI_IRQ,
+	SCIx_TXI_IRQ,
+	SCIx_BRI_IRQ,
+	SCIx_DRI_IRQ,
+	SCIx_TEI_IRQ,
+	SCIx_NR_IRQS,
+
+	SCIx_MUX_IRQ = SCIx_NR_IRQS,	/* special case */
+};
+
+/* Bit x set means sampling rate x + 1 is supported */
+#define SCI_SR(x)		BIT((x) - 1)
+
+extern void sci_release_port(struct uart_port *port);
+extern int sci_request_port(struct uart_port *port);
+extern void sci_config_port(struct uart_port *port, int flags);
+extern int sci_verify_port(struct uart_port *port, struct serial_struct *ser);
+extern void sci_pm(struct uart_port *port, unsigned int state,
+		   unsigned int oldstate);
+extern void sci_enable_ms(struct uart_port *port);
+
+#ifdef CONFIG_CONSOLE_POLL
+extern int sci_poll_get_char(struct uart_port *port);
+extern void sci_poll_put_char(struct uart_port *port, unsigned char c);
+#endif /* CONFIG_CONSOLE_POLL */
+
+struct plat_sci_reg {
+	u8 offset, size;
+};
+
+/* The actual number of needed registers depends on the sci controller;
+ * using this value as a max covers both sci and rsci cases
+ */
+#define SCI_NR_REGS 20
+
+struct sci_port_params_bits {
+	unsigned int rxtx_enable;
+	unsigned int te_clear;
+	unsigned int poll_sent_bits;
+};
+
+struct sci_common_regs {
+	unsigned int status;
+	unsigned int control;
+};
+
+struct sci_port_params {
+	const struct plat_sci_reg regs[SCI_NR_REGS];
+	const struct sci_common_regs *common_regs;
+	unsigned int fifosize;
+	unsigned int overrun_reg;
+	unsigned int overrun_mask;
+	unsigned int sampling_rate_mask;
+	unsigned int error_mask;
+	unsigned int error_clear;
+	struct sci_port_params_bits param_bits;
+};
+
+struct sci_port_ops {
+	u32 (*read_reg)(struct uart_port *port, int reg);
+	void (*write_reg)(struct uart_port *port, int reg, int value);
+	void (*clear_SCxSR)(struct uart_port *port, unsigned int mask);
+
+	void (*transmit_chars)(struct uart_port *port);
+	void (*receive_chars)(struct uart_port *port);
+
+	void (*poll_put_char)(struct uart_port *port, unsigned char c);
+
+	int (*set_rtrg)(struct uart_port *port, int rx_trig);
+	int (*rtrg_enabled)(struct uart_port *port);
+
+	void (*shutdown_complete)(struct uart_port *port);
+
+	unsigned int (*get_ctrl_temp)(struct uart_port *port, unsigned int ctrl);
+};
+
+struct sci_of_data {
+	const struct sci_port_params *params;
+	const struct uart_ops *uart_ops;
+	const struct sci_port_ops *ops;
+	unsigned short regtype;
+	unsigned short type;
+};
+
+struct sci_port {
+	struct uart_port	port;
+
+	/* Platform configuration */
+	const struct sci_port_params *params;
+	const struct plat_sci_port *cfg;
+
+	unsigned int		sampling_rate_mask;
+	resource_size_t		reg_size;
+	struct mctrl_gpios	*gpios;
+
+	/* Clocks */
+	struct clk		*clks[SCI_NUM_CLKS];
+	unsigned long		clk_rates[SCI_NUM_CLKS];
+
+	int			irqs[SCIx_NR_IRQS];
+	char			*irqstr[SCIx_NR_IRQS];
+
+	struct dma_chan			*chan_tx;
+	struct dma_chan			*chan_rx;
+
+#ifdef CONFIG_SERIAL_SH_SCI_DMA
+	struct dma_chan			*chan_tx_saved;
+	struct dma_chan			*chan_rx_saved;
+	dma_cookie_t			cookie_tx;
+	dma_cookie_t			cookie_rx[2];
+	dma_cookie_t			active_rx;
+	dma_addr_t			tx_dma_addr;
+	unsigned int			tx_dma_len;
+	struct scatterlist		sg_rx[2];
+	void				*rx_buf[2];
+	size_t				buf_len_rx;
+	struct work_struct		work_tx;
+	struct hrtimer			rx_timer;
+	unsigned int			rx_timeout;	/* microseconds */
+#endif
+	unsigned int			rx_frame;
+	int				rx_trigger;
+	struct timer_list		rx_fifo_timer;
+	int				rx_fifo_timeout;
+	u16				hscif_tot;
+
+	const struct sci_port_ops *ops;
+
+	bool has_rtscts;
+	bool autorts;
+	bool tx_occurred;
+};
+
+#define to_sci_port(uart) container_of((uart), struct sci_port, port)
+
+extern int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
+			  unsigned int *brr, unsigned int *srr,
+			  unsigned int *cks);
+
+extern void sci_port_disable(struct sci_port *sci_port);
+extern void sci_port_enable(struct sci_port *sci_port);
+
+extern int sci_startup(struct uart_port *port);
+extern void sci_free_irq(struct sci_port *port);
+
+extern void sci_request_dma(struct uart_port *port);
+extern void sci_free_dma(struct uart_port *port);
+extern void sci_flush_buffer(struct uart_port *port);
+
+#define min_sr(_port)		ffs((_port)->sampling_rate_mask)
+#define max_sr(_port)		fls((_port)->sampling_rate_mask)
+
+#ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
+extern int __init early_console_setup(struct earlycon_device *device, int);
+#endif
+
+#endif /* __SH_SCI_COMMON_H__ */
-- 
2.43.0

[PATCH 10/14] serial: sh-sci: Introduced sci_of_data

[Thierry Bultel]

The aim here is to provide an easier support to more different SCI
controllers, like the RZ/T2H one.

The existing .data field of_sci_match is changed to a structure containing
all what that can be statically initialized, and avoid a call to
'sci_probe_regmap', in both 'sci_init_single', and 'early_console_setup'.

'sci_probe_regmap' is now assumed to be called in the only case where the
device description is from a board file instead of a dts.

In this way, there is no need to patch 'sci_probe_regmap' for adding new
SCI type, and also, the specific sci_port_params for a new SCI type can be
provided by an external file.

Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
---
 drivers/tty/serial/sh-sci.c        | 64 +++++++++++++++++++-----------
 drivers/tty/serial/sh-sci_common.h |  3 +-
 2 files changed, 43 insertions(+), 24 deletions(-)

diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index 1b83a246c7ed..c58c0793c521 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -2968,9 +2968,7 @@ static int sci_init_single(struct platform_device *dev,
 	int ret;
 
 	sci_port->cfg	= p;
-	sci_port->ops	= &sci_port_ops;
 
-	port->ops	= &sci_uart_ops;
 	port->iotype	= UPIO_MEM;
 	port->line	= index;
 	port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_SH_SCI_CONSOLE);
@@ -3010,7 +3008,16 @@ static int sci_init_single(struct platform_device *dev,
 		for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++)
 			sci_port->irqs[i] = sci_port->irqs[0];
 
-	sci_port->params = sci_probe_regmap(p);
+	/*
+	 * sci_port->params params can be NULL when using a board file instead
+	 * of a dts.
+	 */
+	if (sci_port->params == NULL) {
+		sci_port->params = sci_probe_regmap(p);
+		if (unlikely(sci_port->params == NULL))
+			return -EINVAL;
+	}
+
 	if (unlikely(sci_port->params == NULL))
 		return -EINVAL;
 
@@ -3266,9 +3273,14 @@ static void sci_remove(struct platform_device *dev)
 		device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout);
 }
 
-#define SCI_OF_DATA(type, regtype)	(void *)((type) << 16 | (regtype))
-#define SCI_OF_TYPE(data)		((unsigned long)(data) >> 16)
-#define SCI_OF_REGTYPE(data)		((unsigned long)(data) & 0xffff)
+#define SCI_OF_DATA(_type, _regtype) (\
+&(struct sci_of_data) {\
+	.type = (_type), \
+	.regtype = (_regtype),\
+	.ops = &sci_port_ops,\
+	.uart_ops = &sci_uart_ops,\
+	.params = &sci_port_params[_regtype],\
+})
 
 static const struct of_device_id of_sci_match[] __maybe_unused = {
 	/* SoC-specific types */
@@ -3336,7 +3348,7 @@ static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
 	struct reset_control *rstc;
 	struct plat_sci_port *p;
 	struct sci_port *sp;
-	const void *data;
+	const struct sci_of_data *data;
 	int id, ret;
 
 	if (!IS_ENABLED(CONFIG_OF) || !np)
@@ -3382,8 +3394,12 @@ static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
 	sp = &sci_ports[id];
 	*dev_id = id;
 
-	p->type = SCI_OF_TYPE(data);
-	p->regtype = SCI_OF_REGTYPE(data);
+	p->type = data->type;
+	p->regtype = data->regtype;
+
+	sp->ops = data->ops;
+	sp->port.ops = data->uart_ops;
+	sp->params = data->params;
 
 	sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts");
 
@@ -3562,19 +3578,23 @@ sh_early_platform_init_buffer("earlyprintk", &sci_driver,
 static struct plat_sci_port port_cfg __initdata;
 
 int __init early_console_setup(struct earlycon_device *device,
-				      int type)
+			       const struct sci_of_data *data)
 {
 	const struct sci_common_regs *regs;
 
 	if (!device->port.membase)
 		return -ENODEV;
 
-	device->port.type = type;
+	device->port.type = data->type;
 	memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
-	port_cfg.type = type;
+
+	port_cfg.type = data->type;
+	port_cfg.regtype = data->regtype;
+
 	sci_ports[0].cfg = &port_cfg;
-	sci_ports[0].ops = &sci_port_ops;
-	sci_ports[0].params = sci_probe_regmap(&port_cfg);
+	sci_ports[0].params = data->params;
+	sci_ports[0].ops = data->ops;
+	sci_ports[0].port.ops = data->uart_ops;
 	regs = sci_ports[0].params->common_regs;
 
 	port_cfg.scscr = sci_ports[0].ops->read_reg(&sci_ports[0].port, regs->control);
@@ -3588,41 +3608,39 @@ int __init early_console_setup(struct earlycon_device *device,
 static int __init sci_early_console_setup(struct earlycon_device *device,
 					  const char *opt)
 {
-	return early_console_setup(device, PORT_SCI);
+	return early_console_setup(device, SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE));
 }
 static int __init scif_early_console_setup(struct earlycon_device *device,
 					  const char *opt)
 {
-	return early_console_setup(device, PORT_SCIF);
+	return early_console_setup(device, SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE));
 }
 static int __init rzscifa_early_console_setup(struct earlycon_device *device,
 					  const char *opt)
 {
-	port_cfg.regtype = SCIx_RZ_SCIFA_REGTYPE;
-	return early_console_setup(device, PORT_SCIF);
+	return early_console_setup(device, SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE));
 }
 
 static int __init rzv2hscif_early_console_setup(struct earlycon_device *device,
 						const char *opt)
 {
-	port_cfg.regtype = SCIx_RZV2H_SCIF_REGTYPE;
-	return early_console_setup(device, PORT_SCIF);
+	return early_console_setup(device, SCI_OF_DATA(PORT_SCIF, SCIx_RZV2H_SCIF_REGTYPE));
 }
 
 static int __init scifa_early_console_setup(struct earlycon_device *device,
 					  const char *opt)
 {
-	return early_console_setup(device, PORT_SCIFA);
+	return early_console_setup(device, SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE));
 }
 static int __init scifb_early_console_setup(struct earlycon_device *device,
 					  const char *opt)
 {
-	return early_console_setup(device, PORT_SCIFB);
+	return early_console_setup(device, SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE));
 }
 static int __init hscif_early_console_setup(struct earlycon_device *device,
 					  const char *opt)
 {
-	return early_console_setup(device, PORT_HSCIF);
+	return early_console_setup(device, SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE));
 }
 
 OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
diff --git a/drivers/tty/serial/sh-sci_common.h b/drivers/tty/serial/sh-sci_common.h
index cbfacdc1a836..f75c185079dd 100644
--- a/drivers/tty/serial/sh-sci_common.h
+++ b/drivers/tty/serial/sh-sci_common.h
@@ -172,7 +172,8 @@ extern void sci_flush_buffer(struct uart_port *port);
 #define max_sr(_port)		fls((_port)->sampling_rate_mask)
 
 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
-extern int __init early_console_setup(struct earlycon_device *device, int);
+extern int __init early_console_setup(struct earlycon_device *device,
+				      const struct sci_of_data *data);
 #endif
 
 #endif /* __SH_SCI_COMMON_H__ */
-- 
2.43.0

[PATCH 11/14] serial: sh-sci: Add support for RZ/T2H SCI

[Thierry Bultel]

Define a new RZSCI port type, and the RSCI 32 bits registers set.
The RZ/T2H SCI has a a fifo, and a quite different set of registers
from the orginal SH SCI ones.
DMA is not supported yet.

Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
---
 drivers/tty/serial/Kconfig       |   7 +
 drivers/tty/serial/Makefile      |   1 +
 drivers/tty/serial/rzsci.c       | 484 +++++++++++++++++++++++++++++++
 drivers/tty/serial/rzsci.h       |  12 +
 drivers/tty/serial/sh-sci.c      |  20 +-
 include/linux/serial_sci.h       |   3 +-
 include/uapi/linux/serial_core.h |   3 +
 7 files changed, 524 insertions(+), 6 deletions(-)
 create mode 100644 drivers/tty/serial/rzsci.c
 create mode 100644 drivers/tty/serial/rzsci.h

diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 45f0f779fbf9..72b563f2e9ba 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -671,6 +671,13 @@ config SERIAL_SH_SCI_DMA
 	depends on SERIAL_SH_SCI && DMA_ENGINE
 	default ARCH_RENESAS
 
+config SERIAL_RZ_SCI
+	tristate "Support for Renesas RZ/T2H SCI variant"
+	depends on SERIAL_SH_SCI
+	help
+	  Support for the RZ/T2H SCI variant with fifo.
+	  Say Y if you want to be able to the RZ/T2H SCI serial port.
+
 config SERIAL_HS_LPC32XX
 	tristate "LPC32XX high speed serial port support"
 	depends on ARCH_LPC32XX || COMPILE_TEST
diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile
index 6ff74f0a9530..537e0a0fc047 100644
--- a/drivers/tty/serial/Makefile
+++ b/drivers/tty/serial/Makefile
@@ -71,6 +71,7 @@ obj-$(CONFIG_SERIAL_QCOM_GENI)		+= qcom_geni_serial.o
 obj-$(CONFIG_SERIAL_QE)			+= ucc_uart.o
 obj-$(CONFIG_SERIAL_RDA)		+= rda-uart.o
 obj-$(CONFIG_SERIAL_RP2)		+= rp2.o
+obj-$(CONFIG_SERIAL_RZ_SCI)		+= rzsci.o
 obj-$(CONFIG_SERIAL_SA1100)		+= sa1100.o
 obj-$(CONFIG_SERIAL_SAMSUNG)		+= samsung_tty.o
 obj-$(CONFIG_SERIAL_SB1250_DUART)	+= sb1250-duart.o
diff --git a/drivers/tty/serial/rzsci.c b/drivers/tty/serial/rzsci.c
new file mode 100644
index 000000000000..7a6452600123
--- /dev/null
+++ b/drivers/tty/serial/rzsci.c
@@ -0,0 +1,484 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <linux/bitops.h>
+#include <linux/io.h>
+#include <linux/serial_core.h>
+#include <linux/serial_sci.h>
+#include <linux/tty_flip.h>
+#include "rzsci.h"
+
+/* RSCI registers */
+#define RDR	0x00
+#define TDR	0x04
+#define CCR0	0x08
+#define CCR1	0x0C
+#define CCR2	0x10
+#define CCR3	0x14
+#define CCR4	0x18
+#define FCR	0x24
+#define DCR	0x30
+#define CSR	0x48
+#define FRSR	0x50
+#define FTSR	0x54
+#define CFCLR	0x68
+#define FFCLR	0x70
+
+/* RDR (Receive Data Register) */
+#define RDR_FER			BIT(28)	/* Framing Error */
+#define RDR_PER			BIT(27)	/* Parity Error */
+#define RDR_ORER		BIT(24)	/* Overrun Error */
+#define RDR_FFER		BIT(12)	/* FIFO Framing Error */
+#define RDR_FPER		BIT(11)	/* FIFO Parity Error */
+#define RDR_DR			BIT(10)	/* Incoming Data Ready */
+#define RDR_MPB			BIT(9)	/* Multiprocessor Bit */
+#define	RDR_RDAT_MSK		GENMASK(8, 0)
+
+/* TDR (Transmit Data Register) */
+#define TDR_MPBT		BIT(9)	/* Multiprocessor Transfer */
+#define TDR_TDAT_9BIT_LSHIFT	0
+#define TDR_TDAT_9BIT_VAL	0x1FF
+#define	TDR_TDAT_9BIT_MSK	(TDR_TDAT_9BIT_VAL << TDR_TDAT_9BIT_LSHIFT)
+
+/* CCR0 (Common Control Register 0) */
+#define CCR0_SSE		BIT(24)	/* SSn# Pin Function Enable */
+#define CCR0_TEIE		BIT(21)	/* Transmit End Interrupt Enable */
+#define CCR0_TIE		BIT(20)	/* Transmit Interrupt Enable */
+#define CCR0_RIE		BIT(16)	/* Receive Interrupt Enable */
+#define CCR0_IDSEL		BIT(10)	/* ID Frame Select */
+#define CCR0_DCME		BIT(9)	/* Data Compare Match Enable */
+#define CCR0_MPIE		BIT(8)	/* Multiprocessor Interrupt Enable */
+#define CCR0_TE			BIT(4)	/* Transmit Enable */
+#define CCR0_RE			BIT(0)	/* Receive Enable */
+
+/* CCR1 (Common Control Register 1) */
+#define CCR1_NFEN		BIT(28)	/* Digital Noise Filter Function */
+#define CCR1_SHARPS		BIT(20)	/* Half -duplex Communication Select */
+#define CCR1_SPLP		BIT(16)	/* Loopback Control */
+#define CCR1_RINV		BIT(13)	/* RxD invert */
+#define CCR1_TINV		BIT(12)	/* TxD invert */
+#define CCR1_PM			BIT(9)	/* Parity Mode */
+#define CCR1_PE			BIT(8)	/* Parity Enable */
+#define CCR1_SPB2IO		BIT(5)	/* Serial Port Break I/O */
+#define CCR1_SPB2DT		BIT(4)	/* Serial Port Break Data Select */
+#define CCR1_CTSPEN		BIT(1)	/* CTS External Pin Enable */
+#define CCR1_CTSE		BIT(0)	/* CTS Enable */
+
+/* CCR2 (Common Control Register 2) */
+#define	CCR2_INIT		0xFF000004
+#define CCR2_CKS_TCLK		(0)	/* TCLK clock */
+#define CCR2_CKS_TCLK_DIV4	BIT(20)	/* TCLK/4 clock */
+#define CCR2_CKS_TCLK_DIV16	BIT(21)	/* TCLK16 clock */
+#define CCR2_CKS_TCLK_DIV64	(BIT(21) | BIT(20))	/* TCLK/64 clock */
+#define CCR2_BRME		BIT(16)	/* Bitrate Modulation Enable */
+#define CCR2_ABCSE		BIT(6)	/* Asynchronous Mode Extended Base Clock Select */
+#define CCR2_ABCS		BIT(5)	/* Asynchronous Mode Base Clock Select */
+#define CCR2_BGDM		BIT(4)	/* Baud Rate Generator Double-Speed Mode Select */
+
+/* CCR3 (Common Control Register 3) */
+#define	CCR3_INIT		0x1283
+#define CCR3_BLK		BIT(29)	/* Block Transfer Mode */
+#define CCR3_GM			BIT(28)	/* GSM Mode */
+#define CCR3_CKE1		BIT(25)	/* Clock Enable 1 */
+#define CCR3_CKE0		BIT(24)	/* Clock Enable 0 */
+#define CCR3_DEN		BIT(21)	/* Driver Enabled */
+#define CCR3_FM			BIT(20)	/* FIFO Mode Select */
+#define CCR3_MP			BIT(19)	/* Multi-Processor Mode */
+#define CCR3_MOD_ASYNC		0	/* Asynchronous mode (Multi-processor mode) */
+#define CCR3_RXDESEL		BIT(15)	/* Asynchronous Start Bit Edge Detection Select */
+#define CCR3_STP		BIT(14)	/* Stop bit Length */
+#define CCR3_SINV		BIT(13)	/* Transmitted/Received Data Invert */
+#define CCR3_LSBF		BIT(12)	/* LSB First select */
+#define CCR3_CHR1		BIT(9)	/* Character Length */
+#define CCR3_CHR0		BIT(8)	/* Character Length */
+#define CCR3_BPEN		BIT(7)	/* Synchronizer Bypass Enable */
+#define CCR3_CPOL		BIT(1)	/* Clock Polarity Select */
+#define CCR3_CPHA		BIT(0)	/* Clock Phase Select */
+
+/* FCR (FIFO Control Register) */
+#define FCR_RFRST		BIT(23)	/* Receive FIFO Data Register Reset */
+#define FCR_TFRST		BIT(15)	/* Transmit FIFO Data Register Reset */
+#define FCR_DRES		BIT(0)	/* Incoming Data Ready Error Select */
+#define FCR_RTRG4_0		GENMASK(20, 16)
+#define FCR_TTRG		GENMASK(12, 8)
+
+/* CSR (Common Status Register) */
+#define CSR_RDRF		BIT(31)	/* Receive Data Full */
+#define CSR_TEND		BIT(30)	/* Transmit End Flag */
+#define CSR_TDRE		BIT(29)	/* Transmit Data Empty */
+#define CSR_FER			BIT(28)	/* Framing Error */
+#define CSR_PER			BIT(27)	/* Parity Error */
+#define CSR_MFF			BIT(26)	/* Mode Fault Error */
+#define CSR_ORER		BIT(24)	/* Overrun Error */
+#define CSR_DFER		BIT(18)	/* Data Compare Match Framing Error */
+#define CSR_DPER		BIT(17)	/* Data Compare Match Parity Error */
+#define CSR_DCMF		BIT(16)	/* Data Compare Match */
+#define CSR_RXDMON		BIT(15)	/* Serial Input Data Monitor */
+#define CSR_ERS			BIT(4)	/* Error Signal Status */
+
+#define SCxSR_ERRORS(port)	(to_sci_port(port)->params->error_mask)
+#define SCxSR_ERROR_CLEAR(port)	(to_sci_port(port)->params->error_clear)
+
+#define RSCI_DEFAULT_ERROR_MASK	(CSR_PER | CSR_FER)
+
+#define RSCI_RDxF_CLEAR		(CFCLR_RDRFC)
+#define RSCI_ERROR_CLEAR	(CFCLR_PERC | CFCLR_FERC)
+#define RSCI_TDxE_CLEAR		(CFCLR_TDREC)
+#define RSCI_BREAK_CLEAR	(CFCLR_PERC | CFCLR_FERC | CFCLR_ORERC)
+
+/* FRSR (FIFO Receive Status Register) */
+#define FRSR_R5_0		GENMASK(13, 8)	/* Receive FIFO Data Count */
+#define FRSR_DR			BIT(0)	/* Receive Data Ready */
+
+/* CFCLR (Common Flag CLear Register) */
+#define CFCLR_RDRFC		BIT(31)	/* RDRF Clear */
+#define CFCLR_TDREC		BIT(29)	/* TDRE Clear */
+#define CFCLR_FERC		BIT(28)	/* FER Clear */
+#define CFCLR_PERC		BIT(27)	/* PER Clear */
+#define CFCLR_MFFC		BIT(26)	/* MFF Clear */
+#define CFCLR_ORERC		BIT(24)	/* ORER Clear */
+#define CFCLR_DFERC		BIT(18)	/* DFER Clear */
+#define CFCLR_DPERC		BIT(17)	/* DPER Clear */
+#define CFCLR_DCMFC		BIT(16)	/* DCMF Clear */
+#define CFCLR_ERSC		BIT(4)	/* ERS Clear */
+#define CFCLR_CLRFLAG		(CFCLR_RDRFC | CFCLR_FERC | CFCLR_PERC | \
+				 CFCLR_MFFC | CFCLR_ORERC | CFCLR_DFERC | \
+				 CFCLR_DPERC | CFCLR_DCMFC | CFCLR_ERSC)
+
+/* FFCLR (FIFO Flag CLear Register) */
+#define FFCLR_DRC		BIT(0)	/* DR Clear */
+
+#define DCR_DEPOL		BIT(0)
+
+static u32 rzsci_serial_in(struct uart_port *p, int offset)
+{
+	return ioread32(p->membase + offset);
+}
+
+static void rzsci_serial_out(struct uart_port *p, int offset, int value)
+{
+	iowrite32(value, p->membase + offset);
+}
+
+static void rzsci_clear_DRxC(struct uart_port *port)
+{
+	rzsci_serial_out(port, CFCLR, CFCLR_RDRFC);
+	rzsci_serial_out(port, FFCLR, FFCLR_DRC);
+}
+
+static void rzsci_clear_SCxSR(struct uart_port *port, unsigned int mask)
+{
+	rzsci_serial_out(port, CFCLR, mask);
+}
+
+static void rzsci_start_rx(struct uart_port *port)
+{
+	unsigned int ctrl;
+
+	ctrl = rzsci_serial_in(port, CCR0);
+	ctrl |= CCR0_RIE;
+	rzsci_serial_out(port, CCR0, ctrl);
+}
+
+static void rzsci_set_termios(struct uart_port *port, struct ktermios *termios,
+			      const struct ktermios *old)
+{
+	struct sci_port *s = to_sci_port(port);
+	unsigned long flags;
+
+	/*
+	 * For now, only RX enabling is supported
+	 */
+
+	sci_port_enable(s);
+	uart_port_lock_irqsave(port, &flags);
+
+	if (termios->c_cflag & CREAD)
+		rzsci_start_rx(port);
+
+	uart_port_unlock_irqrestore(port, flags);
+	sci_port_disable(s);
+}
+
+static int rzsci_txfill(struct uart_port *port)
+{
+	return rzsci_serial_in(port, FTSR);
+}
+
+static int rzsci_rxfill(struct uart_port *port)
+{
+	u32 val = rzsci_serial_in(port, FRSR);
+	return FIELD_GET(FRSR_R5_0, val);
+}
+
+static unsigned int rzsci_tx_empty(struct uart_port *port)
+{
+	unsigned int status = rzsci_serial_in(port, CSR);
+	unsigned int in_tx_fifo = rzsci_txfill(port);
+
+	return (status & CSR_TEND) && !in_tx_fifo ? TIOCSER_TEMT : 0;
+}
+
+static void rzsci_set_mctrl(struct uart_port *port, unsigned int mctrl)
+{
+	/* not supported yet */
+	return;
+}
+
+static unsigned int rzsci_get_mctrl(struct uart_port *port)
+{
+	/* not supported yet */
+	return 0;
+}
+
+static void rzsci_clear_CFC(struct uart_port *port, unsigned int mask)
+{
+	rzsci_serial_out(port, CFCLR, mask);
+}
+
+static void rzsci_start_tx(struct uart_port *port)
+{
+	struct sci_port *sp = to_sci_port(port);
+	u32 ctrl;
+
+	if (sp->chan_tx)
+		return;
+
+	/*
+	 * TE (Transmit Enable) must be set after setting TIE
+	 * (Transmit Interrupt Enable) or in the same instruction
+	 * to start the transmit process.
+	 */
+	ctrl = rzsci_serial_in(port, CCR0);
+	ctrl |= CCR0_TIE | CCR0_TE;
+	rzsci_serial_out(port, CCR0, ctrl);
+}
+
+static void rzsci_stop_tx(struct uart_port *port)
+{
+	u32 ctrl;
+
+	ctrl = rzsci_serial_in(port, CCR0);
+	ctrl &= ~CCR0_TIE;
+
+	rzsci_serial_out(port, CCR0, ctrl);
+}
+
+static void rzsci_stop_rx(struct uart_port *port)
+{
+	u32 ctrl;
+
+	ctrl = rzsci_serial_in(port, CCR0);
+	ctrl &= ~CCR0_RIE;
+
+	rzsci_serial_out(port, CCR0, ctrl);
+}
+
+static int rzsci_txroom(struct uart_port *port)
+{
+	return port->fifosize - rzsci_txfill(port);
+}
+
+static void rzsci_transmit_chars(struct uart_port *port)
+{
+	struct tty_port *tport = &port->state->port;
+	unsigned int stopped = uart_tx_stopped(port);
+	u32 status, ctrl;
+	int count;
+
+	status = rzsci_serial_in(port, CSR);
+	if (!(status & CSR_TDRE)) {
+		ctrl = rzsci_serial_in(port, CCR0);
+		if (kfifo_is_empty(&tport->xmit_fifo))
+			ctrl &= ~CCR0_TIE;
+		else
+			ctrl |= CCR0_TIE;
+		rzsci_serial_out(port, CCR0, ctrl);
+		return;
+	}
+
+	count = rzsci_txroom(port);
+
+	do {
+		unsigned char c;
+
+		if (port->x_char) {
+			c = port->x_char;
+			port->x_char = 0;
+		} else if (stopped || !kfifo_get(&tport->xmit_fifo, &c))
+			break;
+
+		rzsci_clear_CFC(port, CFCLR_TDREC);
+		rzsci_serial_out(port, TDR, c);
+
+		port->icount.tx++;
+	} while (--count > 0);
+
+	if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
+		uart_write_wakeup(port);
+
+	if (kfifo_is_empty(&tport->xmit_fifo)) {
+		ctrl = rzsci_serial_in(port, CCR0);
+		ctrl &= ~CCR0_TIE;
+		ctrl |= CCR0_TEIE;
+		rzsci_serial_out(port, CCR0, ctrl);
+	}
+}
+
+static void rzsci_receive_chars(struct uart_port *port)
+{
+	struct tty_port *tport = &port->state->port;
+	int i, count, copied = 0;
+	u32 status, frsr_status = 0;
+	unsigned char flag;
+
+	status = rzsci_serial_in(port, CSR);
+	frsr_status = rzsci_serial_in(port, FRSR);
+
+	if (!(status & CSR_RDRF) && !(frsr_status & FRSR_DR))
+		return;
+
+	while (1) {
+		/* Don't copy more bytes than there is room for in the buffer */
+		count = tty_buffer_request_room(tport, rzsci_rxfill(port));
+
+		/* If for any reason we can't copy more data, we're done! */
+		if (count == 0)
+			break;
+
+		for (i = 0; i < count; i++) {
+			char c;
+
+			status = rzsci_serial_in(port, CSR);
+			c = rzsci_serial_in(port, RDR) & RDR_RDAT_MSK;
+
+			if (uart_handle_sysrq_char(port, c)) {
+				count--;
+				i--;
+				continue;
+			}
+
+			/* Store data and status */
+			if (status & CSR_FER) {
+				flag = TTY_FRAME;
+				port->icount.frame++;
+			} else if (status & CSR_PER) {
+				flag = TTY_PARITY;
+				port->icount.parity++;
+			} else
+				flag = TTY_NORMAL;
+
+			tty_insert_flip_char(tport, c, flag);
+		}
+
+		rzsci_serial_in(port, CSR); /* dummy read */
+		rzsci_clear_DRxC(port);
+
+		copied += count;
+		port->icount.rx += count;
+	}
+
+	if (copied) {
+		/* Tell the rest of the system the news. New characters! */
+		tty_flip_buffer_push(tport);
+	} else {
+		/* TTY buffers full; read from RX reg to prevent lockup */
+		rzsci_serial_in(port, RDR);
+		rzsci_serial_in(port, CSR); /* dummy read */
+		rzsci_clear_DRxC(port);
+	}
+}
+
+static void rzsci_poll_put_char(struct uart_port *port, unsigned char c)
+{
+	u32 status;
+
+	do {
+		status = rzsci_serial_in(port, CSR);
+	} while (!(status & CSR_TDRE));
+
+	rzsci_serial_out(port, TDR, c);
+	rzsci_clear_SCxSR(port, CFCLR_TDREC);
+	return;
+}
+
+static unsigned int rzci_get_ctrl_temp(struct uart_port *port, unsigned int)
+{
+	struct sci_port *s = to_sci_port(port);
+
+	return s->params->param_bits.rxtx_enable | CCR0_TIE;
+}
+
+static const char *rzsci_type(struct uart_port *port)
+{
+	return "rzsci";
+}
+
+static const struct sci_common_regs rzsci_common_regs = {
+	.status = CSR,
+	.control = CCR0,
+};
+
+static const struct sci_port_params_bits rzsci_port_param_bits = {
+	.rxtx_enable = CCR0_RE | CCR0_TE,
+	.te_clear = CCR0_TE | CCR0_TEIE,
+	.poll_sent_bits = CSR_TDRE | CSR_TEND,
+};
+
+static const struct sci_port_params rzsci_port_params = {
+	.fifosize = 16,
+	.overrun_reg = CSR,
+	.overrun_mask = CSR_ORER,
+	.sampling_rate_mask = SCI_SR(32),
+	.error_mask = RSCI_DEFAULT_ERROR_MASK,
+	.error_clear = RSCI_ERROR_CLEAR,
+	.param_bits = rzsci_port_param_bits,
+	.common_regs = &rzsci_common_regs,
+};
+
+static const struct uart_ops rzt2_sci_uart_ops = {
+	.tx_empty	= rzsci_tx_empty,
+	.set_mctrl	= rzsci_set_mctrl,
+	.get_mctrl	= rzsci_get_mctrl,
+	.start_tx	= rzsci_start_tx,
+	.stop_tx	= rzsci_stop_tx,
+	.stop_rx	= rzsci_stop_rx,
+	.startup	= sci_startup,
+	.flush_buffer	= sci_flush_buffer,
+	.set_termios	= rzsci_set_termios,
+	.pm		= sci_pm,
+	.type		= rzsci_type,
+	.release_port	= sci_release_port,
+	.request_port	= sci_request_port,
+	.config_port	= sci_config_port,
+	.verify_port	= sci_verify_port,
+};
+
+static const struct sci_port_ops rzsci_port_ops = {
+	.read_reg		= rzsci_serial_in,
+	.write_reg		= rzsci_serial_out,
+	.clear_SCxSR		= rzsci_clear_SCxSR,
+	.transmit_chars		= rzsci_transmit_chars,
+	.receive_chars		= rzsci_receive_chars,
+	.poll_put_char		= rzsci_poll_put_char,
+	.get_ctrl_temp		= rzci_get_ctrl_temp,
+};
+
+struct sci_of_data sci_r9a09g077_data = {
+	.type = PORT_RZSCI,
+	.regtype = SCIx_RZT2H_SCI_REGTYPE,
+	.ops = &rzsci_port_ops,
+	.uart_ops = &rzt2_sci_uart_ops,
+	.params = &rzsci_port_params,
+};
+
+#ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
+
+static int __init rzt2hsci_early_console_setup(struct earlycon_device *device,
+						const char *opt)
+{
+	return early_console_setup(device, &sci_r9a09g077_data);
+}
+
+OF_EARLYCON_DECLARE(rzsci, "renesas,r9a09g077-sci", rzt2hsci_early_console_setup);
+
+#endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
diff --git a/drivers/tty/serial/rzsci.h b/drivers/tty/serial/rzsci.h
new file mode 100644
index 000000000000..2840b65e7010
--- /dev/null
+++ b/drivers/tty/serial/rzsci.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __RZT2_SCI_H__
+#define __RZT2_SCI_H__
+
+#include "sh-sci_common.h"
+
+#ifdef CONFIG_SERIAL_RZ_SCI
+extern struct sci_of_data sci_r9a09g077_data;
+#endif
+
+#endif /* __RZT2_SCI_H__ */
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index c58c0793c521..3c0e503295e9 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -54,6 +54,7 @@
 #include <asm/platform_early.h>
 #endif
 
+#include "rzsci.h"
 #include "serial_mctrl_gpio.h"
 #include "sh-sci.h"
 #include "sh-sci_common.h"
@@ -1804,7 +1805,7 @@ static irqreturn_t sci_tx_end_interrupt(int irq, void *ptr)
 	unsigned long flags;
 	u32 ctrl;
 
-	if (port->type != PORT_SCI)
+	if (port->type != PORT_SCI && port->type != PORT_RZSCI)
 		return sci_tx_interrupt(irq, ptr);
 
 	uart_port_lock_irqsave(port, &flags);
@@ -2988,10 +2989,10 @@ static int sci_init_single(struct platform_device *dev,
 	}
 
 	/*
-	 * The fourth interrupt on SCI port is transmit end interrupt, so
+	 * The fourth interrupt on SCI and RZSCI port is transmit end interrupt, so
 	 * shuffle the interrupts.
 	 */
-	if (p->type == PORT_SCI)
+	if (p->type == PORT_SCI || p->type == PORT_RZSCI)
 		swap(sci_port->irqs[SCIx_BRI_IRQ], sci_port->irqs[SCIx_TEI_IRQ]);
 
 	/* The SCI generates several interrupts. They can be muxed together or
@@ -3038,6 +3039,9 @@ static int sci_init_single(struct platform_device *dev,
 		else
 			sci_port->rx_trigger = 8;
 		break;
+	case PORT_RZSCI:
+		sci_port->rx_trigger = 15;
+		break;
 	default:
 		sci_port->rx_trigger = 1;
 		break;
@@ -3269,7 +3273,7 @@ static void sci_remove(struct platform_device *dev)
 
 	if (port->port.fifosize > 1)
 		device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger);
-	if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF)
+	if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF || type == PORT_RZSCI)
 		device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout);
 }
 
@@ -3300,6 +3304,12 @@ static const struct of_device_id of_sci_match[] __maybe_unused = {
 		.compatible = "renesas,scif-r9a09g057",
 		.data = SCI_OF_DATA(PORT_SCIF, SCIx_RZV2H_SCIF_REGTYPE),
 	},
+#ifdef CONFIG_SERIAL_RZ_SCI
+	{
+		.compatible = "renesas,r9a09g077-sci",
+		.data = &sci_r9a09g077_data,
+	},
+#endif	/* CONFIG_SERIAL_RZ_SCI */
 	/* Family-specific types */
 	{
 		.compatible = "renesas,rcar-gen1-scif",
@@ -3504,7 +3514,7 @@ static int sci_probe(struct platform_device *dev)
 			return ret;
 	}
 	if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB ||
-	    sp->port.type == PORT_HSCIF) {
+	    sp->port.type == PORT_HSCIF || sp->port.type == PORT_RZSCI) {
 		ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout);
 		if (ret) {
 			if (sp->port.fifosize > 1) {
diff --git a/include/linux/serial_sci.h b/include/linux/serial_sci.h
index 0f2f50b8d28e..787fd9a96711 100644
--- a/include/linux/serial_sci.h
+++ b/include/linux/serial_sci.h
@@ -38,6 +38,7 @@ enum {
 	SCIx_HSCIF_REGTYPE,
 	SCIx_RZ_SCIFA_REGTYPE,
 	SCIx_RZV2H_SCIF_REGTYPE,
+	SCIx_RZT2H_SCI_REGTYPE,
 
 	SCIx_NR_REGTYPES,
 };
@@ -50,7 +51,7 @@ struct plat_sci_port_ops {
  * Platform device specific platform_data struct
  */
 struct plat_sci_port {
-	unsigned int	type;			/* SCI / SCIF / IRDA / HSCIF */
+	unsigned int	type;			/* SCI / SCIF / IRDA / HSCIF / RZSCI */
 	upf_t		flags;			/* UPF_* flags */
 
 	unsigned int	sampling_rate;
diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h
index 9c007a106330..30fbbef599f4 100644
--- a/include/uapi/linux/serial_core.h
+++ b/include/uapi/linux/serial_core.h
@@ -231,6 +231,9 @@
 /* Sunplus UART */
 #define PORT_SUNPLUS	123
 
+/* SH-SCI */
+#define PORT_RZSCI	124
+
 /* Generic type identifier for ports which type is not important to userspace. */
 #define PORT_GENERIC	(-1)
 
-- 
2.43.0

[PATCH 12/14] arm64: dts: renesas: Add initial support for renesas RZ/T2H SoC

[Thierry Bultel]

Add the initial dtsi for the RZ/T2H Soc:

- gic
- armv8-timer
- cpg clock
- sci0 uart

also add arch/arm64/boot/dts/renesas/r9a09g077m44.dtsi, that keeps
all 4 CPUs enabled, for consistency with later support of -m24
and -m04 SoC revisions, that only have 2 and 1 Cortex-A55, respectively,
and that will use /delete-node/ to disable the missing CPUs.

Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a09g077.dtsi    | 129 ++++++++++++++++++
 arch/arm64/boot/dts/renesas/r9a09g077m44.dtsi |   8 ++
 2 files changed, 137 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r9a09g077.dtsi
 create mode 100644 arch/arm64/boot/dts/renesas/r9a09g077m44.dtsi

diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
new file mode 100644
index 000000000000..55a2b1bd8100
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/T2H SoC
+ *
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/clock/r9a09g077-cpg.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	compatible = "renesas,r9a09g077";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	extal: extal {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by the board */
+		clock-frequency = <0>;
+	};
+
+	loco: loco {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by the board */
+		clock-frequency = <0>;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		L3_CA55: cache-controller-0 {
+			compatible = "cache";
+			cache-unified;
+			cache-size = <0x100000>;
+			cache-level = <3>;
+		};
+
+		cpu0: cpu@0 {
+			compatible = "arm,cortex-a55";
+			reg = <0>;
+			device_type = "cpu";
+			next-level-cache = <&L3_CA55>;
+			enable-method = "psci";
+		};
+
+		cpu1: cpu@100 {
+			compatible = "arm,cortex-a55";
+			reg = <0x100>;
+			device_type = "cpu";
+			next-level-cache = <&L3_CA55>;
+			enable-method = "psci";
+		};
+
+		cpu2: cpu@200 {
+			compatible = "arm,cortex-a55";
+			reg = <0x200>;
+			device_type = "cpu";
+			next-level-cache = <&L3_CA55>;
+			enable-method = "psci";
+		};
+
+		cpu3: cpu@300 {
+			compatible = "arm,cortex-a55";
+			reg = <0x300>;
+			device_type = "cpu";
+			next-level-cache = <&L3_CA55>;
+			enable-method = "psci";
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-1.0", "arm,psci-0.2";
+		method = "smc";
+	};
+
+	soc: soc {
+		compatible = "simple-bus";
+		interrupt-parent = <&gic>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		sci0: serial@80005000 {
+			compatible = "renesas,r9a09g077-sci";
+			reg = <0 0x80005000 0 0x400>;
+			interrupts = <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 591 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 592 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "eri", "rxi", "txi", "tei";
+			clocks = <&cpg CPG_MOD R9A09G077_SCI0_CLK>;
+			clock-names = "fck";
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		cpg: clock-controller@80280000 {
+			compatible = "renesas,r9a09g077-cpg";
+			reg = <0 0x80280000 0 0x1000>,
+			      <0 0x81280000 0 0x9000>;
+			clocks = <&extal>, <&loco>;
+			clock-names = "extal", "loco";
+			#clock-cells = <2>;
+			#reset-cells = <1>;
+			#power-domain-cells = <0>;
+		};
+
+		gic: interrupt-controller@83000000 {
+			compatible = "arm,gic-v3";
+			reg = <0x0 0x83000000 0 0x40000>,
+			      <0x0 0x83040000 0 0x160000>;
+			#interrupt-cells = <3>;
+			#address-cells = <0>;
+			interrupt-controller;
+			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+};
diff --git a/arch/arm64/boot/dts/renesas/r9a09g077m44.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077m44.dtsi
new file mode 100644
index 000000000000..f54bb50829db
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a09g077m44.dtsi
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/T2H 4-core SoC
+ *
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ */
+
+#include "r9a09g077.dtsi"
-- 
2.43.0

[PATCH 13/14] arm64: dts: renesas: Add initial support for renesas RZ/T2H eval board

[Thierry Bultel]

Add the initial device tree for the RZ/T2H evaluation board.

Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/Makefile          |  1 +
 .../dts/renesas/r9a09g077m44-rzt2h-evk.dts    | 37 +++++++++++++++++++
 2 files changed, 38 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts

diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index 97228a3cb99c..422ff9ccd05e 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -140,6 +140,7 @@ dtb-$(CONFIG_ARCH_R9A08G045) += r9a08g045s33-smarc.dtb
 
 dtb-$(CONFIG_ARCH_R9A09G011) += r9a09g011-v2mevk2.dtb
 
+dtb-$(CONFIG_ARCH_R9A09G077) += r9a09g077m44-rzt2h-evk.dtb
 dtb-$(CONFIG_ARCH_R9A09G057) += r9a09g057h44-rzv2h-evk.dtb
 
 dtb-$(CONFIG_ARCH_RCAR_GEN3) += draak-ebisu-panel-aa104xd12.dtbo
diff --git a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
new file mode 100644
index 000000000000..f2b448aaec82
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/T2H Development EVK board
+ *
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+
+#include "r9a09g077m44.dtsi"
+
+/ {
+	model = "Renesas Development EVK based on r9a09g077m44";
+	compatible = "renesas,r9a9g077m44-rzt2h-evk", "renesas,r9a9g077";
+
+	aliases {
+		serial0 = &sci0;
+	};
+
+	chosen {
+		bootargs = "ignore_loglevel";
+		stdout-path = "serial0:115200n8";
+	};
+
+};
+
+&extal {
+	clock-frequency = <25000000>;
+};
+
+&loco {
+	clock-frequency = <1000000>;
+};
+
+&sci0 {
+	status = "okay";
+};
-- 
2.43.0

[PATCH 14/14] defconfig: Enable RZ/T2H Soc and RZ_SCI

[Thierry Bultel]

Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
---
 arch/arm64/configs/defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index c62831e61586..a1cc7a37386d 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -486,6 +486,7 @@ CONFIG_SERIAL_TEGRA_TCU=y
 CONFIG_SERIAL_IMX=y
 CONFIG_SERIAL_IMX_CONSOLE=y
 CONFIG_SERIAL_SH_SCI=y
+CONFIG_SERIAL_RZ_SCI=y
 CONFIG_SERIAL_MSM=y
 CONFIG_SERIAL_MSM_CONSOLE=y
 CONFIG_SERIAL_QCOM_GENI=y
@@ -1457,6 +1458,7 @@ CONFIG_ARCH_R9A07G054=y
 CONFIG_ARCH_R9A08G045=y
 CONFIG_ARCH_R9A09G011=y
 CONFIG_ARCH_R9A09G057=y
+CONFIG_ARCH_R9A09G077=y
 CONFIG_ROCKCHIP_IODOMAIN=y
 CONFIG_ARCH_TEGRA_132_SOC=y
 CONFIG_ARCH_TEGRA_210_SOC=y
-- 
2.43.0

Re: [PATCH 01/14] dt-bindings: soc: Document Renesas RZ/T2H (R9A09G077) SoC

[Krzysztof Kozlowski]

On 29/01/2025 17:37, Thierry Bultel wrote:
> Add RZ/T2H (R9A09G077) and variants in documentation.
> 
> Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
> ---
>  .../devicetree/bindings/soc/renesas/renesas.yaml          | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> index b7acb65bdecd..33f9e37a3d3d 100644
> --- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> +++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> @@ -535,6 +535,14 @@ properties:
>                - renesas,r9a09g057h44 # RZ/V2HP with Mali-G31 + Mali-C55 support
>            - const: renesas,r9a09g057
>  
> +      - description: RZ/T2H (R9A09G077)
> +        items:
> +          - enum:
> +            - renesas,r9a09g077 # RZ/T2H with Quad Cortex-A55 + Dual Cortex-R52
> +            - renesas,r9a09g077m04 # RZ/T2H with Single Cortex-A55 + Dual Cortex-R52 - no security
> +            - renesas,r9a09g077m24 # RZ/T2H with Dual Cortex-A55 + Dual Cortex-R52 - no security
> +            - renesas,r9a09g077m44 # RZ/T2H with Quad Cortex-A55 + Dual Cortex-R52 - no security

1. Never tested (see writing schema).
2. I don't quite get what this is supposed to express. There is no board
here.

Best regards,
Krzysztof

Re: [PATCH 02/14] dt-bindings: serial: Document sci bindings for the Renesas RZ/T2H (a.k.a r9a09g077) SoC

[Krzysztof Kozlowski]

On 29/01/2025 17:37, Thierry Bultel wrote:
> Document RZ/T2H (a.k.a r9a09g077) in SCI binding.

A nit, subject: drop second/last, redundant "bindings". The
"dt-bindings" prefix is already stating that these are bindings.
See also:
https://elixir.bootlin.com/linux/v6.7-rc8/source/Documentation/devicetree/bindings/submitting-patches.rst#L18

And make it anyway shorter.

> 
> Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
> ---
>  .../bindings/serial/renesas,rzsci.yaml        | 100 ++++++++++++++++++
>  1 file changed, 100 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/serial/renesas,rzsci.yaml
> 
> diff --git a/Documentation/devicetree/bindings/serial/renesas,rzsci.yaml b/Documentation/devicetree/bindings/serial/renesas,rzsci.yaml
> new file mode 100644
> index 000000000000..70e83bbcc79d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/serial/renesas,rzsci.yaml
> @@ -0,0 +1,100 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/serial/renesas,rzsci.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas Serial Communication Interface


You are duplicating existing renesas,sci without any explanation. No,
don't. This is pointless.

Best regards,
Krzysztof

Re: [PATCH 03/14] dt-bindings: soc: Document the Renesas RZ/T2H Evaluation board for the R9A09G077 SoC

[Krzysztof Kozlowski]

On 29/01/2025 17:37, Thierry Bultel wrote:
> Add the RZ/T2H Evaluation board (r9a9g077m44-dev) in documentation.
> 
> Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
> ---
>  Documentation/devicetree/bindings/soc/renesas/renesas.yaml | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> index 33f9e37a3d3d..331a007dbe35 100644
> --- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> +++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> @@ -537,6 +537,8 @@ properties:
>  
>        - description: RZ/T2H (R9A09G077)
>          items:
> +          - enum:
> +            - renesas,r9a9g077m44-dev # RZ/T2H Evaluation Board


Still not tested and previous commit makes no sense on its own.


Best regards,
Krzysztof

Re: [PATCH 04/14] dt-bindings: clock: Document cpg bindings for the Renesas RZ/T2H SoC

[Krzysztof Kozlowski]

On 29/01/2025 17:37, Thierry Bultel wrote:
> Document RZ/T2H (a.k.a r9a09g077) CPG (Clock Pulse Generator) binding.
> Add the header file for the resets and clocks definitions.
> 
> Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
> ---
>  .../bindings/clock/renesas,rzt2h-cpg.yaml     |  73 +++++++++
>  include/dt-bindings/clock/r9a09g077-cpg.h     | 144 ++++++++++++++++++
>  2 files changed, 217 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/renesas,rzt2h-cpg.yaml
>  create mode 100644 include/dt-bindings/clock/r9a09g077-cpg.h
> 
> diff --git a/Documentation/devicetree/bindings/clock/renesas,rzt2h-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzt2h-cpg.yaml
> new file mode 100644
> index 000000000000..9a3a00126d2b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/renesas,rzt2h-cpg.yaml
> @@ -0,0 +1,73 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/renesas,rzt2h-cpg.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas RZ/T2H(P) Clock Pulse Generator (CPG)
> +
> +maintainers:
> +  - Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
> +
> +description:
> +  On Renesas RZ/T2H SoCs, the CPG (Clock Pulse Generator) handles generation
> +  and control of clock signals for the IP modules, generation and control of resets,

Wrap at 80. See Coding style doc.

> +  and control over booting, low power consumption and power supply domains.
> +
> +properties:
> +  compatible:
> +    const: renesas,r9a09g077-cpg

...

> +#define R9A09G077_SHOSTIF_MASTER_RST	13
> +#define R9A09G077_SHOSTIF_SLAVE_RST	14
> +#define R9A09G077_SHOSTIF_IP_RST	15
> +#define R9A09G077_DDRSS_RST_N_RST	16
> +#define R9A09G077_DDRSS_PWROKIN_RST	17
> +#define R9A09G077_DDRSS_RST_RST		18
> +#define R9A09G077_DDRSS_AXI0_RST	19
> +#define R9A09G077_DDRSS_AXI1_RST	20
> +#define R9A09G077_DDRSS_AXI2_RST	21
> +#define R9A09G077_DDRSS_AXI3_RST	22
> +#define R9A09G077_DDRSS_AXI4_RST	23
> +#define R9A09G077_DDRSS_MC_RST		24
> +#define R9A09G077_PCIE_RST		25
> +#define R9A09G077_DDRSS_PHY_RST		26
> +
> +#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ */
> \ No newline at end of file

Patch warning here.


Best regards,
Krzysztof

Re: [PATCH 12/14] arm64: dts: renesas: Add initial support for renesas RZ/T2H SoC

[Krzysztof Kozlowski]

On 29/01/2025 17:37, Thierry Bultel wrote:
> Add the initial dtsi for the RZ/T2H Soc:
> 
> - gic
> - armv8-timer
> - cpg clock
> - sci0 uart
> 
> also add arch/arm64/boot/dts/renesas/r9a09g077m44.dtsi, that keeps
> all 4 CPUs enabled, for consistency with later support of -m24
> and -m04 SoC revisions, that only have 2 and 1 Cortex-A55, respectively,
> and that will use /delete-node/ to disable the missing CPUs.
> 
> Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
> ---
>  arch/arm64/boot/dts/renesas/r9a09g077.dtsi    | 129 ++++++++++++++++++
>  arch/arm64/boot/dts/renesas/r9a09g077m44.dtsi |   8 ++
>  2 files changed, 137 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/renesas/r9a09g077.dtsi
>  create mode 100644 arch/arm64/boot/dts/renesas/r9a09g077m44.dtsi
> 
> diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
> new file mode 100644
> index 000000000000..55a2b1bd8100
> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
> @@ -0,0 +1,129 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Device Tree Source for the RZ/T2H SoC
> + *
> + * Copyright (C) 2025 Renesas Electronics Corp.
> + */
> +
> +#include <dt-bindings/clock/r9a09g077-cpg.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> +	compatible = "renesas,r9a09g077";
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	extal: extal {

Use some generic clock names, prefixes or suffixes.

> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		/* This value must be overridden by the board */
> +		clock-frequency = <0>;
> +	};
> +
> +	loco: loco {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		/* This value must be overridden by the board */
> +		clock-frequency = <0>;
> +	};
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		L3_CA55: cache-controller-0 {

Labels are lowercase.

> +			compatible = "cache";
> +			cache-unified;
> +			cache-size = <0x100000>;
> +			cache-level = <3>;
> +		};

...

> diff --git a/arch/arm64/boot/dts/renesas/r9a09g077m44.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077m44.dtsi
> new file mode 100644
> index 000000000000..f54bb50829db
> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/r9a09g077m44.dtsi
> @@ -0,0 +1,8 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Device Tree Source for the RZ/T2H 4-core SoC
> + *
> + * Copyright (C) 2025 Renesas Electronics Corp.
> + */
> +
> +#include "r9a09g077.dtsi"


What is the point of this DTSI file? What is the point of your top-level
compatibles if you do not use them?


Best regards,
Krzysztof

Re: [PATCH 13/14] arm64: dts: renesas: Add initial support for renesas RZ/T2H eval board

[Krzysztof Kozlowski]

On 29/01/2025 17:37, Thierry Bultel wrote:
> diff --git a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
> new file mode 100644
> index 000000000000..f2b448aaec82
> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
> @@ -0,0 +1,37 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Device Tree Source for the RZ/T2H Development EVK board
> + *
> + * Copyright (C) 2025 Renesas Electronics Corp.
> + */
> +
> +/dts-v1/;
> +
> +#include "r9a09g077m44.dtsi"
> +
> +/ {
> +	model = "Renesas Development EVK based on r9a09g077m44";
> +	compatible = "renesas,r9a9g077m44-rzt2h-evk", "renesas,r9a9g077";
> +
> +	aliases {
> +		serial0 = &sci0;
> +	};
> +
> +	chosen {
> +		bootargs = "ignore_loglevel";

Drop, that's development, not wide-mainline use.

> +		stdout-path = "serial0:115200n8";
> +	};
> +

Stray blank line.



Best regards,
Krzysztof

Re: [PATCH 14/14] defconfig: Enable RZ/T2H Soc and RZ_SCI

[Krzysztof Kozlowski]

On 29/01/2025 17:37, Thierry Bultel wrote:
> Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
> ---
>  arch/arm64/configs/defconfig | 2 ++
>  1 file changed, 2 insertions(+)
> 


Cc list does not look here correct. Actually for entire set is not
correct. You should always Cc your soc maintainers.


> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
> index c62831e61586..a1cc7a37386d 100644
> --- a/arch/arm64/configs/defconfig
> +++ b/arch/arm64/configs/defconfig
> @@ -486,6 +486,7 @@ CONFIG_SERIAL_TEGRA_TCU=y
>  CONFIG_SERIAL_IMX=y
>  CONFIG_SERIAL_IMX_CONSOLE=y
>  CONFIG_SERIAL_SH_SCI=y
> +CONFIG_SERIAL_RZ_SCI=y
>  CONFIG_SERIAL_MSM=y
>  CONFIG_SERIAL_MSM_CONSOLE=y
>  CONFIG_SERIAL_QCOM_GENI=y
> @@ -1457,6 +1458,7 @@ CONFIG_ARCH_R9A07G054=y
>  CONFIG_ARCH_R9A08G045=y
>  CONFIG_ARCH_R9A09G011=y
>  CONFIG_ARCH_R9A09G057=y
> +CONFIG_ARCH_R9A09G077=y

Folks, you need to stop adding user-selectable SoC-choices. This is
really odd for arm64, like some old arm32 style. None of the platforms
do it, including much, much bigger ones like Qualcomm.

The defconfig is supposed to select only top-level ARCH for given vendor
or family of devices.

$ git grep ARCH_R[89] -- arch/arm64/configs/defconfig | wc -l
23


Best regards,
Krzysztof

Re: [PATCH 02/14] dt-bindings: serial: Document sci bindings for the Renesas RZ/T2H (a.k.a r9a09g077) SoC

[Krzysztof Kozlowski]

On Wed, Jan 29, 2025 at 07:31:04PM +0100, Krzysztof Kozlowski wrote:
> On 29/01/2025 17:37, Thierry Bultel wrote:
> > Document RZ/T2H (a.k.a r9a09g077) in SCI binding.
> 
> A nit, subject: drop second/last, redundant "bindings". The
> "dt-bindings" prefix is already stating that these are bindings.
> See also:
> https://elixir.bootlin.com/linux/v6.7-rc8/source/Documentation/devicetree/bindings/submitting-patches.rst#L18
> 
> And make it anyway shorter.
> 
> > 
> > Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
> > ---
> >  .../bindings/serial/renesas,rzsci.yaml        | 100 ++++++++++++++++++
> >  1 file changed, 100 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/serial/renesas,rzsci.yaml
> > 
> > diff --git a/Documentation/devicetree/bindings/serial/renesas,rzsci.yaml b/Documentation/devicetree/bindings/serial/renesas,rzsci.yaml
> > new file mode 100644
> > index 000000000000..70e83bbcc79d
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/serial/renesas,rzsci.yaml
> > @@ -0,0 +1,100 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/serial/renesas,rzsci.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Renesas Serial Communication Interface
> 
> 
> You are duplicating existing renesas,sci without any explanation. No,
> don't. This is pointless.


... and this wasn't tested either. :/

Best regards,
Krzysztof

Re: [PATCH 03/14] dt-bindings: soc: Document the Renesas RZ/T2H Evaluation board for the R9A09G077 SoC

[Krzysztof Kozlowski]

On Wed, 29 Jan 2025 16:37:39 +0000, Thierry Bultel wrote:
> Add the RZ/T2H Evaluation board (r9a9g077m44-dev) in documentation.
> 
> Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
> ---
>  Documentation/devicetree/bindings/soc/renesas/renesas.yaml | 2 ++
>  1 file changed, 2 insertions(+)
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:
./Documentation/devicetree/bindings/soc/renesas/renesas.yaml:543:13: [warning] wrong indentation: expected 14 but found 12 (indentation)

dtschema/dtc warnings/errors:

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/patch/2040353

This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.

Re: [PATCH 02/14] dt-bindings: serial: Document sci bindings for the Renesas RZ/T2H (a.k.a r9a09g077) SoC

[Krzysztof Kozlowski]

On Wed, 29 Jan 2025 16:37:38 +0000, Thierry Bultel wrote:
> Document RZ/T2H (a.k.a r9a09g077) in SCI binding.
> 
> Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
> ---
>  .../bindings/serial/renesas,rzsci.yaml        | 100 ++++++++++++++++++
>  1 file changed, 100 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/serial/renesas,rzsci.yaml
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/serial/renesas,rzsci.example.dts:24:18: fatal error: dt-bindings/clock/r9a09g077-cpg.h: No such file or directory
   24 |         #include <dt-bindings/clock/r9a09g077-cpg.h>
      |                  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[2]: *** [scripts/Makefile.dtbs:131: Documentation/devicetree/bindings/serial/renesas,rzsci.example.dtb] Error 1
make[2]: *** Waiting for unfinished jobs....
make[1]: *** [/builds/robherring/dt-review-ci/linux/Makefile:1506: dt_binding_check] Error 2
make: *** [Makefile:251: __sub-make] Error 2

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/patch/2040352

This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.

Re: [PATCH 08/14] serial: sh-sci: Fix a comment about SCIFA

[Geert Uytterhoeven]

CC linux-renesas-soc

On Wed, 29 Jan 2025 at 17:54, Thierry Bultel
<thierry.bultel.yh@bp.renesas.com> wrote:
>
> RZ/T1 has SCIFA, 'T' is not relevant.
>
> Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
> ---
>  drivers/tty/serial/sh-sci.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
> index 924b803af440..5ba25a6a5432 100644
> --- a/drivers/tty/serial/sh-sci.c
> +++ b/drivers/tty/serial/sh-sci.c
> @@ -291,7 +291,7 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
>         },
>
>         /*
> -        * The "SCIFA" that is in RZ/A2, RZ/G2L and RZ/T.
> +        * The "SCIFA" that is in RZ/A2, RZ/G2L and RZ/T1
>          * It looks like a normal SCIF with FIFO data, but with a
>          * compressed address space. Also, the break out of interrupts
>          * are different: ERI/BRI, RXI, TXI, TEI, DRI.
> --
> 2.43.0

Re: [PATCH 09/14] serial: sh-sci: Introduced function pointers

[Geert Uytterhoeven]

CC linux-renesas-soc

On Wed, 29 Jan 2025 at 18:03, Thierry Bultel
<thierry.bultel.yh@bp.renesas.com> wrote:
> The aim here is to prepare support for new sci controllers like
> the T2H/RSCI whose registers are too much different for being
> handled in common code.
>
> This named serial controller also has 32 bits register,
> so some return types had to be changed.
>
> The needed generic functions are no longer static, with prototypes
> defined in sh-sci-common.h so that they can be used from specific
> implementation in a separate file, to keep this driver as little
> changed as possible.
>
> For doing so, a set of 'ops' is added to struct sci_port.
>
> Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
> ---
>  drivers/tty/serial/sh-sci.c        | 339 +++++++++++++++--------------
>  drivers/tty/serial/sh-sci_common.h | 178 +++++++++++++++
>  2 files changed, 349 insertions(+), 168 deletions(-)
>  create mode 100644 drivers/tty/serial/sh-sci_common.h
>
> diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
> index 5ba25a6a5432..1b83a246c7ed 100644
> --- a/drivers/tty/serial/sh-sci.c
> +++ b/drivers/tty/serial/sh-sci.c
> @@ -56,19 +56,7 @@
>
>  #include "serial_mctrl_gpio.h"
>  #include "sh-sci.h"
> -
> -/* Offsets into the sci_port->irqs array */
> -enum {
> -       SCIx_ERI_IRQ,
> -       SCIx_RXI_IRQ,
> -       SCIx_TXI_IRQ,
> -       SCIx_BRI_IRQ,
> -       SCIx_DRI_IRQ,
> -       SCIx_TEI_IRQ,
> -       SCIx_NR_IRQS,
> -
> -       SCIx_MUX_IRQ = SCIx_NR_IRQS,    /* special case */
> -};
> +#include "sh-sci_common.h"
>
>  #define SCIx_IRQ_IS_MUXED(port)                        \
>         ((port)->irqs[SCIx_ERI_IRQ] ==  \
> @@ -76,101 +64,39 @@ enum {
>         ((port)->irqs[SCIx_ERI_IRQ] &&  \
>          ((port)->irqs[SCIx_RXI_IRQ] < 0))
>
> -enum SCI_CLKS {
> -       SCI_FCK,                /* Functional Clock */
> -       SCI_SCK,                /* Optional External Clock */
> -       SCI_BRG_INT,            /* Optional BRG Internal Clock Source */
> -       SCI_SCIF_CLK,           /* Optional BRG External Clock Source */
> -       SCI_NUM_CLKS
> -};
> -
> -/* Bit x set means sampling rate x + 1 is supported */
> -#define SCI_SR(x)              BIT((x) - 1)
>  #define SCI_SR_RANGE(x, y)     GENMASK((y) - 1, (x) - 1)
>
>  #define SCI_SR_SCIFAB          SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
>                                 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
>                                 SCI_SR(19) | SCI_SR(27)
>
> -#define min_sr(_port)          ffs((_port)->sampling_rate_mask)
> -#define max_sr(_port)          fls((_port)->sampling_rate_mask)
> -
>  /* Iterate over all supported sampling rates, from high to low */
>  #define for_each_sr(_sr, _port)                                                \
>         for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--)    \
>                 if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
>
> -struct plat_sci_reg {
> -       u8 offset, size;
> -};
> -
> -struct sci_port_params {
> -       const struct plat_sci_reg regs[SCIx_NR_REGS];
> -       unsigned int fifosize;
> -       unsigned int overrun_reg;
> -       unsigned int overrun_mask;
> -       unsigned int sampling_rate_mask;
> -       unsigned int error_mask;
> -       unsigned int error_clear;
> -};
> -
> -struct sci_port {
> -       struct uart_port        port;
> -
> -       /* Platform configuration */
> -       const struct sci_port_params *params;
> -       const struct plat_sci_port *cfg;
> -       unsigned int            sampling_rate_mask;
> -       resource_size_t         reg_size;
> -       struct mctrl_gpios      *gpios;
> -
> -       /* Clocks */
> -       struct clk              *clks[SCI_NUM_CLKS];
> -       unsigned long           clk_rates[SCI_NUM_CLKS];
> -
> -       int                     irqs[SCIx_NR_IRQS];
> -       char                    *irqstr[SCIx_NR_IRQS];
> -
> -       struct dma_chan                 *chan_tx;
> -       struct dma_chan                 *chan_rx;
> -
> -#ifdef CONFIG_SERIAL_SH_SCI_DMA
> -       struct dma_chan                 *chan_tx_saved;
> -       struct dma_chan                 *chan_rx_saved;
> -       dma_cookie_t                    cookie_tx;
> -       dma_cookie_t                    cookie_rx[2];
> -       dma_cookie_t                    active_rx;
> -       dma_addr_t                      tx_dma_addr;
> -       unsigned int                    tx_dma_len;
> -       struct scatterlist              sg_rx[2];
> -       void                            *rx_buf[2];
> -       size_t                          buf_len_rx;
> -       struct work_struct              work_tx;
> -       struct hrtimer                  rx_timer;
> -       unsigned int                    rx_timeout;     /* microseconds */
> -#endif
> -       unsigned int                    rx_frame;
> -       int                             rx_trigger;
> -       struct timer_list               rx_fifo_timer;
> -       int                             rx_fifo_timeout;
> -       u16                             hscif_tot;
> -
> -       bool has_rtscts;
> -       bool autorts;
> -       bool tx_occurred;
> -};
> -
>  #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
>
>  static struct sci_port sci_ports[SCI_NPORTS];
>  static unsigned long sci_ports_in_use;
>  static struct uart_driver sci_uart_driver;
>
> -static inline struct sci_port *
> -to_sci_port(struct uart_port *uart)
> -{
> -       return container_of(uart, struct sci_port, port);
> -}
> +static const struct sci_port_params_bits sci_sci_port_params_bits = {
> +       .rxtx_enable = SCSCR_RE | SCSCR_TE,
> +       .te_clear = SCSCR_TE | SCSCR_TEIE,
> +       .poll_sent_bits = SCI_FER | SCI_TEND
> +};
> +
> +static const struct sci_port_params_bits sci_scix_port_params_bits = {
> +       .rxtx_enable = SCSCR_RE | SCSCR_TE,
> +       .te_clear = SCSCR_TE | SCSCR_TEIE,
> +       .poll_sent_bits = SCIF_TDFE | SCIF_TEND
> +};
> +
> +static const struct sci_common_regs sci_common_regs = {
> +       .status = SCxSR,
> +       .control = SCSCR,
> +};
>
>  static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
>         /*
> @@ -192,6 +118,8 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
>                 .sampling_rate_mask = SCI_SR(32),
>                 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
>                 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
> +               .param_bits = sci_sci_port_params_bits,
> +               .common_regs = &sci_common_regs,
>         },
>
>         /*
> @@ -214,6 +142,8 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
>                 .sampling_rate_mask = SCI_SR(32),
>                 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
>                 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
> +               .param_bits = sci_scix_port_params_bits,
> +               .common_regs = &sci_common_regs,
>         },
>
>         /*
> @@ -238,6 +168,8 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
>                 .sampling_rate_mask = SCI_SR_SCIFAB,
>                 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
>                 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
> +               .param_bits = sci_scix_port_params_bits,
> +               .common_regs = &sci_common_regs,
>         },
>
>         /*
> @@ -263,6 +195,8 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
>                 .sampling_rate_mask = SCI_SR_SCIFAB,
>                 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
>                 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
> +               .param_bits = sci_scix_port_params_bits,
> +               .common_regs = &sci_common_regs,
>         },
>
>         /*
> @@ -288,6 +222,8 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
>                 .sampling_rate_mask = SCI_SR(32),
>                 .error_mask = SCIF_DEFAULT_ERROR_MASK,
>                 .error_clear = SCIF_ERROR_CLEAR,
> +               .param_bits = sci_scix_port_params_bits,
> +               .common_regs = &sci_common_regs,
>         },
>
>         /*
> @@ -316,6 +252,8 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
>                 .sampling_rate_mask = SCI_SR(32),
>                 .error_mask = SCIF_DEFAULT_ERROR_MASK,
>                 .error_clear = SCIF_ERROR_CLEAR,
> +               .param_bits = sci_scix_port_params_bits,
> +               .common_regs = &sci_common_regs,
>         },
>
>         /*
> @@ -347,6 +285,8 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
>                 .sampling_rate_mask = SCI_SR(32),
>                 .error_mask = SCIF_DEFAULT_ERROR_MASK,
>                 .error_clear = SCIF_ERROR_CLEAR,
> +               .param_bits = sci_scix_port_params_bits,
> +               .common_regs = &sci_common_regs,
>         },
>
>         /*
> @@ -369,6 +309,8 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
>                 .sampling_rate_mask = SCI_SR(32),
>                 .error_mask = SCIF_DEFAULT_ERROR_MASK,
>                 .error_clear = SCIF_ERROR_CLEAR,
> +               .param_bits = sci_scix_port_params_bits,
> +               .common_regs = &sci_common_regs,
>         },
>
>         /*
> @@ -393,6 +335,8 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
>                 .sampling_rate_mask = SCI_SR(32),
>                 .error_mask = SCIF_DEFAULT_ERROR_MASK,
>                 .error_clear = SCIF_ERROR_CLEAR,
> +               .param_bits = sci_scix_port_params_bits,
> +               .common_regs = &sci_common_regs,
>         },
>
>         /*
> @@ -420,6 +364,8 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
>                 .sampling_rate_mask = SCI_SR(32),
>                 .error_mask = SCIF_DEFAULT_ERROR_MASK,
>                 .error_clear = SCIF_ERROR_CLEAR,
> +               .param_bits = sci_scix_port_params_bits,
> +               .common_regs = &sci_common_regs,
>         },
>
>         /*
> @@ -449,6 +395,8 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
>                 .sampling_rate_mask = SCI_SR_RANGE(8, 32),
>                 .error_mask = SCIF_DEFAULT_ERROR_MASK,
>                 .error_clear = SCIF_ERROR_CLEAR,
> +               .param_bits = sci_scix_port_params_bits,
> +               .common_regs = &sci_common_regs,
>         },
>
>         /*
> @@ -473,6 +421,8 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
>                 .sampling_rate_mask = SCI_SR(32),
>                 .error_mask = SCIF_DEFAULT_ERROR_MASK,
>                 .error_clear = SCIF_ERROR_CLEAR,
> +               .param_bits = sci_scix_port_params_bits,
> +               .common_regs = &sci_common_regs,
>         },
>
>         /*
> @@ -500,6 +450,8 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
>                 .sampling_rate_mask = SCI_SR(32),
>                 .error_mask = SCIF_DEFAULT_ERROR_MASK,
>                 .error_clear = SCIF_ERROR_CLEAR,
> +               .param_bits = sci_scix_port_params_bits,
> +               .common_regs = &sci_common_regs,
>         },
>
>         /*
> @@ -523,6 +475,8 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
>                 .sampling_rate_mask = SCI_SR(16),
>                 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
>                 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
> +               .param_bits = sci_scix_port_params_bits,
> +               .common_regs = &sci_common_regs,
>         },
>  };
>
> @@ -560,7 +514,7 @@ static void sci_serial_out(struct uart_port *p, int offset, int value)
>                 WARN(1, "Invalid register access\n");
>  }
>
> -static void sci_port_enable(struct sci_port *sci_port)
> +void sci_port_enable(struct sci_port *sci_port)
>  {
>         unsigned int i;
>
> @@ -576,7 +530,7 @@ static void sci_port_enable(struct sci_port *sci_port)
>         sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
>  }
>
> -static void sci_port_disable(struct sci_port *sci_port)
> +void sci_port_disable(struct sci_port *sci_port)
>  {
>         unsigned int i;
>
> @@ -713,15 +667,16 @@ static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
>      defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
>
>  #ifdef CONFIG_CONSOLE_POLL
> -static int sci_poll_get_char(struct uart_port *port)
> +int sci_poll_get_char(struct uart_port *port)
>  {
>         unsigned short status;
> +       struct sci_port *s = to_sci_port(port);
>         int c;
>
>         do {
>                 status = sci_serial_in(port, SCxSR);
>                 if (status & SCxSR_ERRORS(port)) {
> -                       sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
> +                       s->ops->clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
>                         continue;
>                 }
>                 break;
> @@ -734,7 +689,7 @@ static int sci_poll_get_char(struct uart_port *port)
>
>         /* Dummy read */
>         sci_serial_in(port, SCxSR);
> -       sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
> +       s->ops->clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
>
>         return c;
>  }
> @@ -742,14 +697,16 @@ static int sci_poll_get_char(struct uart_port *port)
>
>  static void sci_poll_put_char(struct uart_port *port, unsigned char c)
>  {
> -       unsigned short status;
> +       struct sci_port *s = to_sci_port(port);
> +       const struct sci_common_regs *regs = s->params->common_regs;
> +       unsigned int status;
>
>         do {
> -               status = sci_serial_in(port, SCxSR);
> +               status = s->ops->read_reg(port, regs->status);
>         } while (!(status & SCxSR_TDxE(port)));
>
>         sci_serial_out(port, SCxTDR, c);
> -       sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
> +       s->ops->clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
>  }
>  #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE ||
>           CONFIG_SERIAL_SH_SCI_EARLYCON */
> @@ -892,7 +849,7 @@ static void sci_transmit_chars(struct uart_port *port)
>                 port->icount.tx++;
>         } while (--count > 0);
>
> -       sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
> +       s->ops->clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
>
>         if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
>                 uart_write_wakeup(port);
> @@ -911,6 +868,7 @@ static void sci_transmit_chars(struct uart_port *port)
>  static void sci_receive_chars(struct uart_port *port)
>  {
>         struct tty_port *tport = &port->state->port;
> +       struct sci_port *s = to_sci_port(port);
>         int i, count, copied = 0;
>         unsigned short status;
>         unsigned char flag;
> @@ -965,7 +923,7 @@ static void sci_receive_chars(struct uart_port *port)
>                 }
>
>                 sci_serial_in(port, SCxSR); /* dummy read */
> -               sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
> +               s->ops->clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
>
>                 copied += count;
>                 port->icount.rx += count;
> @@ -978,16 +936,17 @@ static void sci_receive_chars(struct uart_port *port)
>                 /* TTY buffers full; read from RX reg to prevent lockup */
>                 sci_serial_in(port, SCxRDR);
>                 sci_serial_in(port, SCxSR); /* dummy read */
> -               sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
> +               s->ops->clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
>         }
>  }
>
>  static int sci_handle_errors(struct uart_port *port)
>  {
>         int copied = 0;
> -       unsigned short status = sci_serial_in(port, SCxSR);
> -       struct tty_port *tport = &port->state->port;
>         struct sci_port *s = to_sci_port(port);
> +       const struct sci_common_regs *regs = s->params->common_regs;
> +       unsigned int status = s->ops->read_reg(port, regs->status);
> +       struct tty_port *tport = &port->state->port;
>
>         /* Handle overruns */
>         if (status & s->params->overrun_mask) {
> @@ -1146,7 +1105,7 @@ static void rx_fifo_timer_fn(struct timer_list *t)
>         struct uart_port *port = &s->port;
>
>         dev_dbg(port->dev, "Rx timed out\n");
> -       scif_set_rtrg(port, 1);
> +       s->ops->set_rtrg(port, 1);
>  }
>
>  static ssize_t rx_fifo_trigger_show(struct device *dev,
> @@ -1171,9 +1130,9 @@ static ssize_t rx_fifo_trigger_store(struct device *dev,
>         if (ret)
>                 return ret;
>
> -       sci->rx_trigger = scif_set_rtrg(port, r);
> +       sci->rx_trigger = sci->ops->set_rtrg(port, r);
>         if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
> -               scif_set_rtrg(port, 1);
> +               sci->ops->set_rtrg(port, 1);
>
>         return count;
>  }
> @@ -1216,7 +1175,7 @@ static ssize_t rx_fifo_timeout_store(struct device *dev,
>                 sci->hscif_tot = r << HSSCR_TOT_SHIFT;
>         } else {
>                 sci->rx_fifo_timeout = r;
> -               scif_set_rtrg(port, 1);
> +               sci->ops->set_rtrg(port, 1);
>                 if (r > 0)
>                         timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0);
>         }
> @@ -1341,7 +1300,7 @@ static void sci_dma_rx_reenable_irq(struct sci_port *s)
>             s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
>                 enable_irq(s->irqs[SCIx_RXI_IRQ]);
>                 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE)
> -                       scif_set_rtrg(port, s->rx_trigger);
> +                       s->ops->set_rtrg(port, s->rx_trigger);
>                 else
>                         scr &= ~SCSCR_RDRQE;
>         }
> @@ -1623,7 +1582,7 @@ static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
>         return chan;
>  }
>
> -static void sci_request_dma(struct uart_port *port)
> +void sci_request_dma(struct uart_port *port)
>  {
>         struct sci_port *s = to_sci_port(port);
>         struct tty_port *tport = &port->state->port;
> @@ -1711,7 +1670,7 @@ static void sci_request_dma(struct uart_port *port)
>         }
>  }
>
> -static void sci_free_dma(struct uart_port *port)
> +void sci_free_dma(struct uart_port *port)
>  {
>         struct sci_port *s = to_sci_port(port);
>
> @@ -1721,7 +1680,7 @@ static void sci_free_dma(struct uart_port *port)
>                 sci_dma_rx_release(s);
>  }
>
> -static void sci_flush_buffer(struct uart_port *port)
> +void sci_flush_buffer(struct uart_port *port)
>  {
>         struct sci_port *s = to_sci_port(port);
>
> @@ -1750,11 +1709,11 @@ static void sci_dma_check_tx_occurred(struct sci_port *s)
>                 s->tx_occurred = true;
>  }
>  #else /* !CONFIG_SERIAL_SH_SCI_DMA */
> -static inline void sci_request_dma(struct uart_port *port)
> +inline void sci_request_dma(struct uart_port *port)
>  {
>  }
>
> -static inline void sci_free_dma(struct uart_port *port)
> +inline void sci_free_dma(struct uart_port *port)
>  {
>  }
>
> @@ -1762,7 +1721,9 @@ static void sci_dma_check_tx_occurred(struct sci_port *s)
>  {
>  }
>
> -#define sci_flush_buffer       NULL
> +inline void sci_flush_buffer(struct uart_port *port)
> +{
> +}
>  #endif /* !CONFIG_SERIAL_SH_SCI_DMA */
>
>  static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
> @@ -1780,7 +1741,7 @@ static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
>                     s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
>                         disable_irq_nosync(s->irqs[SCIx_RXI_IRQ]);
>                         if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
> -                               scif_set_rtrg(port, 1);
> +                               s->ops->set_rtrg(port, 1);
>                                 scr |= SCSCR_RIE;
>                         } else {
>                                 scr |= SCSCR_RDRQE;
> @@ -1806,8 +1767,8 @@ static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
>  #endif
>
>         if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) {
> -               if (!scif_rtrg_enabled(port))
> -                       scif_set_rtrg(port, s->rx_trigger);
> +               if (!s->ops->rtrg_enabled(port))
> +                       s->ops->set_rtrg(port, s->rx_trigger);
>
>                 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP(
>                           s->rx_frame * HZ * s->rx_fifo_timeout, 1000000));
> @@ -1817,7 +1778,7 @@ static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
>          * of whether the I_IXOFF is set, otherwise, how is the interrupt
>          * to be disabled?
>          */
> -       sci_receive_chars(port);
> +       s->ops->receive_chars(port);
>
>         return IRQ_HANDLED;
>  }
> @@ -1826,9 +1787,10 @@ static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
>  {
>         struct uart_port *port = ptr;
>         unsigned long flags;
> +       struct sci_port *s = to_sci_port(port);
>
>         uart_port_lock_irqsave(port, &flags);
> -       sci_transmit_chars(port);
> +       s->ops->transmit_chars(port);
>         uart_port_unlock_irqrestore(port, flags);
>
>         return IRQ_HANDLED;
> @@ -1837,16 +1799,19 @@ static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
>  static irqreturn_t sci_tx_end_interrupt(int irq, void *ptr)
>  {
>         struct uart_port *port = ptr;
> +       struct sci_port *s = to_sci_port(port);
> +       const struct sci_common_regs *regs = s->params->common_regs;
>         unsigned long flags;
> -       unsigned short ctrl;
> +       u32 ctrl;
>
>         if (port->type != PORT_SCI)
>                 return sci_tx_interrupt(irq, ptr);
>
>         uart_port_lock_irqsave(port, &flags);
> -       ctrl = sci_serial_in(port, SCSCR);
> -       ctrl &= ~(SCSCR_TE | SCSCR_TEIE);
> -       sci_serial_out(port, SCSCR, ctrl);
> +       ctrl = s->ops->read_reg(port, regs->control);
> +
> +       ctrl &= ~(s->params->param_bits.te_clear);
> +       s->ops->write_reg(port, regs->control, ctrl);
>         uart_port_unlock_irqrestore(port, flags);
>
>         return IRQ_HANDLED;
> @@ -1855,6 +1820,7 @@ static irqreturn_t sci_tx_end_interrupt(int irq, void *ptr)
>  static irqreturn_t sci_br_interrupt(int irq, void *ptr)
>  {
>         struct uart_port *port = ptr;
> +       struct sci_port *s = to_sci_port(port);
>
>         /* Handle BREAKs */
>         sci_handle_breaks(port);
> @@ -1862,7 +1828,7 @@ static irqreturn_t sci_br_interrupt(int irq, void *ptr)
>         /* drop invalid character received before break was detected */
>         sci_serial_in(port, SCxRDR);
>
> -       sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
> +       s->ops->clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
>
>         return IRQ_HANDLED;
>  }
> @@ -1890,15 +1856,15 @@ static irqreturn_t sci_er_interrupt(int irq, void *ptr)
>                 if (sci_handle_errors(port)) {
>                         /* discard character in rx buffer */
>                         sci_serial_in(port, SCxSR);
> -                       sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
> +                       s->ops->clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
>                 }
>         } else {
>                 sci_handle_fifo_overrun(port);
>                 if (!s->chan_rx)
> -                       sci_receive_chars(port);
> +                       s->ops->receive_chars(port);
>         }
>
> -       sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
> +       s->ops->clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
>
>         /* Kick the transmission */
>         if (!s->chan_tx)
> @@ -2059,7 +2025,7 @@ static int sci_request_irq(struct sci_port *port)
>         return ret;
>  }
>
> -static void sci_free_irq(struct sci_port *port)
> +void sci_free_irq(struct sci_port *port)
>  {
>         int i, j;
>
> @@ -2232,7 +2198,7 @@ static unsigned int sci_get_mctrl(struct uart_port *port)
>         return mctrl;
>  }
>
> -static void sci_enable_ms(struct uart_port *port)
> +void sci_enable_ms(struct uart_port *port)
>  {
>         mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
>  }
> @@ -2268,7 +2234,17 @@ static void sci_break_ctl(struct uart_port *port, int break_state)
>         uart_port_unlock_irqrestore(port, flags);
>  }
>
> -static int sci_startup(struct uart_port *port)
> +static void sci_shutdown_complete(struct uart_port *port)
> +{
> +       struct sci_port *s = to_sci_port(port);
> +       u16 scr;
> +
> +       scr = sci_serial_in(port, SCSCR);
> +       sci_serial_out(port, SCSCR,
> +                      scr & (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot));
> +}
> +
> +int sci_startup(struct uart_port *port)
>  {
>         struct sci_port *s = to_sci_port(port);
>         int ret;
> @@ -2291,7 +2267,6 @@ static void sci_shutdown(struct uart_port *port)
>  {
>         struct sci_port *s = to_sci_port(port);
>         unsigned long flags;
> -       u16 scr;
>
>         dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
>
> @@ -2301,13 +2276,7 @@ static void sci_shutdown(struct uart_port *port)
>         uart_port_lock_irqsave(port, &flags);
>         sci_stop_rx(port);
>         sci_stop_tx(port);
> -       /*
> -        * Stop RX and TX, disable related interrupts, keep clock source
> -        * and HSCIF TOT bits
> -        */
> -       scr = sci_serial_in(port, SCSCR);
> -       sci_serial_out(port, SCSCR,
> -                      scr & (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot));
> +       s->ops->shutdown_complete(port);
>         uart_port_unlock_irqrestore(port, flags);
>
>  #ifdef CONFIG_SERIAL_SH_SCI_DMA
> @@ -2383,9 +2352,9 @@ static int sci_brg_calc(struct sci_port *s, unsigned int bps,
>  }
>
>  /* calculate sample rate, BRR, and clock select */
> -static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
> -                         unsigned int *brr, unsigned int *srr,
> -                         unsigned int *cks)
> +int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
> +                  unsigned int *brr, unsigned int *srr,
> +                  unsigned int *cks)
>  {
>         unsigned long freq = s->clk_rates[SCI_FCK];
>         unsigned int sr, br, prediv, scrate, c;
> @@ -2462,9 +2431,9 @@ static void sci_reset(struct uart_port *port)
>         if (reg->size)
>                 sci_serial_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
>
> -       sci_clear_SCxSR(port,
> -                       SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) &
> -                       SCxSR_BREAK_CLEAR(port));
> +       s->ops->clear_SCxSR(port,
> +                           SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) &
> +                           SCxSR_BREAK_CLEAR(port));
>         if (sci_getreg(port, SCLSR)->size) {
>                 status = sci_serial_in(port, SCLSR);
>                 status &= ~(SCLSR_TO | SCLSR_ORER);
> @@ -2473,14 +2442,14 @@ static void sci_reset(struct uart_port *port)
>
>         if (s->rx_trigger > 1) {
>                 if (s->rx_fifo_timeout) {
> -                       scif_set_rtrg(port, 1);
> +                       s->ops->set_rtrg(port, 1);
>                         timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0);
>                 } else {
>                         if (port->type == PORT_SCIFA ||
>                             port->type == PORT_SCIFB)
> -                               scif_set_rtrg(port, 1);
> +                               s->ops->set_rtrg(port, 1);
>                         else
> -                               scif_set_rtrg(port, s->rx_trigger);
> +                               s->ops->set_rtrg(port, s->rx_trigger);
>                 }
>         }
>  }
> @@ -2740,7 +2709,7 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
>                 sci_enable_ms(port);
>  }
>
> -static void sci_pm(struct uart_port *port, unsigned int state,
> +void sci_pm(struct uart_port *port, unsigned int state,
>                    unsigned int oldstate)
>  {
>         struct sci_port *sci_port = to_sci_port(port);
> @@ -2803,7 +2772,7 @@ static int sci_remap_port(struct uart_port *port)
>         return 0;
>  }
>
> -static void sci_release_port(struct uart_port *port)
> +void sci_release_port(struct uart_port *port)
>  {
>         struct sci_port *sport = to_sci_port(port);
>
> @@ -2815,7 +2784,7 @@ static void sci_release_port(struct uart_port *port)
>         release_mem_region(port->mapbase, sport->reg_size);
>  }
>
> -static int sci_request_port(struct uart_port *port)
> +int sci_request_port(struct uart_port *port)
>  {
>         struct resource *res;
>         struct sci_port *sport = to_sci_port(port);
> @@ -2837,7 +2806,7 @@ static int sci_request_port(struct uart_port *port)
>         return 0;
>  }
>
> -static void sci_config_port(struct uart_port *port, int flags)
> +void sci_config_port(struct uart_port *port, int flags)
>  {
>         if (flags & UART_CONFIG_TYPE) {
>                 struct sci_port *sport = to_sci_port(port);
> @@ -2847,7 +2816,7 @@ static void sci_config_port(struct uart_port *port, int flags)
>         }
>  }
>
> -static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
> +int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
>  {
>         if (ser->baud_base < 2400)
>                 /* No paper tape reader for Mitch.. */
> @@ -2856,6 +2825,18 @@ static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
>         return 0;
>  }
>
> +static u32 sci_get_ctrl_temp(struct uart_port *port, unsigned int ctrl)
> +{
> +       struct sci_port *s = to_sci_port(port);
> +       unsigned int ctrl_temp;
> +
> +       ctrl_temp = s->params->param_bits.rxtx_enable;
> +       ctrl_temp |=
> +               (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
> +               (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
> +       return ctrl_temp;
> +}
> +
>  static const struct uart_ops sci_uart_ops = {
>         .tx_empty       = sci_tx_empty,
>         .set_mctrl      = sci_set_mctrl,
> @@ -2881,6 +2862,19 @@ static const struct uart_ops sci_uart_ops = {
>  #endif
>  };
>
> +static const struct sci_port_ops sci_port_ops = {
> +       .read_reg               = sci_serial_in,
> +       .write_reg              = sci_serial_out,
> +       .receive_chars          = sci_receive_chars,
> +       .transmit_chars         = sci_transmit_chars,
> +       .poll_put_char          = sci_poll_put_char,
> +       .clear_SCxSR            = sci_clear_SCxSR,
> +       .set_rtrg               = scif_set_rtrg,
> +       .rtrg_enabled           = scif_rtrg_enabled,
> +       .shutdown_complete      = sci_shutdown_complete,
> +       .get_ctrl_temp          = sci_get_ctrl_temp,
> +};
> +
>  static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
>  {
>         const char *clk_names[] = {
> @@ -2974,6 +2968,7 @@ static int sci_init_single(struct platform_device *dev,
>         int ret;
>
>         sci_port->cfg   = p;
> +       sci_port->ops   = &sci_port_ops;
>
>         port->ops       = &sci_uart_ops;
>         port->iotype    = UPIO_MEM;
> @@ -3095,7 +3090,7 @@ static void sci_cleanup_single(struct sci_port *port)
>      defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
>  static void serial_console_putchar(struct uart_port *port, unsigned char ch)
>  {
> -       sci_poll_put_char(port, ch);
> +       to_sci_port(port)->ops->poll_put_char(port, ch);
>  }
>
>  /*
> @@ -3107,7 +3102,9 @@ static void serial_console_write(struct console *co, const char *s,
>  {
>         struct sci_port *sci_port = &sci_ports[co->index];
>         struct uart_port *port = &sci_port->port;
> -       unsigned short bits, ctrl, ctrl_temp;
> +       const struct sci_common_regs *regs = sci_port->params->common_regs;
> +       unsigned int bits;
> +       u32 ctrl, ctrl_temp;
>         unsigned long flags;
>         int locked = 1;
>
> @@ -3119,21 +3116,22 @@ static void serial_console_write(struct console *co, const char *s,
>                 uart_port_lock_irqsave(port, &flags);
>
>         /* first save SCSCR then disable interrupts, keep clock source */
> -       ctrl = sci_serial_in(port, SCSCR);
> -       ctrl_temp = SCSCR_RE | SCSCR_TE |
> -                   (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
> -                   (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
> -       sci_serial_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot);
> +       ctrl = sci_port->ops->read_reg(port, regs->control);
> +       ctrl_temp = sci_port->ops->get_ctrl_temp(port, ctrl);
> +
> +       sci_port->ops->write_reg(port, regs->control, ctrl_temp | sci_port->hscif_tot);
>
>         uart_console_write(port, s, count, serial_console_putchar);
>
>         /* wait until fifo is empty and last bit has been transmitted */
> -       bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
> -       while ((sci_serial_in(port, SCxSR) & bits) != bits)
> +
> +       bits = sci_ports->params->param_bits.poll_sent_bits;
> +
> +       while ((sci_port->ops->read_reg(port, regs->status) & bits) != bits)
>                 cpu_relax();
>
>         /* restore the SCSCR */
> -       sci_serial_out(port, SCSCR, ctrl);
> +       sci_port->ops->write_reg(port, regs->control, ctrl);
>
>         if (locked)
>                 uart_port_unlock_irqrestore(port, flags);
> @@ -3268,7 +3266,6 @@ static void sci_remove(struct platform_device *dev)
>                 device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout);
>  }
>
> -
>  #define SCI_OF_DATA(type, regtype)     (void *)((type) << 16 | (regtype))
>  #define SCI_OF_TYPE(data)              ((unsigned long)(data) >> 16)
>  #define SCI_OF_REGTYPE(data)           ((unsigned long)(data) & 0xffff)
> @@ -3564,9 +3561,11 @@ sh_early_platform_init_buffer("earlyprintk", &sci_driver,
>  #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
>  static struct plat_sci_port port_cfg __initdata;
>
> -static int __init early_console_setup(struct earlycon_device *device,
> +int __init early_console_setup(struct earlycon_device *device,
>                                       int type)
>  {
> +       const struct sci_common_regs *regs;
> +
>         if (!device->port.membase)
>                 return -ENODEV;
>
> @@ -3574,10 +3573,14 @@ static int __init early_console_setup(struct earlycon_device *device,
>         memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
>         port_cfg.type = type;
>         sci_ports[0].cfg = &port_cfg;
> +       sci_ports[0].ops = &sci_port_ops;
>         sci_ports[0].params = sci_probe_regmap(&port_cfg);
> -       port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR);
> -       sci_serial_out(&sci_ports[0].port, SCSCR,
> -                      SCSCR_RE | SCSCR_TE | port_cfg.scscr);
> +       regs = sci_ports[0].params->common_regs;
> +
> +       port_cfg.scscr = sci_ports[0].ops->read_reg(&sci_ports[0].port, regs->control);
> +       sci_ports[0].ops->write_reg(&sci_ports[0].port,
> +                                   regs->control,
> +                                   sci_ports[0].params->param_bits.rxtx_enable | port_cfg.scscr);
>
>         device->con->write = serial_console_write;
>         return 0;
> diff --git a/drivers/tty/serial/sh-sci_common.h b/drivers/tty/serial/sh-sci_common.h
> new file mode 100644
> index 000000000000..cbfacdc1a836
> --- /dev/null
> +++ b/drivers/tty/serial/sh-sci_common.h
> @@ -0,0 +1,178 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +
> +#ifndef __SH_SCI_COMMON_H__
> +#define __SH_SCI_COMMON_H__
> +
> +#define SCI_MAJOR      204
> +#define SCI_MINOR_START        8
> +
> +#include <linux/serial_core.h>
> +
> +enum SCI_CLKS {
> +       SCI_FCK,                /* Functional Clock */
> +       SCI_SCK,                /* Optional External Clock */
> +       SCI_BRG_INT,            /* Optional BRG Internal Clock Source */
> +       SCI_SCIF_CLK,           /* Optional BRG External Clock Source */
> +       SCI_NUM_CLKS
> +};
> +
> +/* Offsets into the sci_port->irqs array */
> +enum {
> +       SCIx_ERI_IRQ,
> +       SCIx_RXI_IRQ,
> +       SCIx_TXI_IRQ,
> +       SCIx_BRI_IRQ,
> +       SCIx_DRI_IRQ,
> +       SCIx_TEI_IRQ,
> +       SCIx_NR_IRQS,
> +
> +       SCIx_MUX_IRQ = SCIx_NR_IRQS,    /* special case */
> +};
> +
> +/* Bit x set means sampling rate x + 1 is supported */
> +#define SCI_SR(x)              BIT((x) - 1)
> +
> +extern void sci_release_port(struct uart_port *port);
> +extern int sci_request_port(struct uart_port *port);
> +extern void sci_config_port(struct uart_port *port, int flags);
> +extern int sci_verify_port(struct uart_port *port, struct serial_struct *ser);
> +extern void sci_pm(struct uart_port *port, unsigned int state,
> +                  unsigned int oldstate);
> +extern void sci_enable_ms(struct uart_port *port);
> +
> +#ifdef CONFIG_CONSOLE_POLL
> +extern int sci_poll_get_char(struct uart_port *port);
> +extern void sci_poll_put_char(struct uart_port *port, unsigned char c);
> +#endif /* CONFIG_CONSOLE_POLL */
> +
> +struct plat_sci_reg {
> +       u8 offset, size;
> +};
> +
> +/* The actual number of needed registers depends on the sci controller;
> + * using this value as a max covers both sci and rsci cases
> + */
> +#define SCI_NR_REGS 20
> +
> +struct sci_port_params_bits {
> +       unsigned int rxtx_enable;
> +       unsigned int te_clear;
> +       unsigned int poll_sent_bits;
> +};
> +
> +struct sci_common_regs {
> +       unsigned int status;
> +       unsigned int control;
> +};
> +
> +struct sci_port_params {
> +       const struct plat_sci_reg regs[SCI_NR_REGS];
> +       const struct sci_common_regs *common_regs;
> +       unsigned int fifosize;
> +       unsigned int overrun_reg;
> +       unsigned int overrun_mask;
> +       unsigned int sampling_rate_mask;
> +       unsigned int error_mask;
> +       unsigned int error_clear;
> +       struct sci_port_params_bits param_bits;
> +};
> +
> +struct sci_port_ops {
> +       u32 (*read_reg)(struct uart_port *port, int reg);
> +       void (*write_reg)(struct uart_port *port, int reg, int value);
> +       void (*clear_SCxSR)(struct uart_port *port, unsigned int mask);
> +
> +       void (*transmit_chars)(struct uart_port *port);
> +       void (*receive_chars)(struct uart_port *port);
> +
> +       void (*poll_put_char)(struct uart_port *port, unsigned char c);
> +
> +       int (*set_rtrg)(struct uart_port *port, int rx_trig);
> +       int (*rtrg_enabled)(struct uart_port *port);
> +
> +       void (*shutdown_complete)(struct uart_port *port);
> +
> +       unsigned int (*get_ctrl_temp)(struct uart_port *port, unsigned int ctrl);
> +};
> +
> +struct sci_of_data {
> +       const struct sci_port_params *params;
> +       const struct uart_ops *uart_ops;
> +       const struct sci_port_ops *ops;
> +       unsigned short regtype;
> +       unsigned short type;
> +};
> +
> +struct sci_port {
> +       struct uart_port        port;
> +
> +       /* Platform configuration */
> +       const struct sci_port_params *params;
> +       const struct plat_sci_port *cfg;
> +
> +       unsigned int            sampling_rate_mask;
> +       resource_size_t         reg_size;
> +       struct mctrl_gpios      *gpios;
> +
> +       /* Clocks */
> +       struct clk              *clks[SCI_NUM_CLKS];
> +       unsigned long           clk_rates[SCI_NUM_CLKS];
> +
> +       int                     irqs[SCIx_NR_IRQS];
> +       char                    *irqstr[SCIx_NR_IRQS];
> +
> +       struct dma_chan                 *chan_tx;
> +       struct dma_chan                 *chan_rx;
> +
> +#ifdef CONFIG_SERIAL_SH_SCI_DMA
> +       struct dma_chan                 *chan_tx_saved;
> +       struct dma_chan                 *chan_rx_saved;
> +       dma_cookie_t                    cookie_tx;
> +       dma_cookie_t                    cookie_rx[2];
> +       dma_cookie_t                    active_rx;
> +       dma_addr_t                      tx_dma_addr;
> +       unsigned int                    tx_dma_len;
> +       struct scatterlist              sg_rx[2];
> +       void                            *rx_buf[2];
> +       size_t                          buf_len_rx;
> +       struct work_struct              work_tx;
> +       struct hrtimer                  rx_timer;
> +       unsigned int                    rx_timeout;     /* microseconds */
> +#endif
> +       unsigned int                    rx_frame;
> +       int                             rx_trigger;
> +       struct timer_list               rx_fifo_timer;
> +       int                             rx_fifo_timeout;
> +       u16                             hscif_tot;
> +
> +       const struct sci_port_ops *ops;
> +
> +       bool has_rtscts;
> +       bool autorts;
> +       bool tx_occurred;
> +};
> +
> +#define to_sci_port(uart) container_of((uart), struct sci_port, port)
> +
> +extern int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
> +                         unsigned int *brr, unsigned int *srr,
> +                         unsigned int *cks);
> +
> +extern void sci_port_disable(struct sci_port *sci_port);
> +extern void sci_port_enable(struct sci_port *sci_port);
> +
> +extern int sci_startup(struct uart_port *port);
> +extern void sci_free_irq(struct sci_port *port);
> +
> +extern void sci_request_dma(struct uart_port *port);
> +extern void sci_free_dma(struct uart_port *port);
> +extern void sci_flush_buffer(struct uart_port *port);
> +
> +#define min_sr(_port)          ffs((_port)->sampling_rate_mask)
> +#define max_sr(_port)          fls((_port)->sampling_rate_mask)
> +
> +#ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
> +extern int __init early_console_setup(struct earlycon_device *device, int);
> +#endif
> +
> +#endif /* __SH_SCI_COMMON_H__ */
> --
> 2.43.0

Re: [PATCH 10/14] serial: sh-sci: Introduced sci_of_data

[Geert Uytterhoeven]

CC linux-renesas-soc

On Wed, 29 Jan 2025 at 17:56, Thierry Bultel
<thierry.bultel.yh@bp.renesas.com> wrote:
> The aim here is to provide an easier support to more different SCI
> controllers, like the RZ/T2H one.
>
> The existing .data field of_sci_match is changed to a structure containing
> all what that can be statically initialized, and avoid a call to
> 'sci_probe_regmap', in both 'sci_init_single', and 'early_console_setup'.
>
> 'sci_probe_regmap' is now assumed to be called in the only case where the
> device description is from a board file instead of a dts.
>
> In this way, there is no need to patch 'sci_probe_regmap' for adding new
> SCI type, and also, the specific sci_port_params for a new SCI type can be
> provided by an external file.
>
> Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
> ---
>  drivers/tty/serial/sh-sci.c        | 64 +++++++++++++++++++-----------
>  drivers/tty/serial/sh-sci_common.h |  3 +-
>  2 files changed, 43 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
> index 1b83a246c7ed..c58c0793c521 100644
> --- a/drivers/tty/serial/sh-sci.c
> +++ b/drivers/tty/serial/sh-sci.c
> @@ -2968,9 +2968,7 @@ static int sci_init_single(struct platform_device *dev,
>         int ret;
>
>         sci_port->cfg   = p;
> -       sci_port->ops   = &sci_port_ops;
>
> -       port->ops       = &sci_uart_ops;
>         port->iotype    = UPIO_MEM;
>         port->line      = index;
>         port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_SH_SCI_CONSOLE);
> @@ -3010,7 +3008,16 @@ static int sci_init_single(struct platform_device *dev,
>                 for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++)
>                         sci_port->irqs[i] = sci_port->irqs[0];
>
> -       sci_port->params = sci_probe_regmap(p);
> +       /*
> +        * sci_port->params params can be NULL when using a board file instead
> +        * of a dts.
> +        */
> +       if (sci_port->params == NULL) {
> +               sci_port->params = sci_probe_regmap(p);
> +               if (unlikely(sci_port->params == NULL))
> +                       return -EINVAL;
> +       }
> +
>         if (unlikely(sci_port->params == NULL))
>                 return -EINVAL;
>
> @@ -3266,9 +3273,14 @@ static void sci_remove(struct platform_device *dev)
>                 device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout);
>  }
>
> -#define SCI_OF_DATA(type, regtype)     (void *)((type) << 16 | (regtype))
> -#define SCI_OF_TYPE(data)              ((unsigned long)(data) >> 16)
> -#define SCI_OF_REGTYPE(data)           ((unsigned long)(data) & 0xffff)
> +#define SCI_OF_DATA(_type, _regtype) (\
> +&(struct sci_of_data) {\
> +       .type = (_type), \
> +       .regtype = (_regtype),\
> +       .ops = &sci_port_ops,\
> +       .uart_ops = &sci_uart_ops,\
> +       .params = &sci_port_params[_regtype],\
> +})
>
>  static const struct of_device_id of_sci_match[] __maybe_unused = {
>         /* SoC-specific types */
> @@ -3336,7 +3348,7 @@ static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
>         struct reset_control *rstc;
>         struct plat_sci_port *p;
>         struct sci_port *sp;
> -       const void *data;
> +       const struct sci_of_data *data;
>         int id, ret;
>
>         if (!IS_ENABLED(CONFIG_OF) || !np)
> @@ -3382,8 +3394,12 @@ static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
>         sp = &sci_ports[id];
>         *dev_id = id;
>
> -       p->type = SCI_OF_TYPE(data);
> -       p->regtype = SCI_OF_REGTYPE(data);
> +       p->type = data->type;
> +       p->regtype = data->regtype;
> +
> +       sp->ops = data->ops;
> +       sp->port.ops = data->uart_ops;
> +       sp->params = data->params;
>
>         sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts");
>
> @@ -3562,19 +3578,23 @@ sh_early_platform_init_buffer("earlyprintk", &sci_driver,
>  static struct plat_sci_port port_cfg __initdata;
>
>  int __init early_console_setup(struct earlycon_device *device,
> -                                     int type)
> +                              const struct sci_of_data *data)
>  {
>         const struct sci_common_regs *regs;
>
>         if (!device->port.membase)
>                 return -ENODEV;
>
> -       device->port.type = type;
> +       device->port.type = data->type;
>         memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
> -       port_cfg.type = type;
> +
> +       port_cfg.type = data->type;
> +       port_cfg.regtype = data->regtype;
> +
>         sci_ports[0].cfg = &port_cfg;
> -       sci_ports[0].ops = &sci_port_ops;
> -       sci_ports[0].params = sci_probe_regmap(&port_cfg);
> +       sci_ports[0].params = data->params;
> +       sci_ports[0].ops = data->ops;
> +       sci_ports[0].port.ops = data->uart_ops;
>         regs = sci_ports[0].params->common_regs;
>
>         port_cfg.scscr = sci_ports[0].ops->read_reg(&sci_ports[0].port, regs->control);
> @@ -3588,41 +3608,39 @@ int __init early_console_setup(struct earlycon_device *device,
>  static int __init sci_early_console_setup(struct earlycon_device *device,
>                                           const char *opt)
>  {
> -       return early_console_setup(device, PORT_SCI);
> +       return early_console_setup(device, SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE));
>  }
>  static int __init scif_early_console_setup(struct earlycon_device *device,
>                                           const char *opt)
>  {
> -       return early_console_setup(device, PORT_SCIF);
> +       return early_console_setup(device, SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE));
>  }
>  static int __init rzscifa_early_console_setup(struct earlycon_device *device,
>                                           const char *opt)
>  {
> -       port_cfg.regtype = SCIx_RZ_SCIFA_REGTYPE;
> -       return early_console_setup(device, PORT_SCIF);
> +       return early_console_setup(device, SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE));
>  }
>
>  static int __init rzv2hscif_early_console_setup(struct earlycon_device *device,
>                                                 const char *opt)
>  {
> -       port_cfg.regtype = SCIx_RZV2H_SCIF_REGTYPE;
> -       return early_console_setup(device, PORT_SCIF);
> +       return early_console_setup(device, SCI_OF_DATA(PORT_SCIF, SCIx_RZV2H_SCIF_REGTYPE));
>  }
>
>  static int __init scifa_early_console_setup(struct earlycon_device *device,
>                                           const char *opt)
>  {
> -       return early_console_setup(device, PORT_SCIFA);
> +       return early_console_setup(device, SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE));
>  }
>  static int __init scifb_early_console_setup(struct earlycon_device *device,
>                                           const char *opt)
>  {
> -       return early_console_setup(device, PORT_SCIFB);
> +       return early_console_setup(device, SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE));
>  }
>  static int __init hscif_early_console_setup(struct earlycon_device *device,
>                                           const char *opt)
>  {
> -       return early_console_setup(device, PORT_HSCIF);
> +       return early_console_setup(device, SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE));
>  }
>
>  OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
> diff --git a/drivers/tty/serial/sh-sci_common.h b/drivers/tty/serial/sh-sci_common.h
> index cbfacdc1a836..f75c185079dd 100644
> --- a/drivers/tty/serial/sh-sci_common.h
> +++ b/drivers/tty/serial/sh-sci_common.h
> @@ -172,7 +172,8 @@ extern void sci_flush_buffer(struct uart_port *port);
>  #define max_sr(_port)          fls((_port)->sampling_rate_mask)
>
>  #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
> -extern int __init early_console_setup(struct earlycon_device *device, int);
> +extern int __init early_console_setup(struct earlycon_device *device,
> +                                     const struct sci_of_data *data);
>  #endif
>
>  #endif /* __SH_SCI_COMMON_H__ */
> --
> 2.43.0
\

Re: [PATCH 14/14] defconfig: Enable RZ/T2H Soc and RZ_SCI

[Geert Uytterhoeven]

CC linux-renesas-soc

On Wed, 29 Jan 2025 at 17:57, Thierry Bultel
<thierry.bultel.yh@bp.renesas.com> wrote:
> Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
> ---
>  arch/arm64/configs/defconfig | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
> index c62831e61586..a1cc7a37386d 100644
> --- a/arch/arm64/configs/defconfig
> +++ b/arch/arm64/configs/defconfig
> @@ -486,6 +486,7 @@ CONFIG_SERIAL_TEGRA_TCU=y
>  CONFIG_SERIAL_IMX=y
>  CONFIG_SERIAL_IMX_CONSOLE=y
>  CONFIG_SERIAL_SH_SCI=y
> +CONFIG_SERIAL_RZ_SCI=y
>  CONFIG_SERIAL_MSM=y
>  CONFIG_SERIAL_MSM_CONSOLE=y
>  CONFIG_SERIAL_QCOM_GENI=y
> @@ -1457,6 +1458,7 @@ CONFIG_ARCH_R9A07G054=y
>  CONFIG_ARCH_R9A08G045=y
>  CONFIG_ARCH_R9A09G011=y
>  CONFIG_ARCH_R9A09G057=y
> +CONFIG_ARCH_R9A09G077=y
>  CONFIG_ROCKCHIP_IODOMAIN=y
>  CONFIG_ARCH_TEGRA_132_SOC=y
>  CONFIG_ARCH_TEGRA_210_SOC=y
> --
> 2.43.0

Re: [PATCH 06/14] clk: renesas: Add support for RZ/T2H family clock

[Paul Barker]

[-- Attachment #1.1.1: Type: text/plain, Size: 11989 bytes --]

Hi Thierry,

On 29/01/2025 16:37, Thierry Bultel wrote:
> Add the CPG driver for T2H family.
> 
> Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
> ---
>  drivers/clk/renesas/Kconfig     |   4 +
>  drivers/clk/renesas/Makefile    |   1 +
>  drivers/clk/renesas/rzt2h-cpg.c | 549 ++++++++++++++++++++++++++++++++
>  drivers/clk/renesas/rzt2h-cpg.h | 201 ++++++++++++
>  4 files changed, 755 insertions(+)
>  create mode 100644 drivers/clk/renesas/rzt2h-cpg.c
>  create mode 100644 drivers/clk/renesas/rzt2h-cpg.h

[snip]

> diff --git a/drivers/clk/renesas/rzt2h-cpg.c b/drivers/clk/renesas/rzt2h-cpg.c
> new file mode 100644
> index 000000000000..79dacbd2b186
> --- /dev/null
> +++ b/drivers/clk/renesas/rzt2h-cpg.c

[snip]

> +struct pll_clk {
> +	void __iomem *base;
> +	struct rzt2h_cpg_priv *priv;
> +	struct clk_hw hw;
> +	unsigned int conf;
> +	unsigned int type;
> +};
> +#define to_pll(_hw)	container_of(_hw, struct pll_clk, hw)

Please add a blank line between these definitions.

> +
> +static struct clk
> +*rzt2h_cpg_clk_src_twocell_get(struct of_phandle_args *clkspec,

The '*' is part of the type so should be on the previous line. i.e.

    static struct clk *
    rzt2h_cpg_clk_src_twocell_get(...)

> +			       void *data)
> +{
> +	unsigned int clkidx = clkspec->args[1];
> +	struct rzt2h_cpg_priv *priv = data;
> +	struct device *dev = priv->dev;
> +	const char *type;
> +	struct clk *clk;
> +
> +	switch (clkspec->args[0]) {
> +	case CPG_CORE:
> +		type = "core";
> +		if (clkidx > priv->last_dt_core_clk) {
> +			dev_err(dev, "Invalid %s clock index %u\n", type, clkidx);
> +			return ERR_PTR(-EINVAL);
> +		}
> +		clk = priv->clks[clkidx];
> +		break;
> +
> +	case CPG_MOD:
> +		type = "module";
> +		if (clkidx >= priv->num_mod_clks) {
> +			dev_err(dev, "Invalid %s clock index %u\n", type,
> +				clkidx);
> +			return ERR_PTR(-EINVAL);
> +		}
> +		clk = priv->clks[priv->num_core_clks + clkidx];
> +		break;
> +
> +	default:
> +		dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]);
> +		return ERR_PTR(-EINVAL);
> +	}
> +
> +	if (IS_ERR(clk))
> +		dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx,
> +			PTR_ERR(clk));
> +	else
> +		dev_dbg(dev, "clock (%u, %u) is %pC at %lu Hz\n",
> +			clkspec->args[0], clkspec->args[1], clk,
> +			clk_get_rate(clk));
> +	return clk;
> +}
> +
> +static void __init
> +rzt2h_cpg_register_core_clk(const struct cpg_core_clk *core,
> +			    const struct rzt2h_cpg_info *info,
> +			    struct rzt2h_cpg_priv *priv)
> +{
> +	struct clk *clk = ERR_PTR(-EOPNOTSUPP), *parent;
> +	unsigned int id = core->id, div = core->div;
> +	struct device *dev = priv->dev;
> +	const char *parent_name;
> +
> +	WARN_DEBUG(id >= priv->num_core_clks);
> +	WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
> +
> +	/* Skip NULLified clock */
> +	if (!core->name)
> +		return;
> +
> +	switch (core->type) {
> +	case CLK_TYPE_IN:
> +		clk = of_clk_get_by_name(priv->dev->of_node, core->name);
> +		break;
> +	case CLK_TYPE_FF:
> +		WARN_DEBUG(core->parent >= priv->num_core_clks);
> +		parent = priv->clks[core->parent];
> +		if (IS_ERR(parent)) {
> +			clk = parent;
> +			goto fail;
> +		}
> +
> +		parent_name = __clk_get_name(parent);
> +		clk = clk_register_fixed_factor(NULL, core->name,
> +						parent_name, CLK_SET_RATE_PARENT,
> +						core->mult, div);
> +		break;
> +	case CLK_TYPE_DIV:
> +		if (core->sel_base > 0)
> +			clk = rzt2h_cpg_div_clk_register(core,
> +							 priv->cpg_base1, priv);
> +		else
> +			clk = rzt2h_cpg_div_clk_register(core,
> +							 priv->cpg_base0, priv);
> +		break;
> +	case CLK_TYPE_MUX:
> +		clk = rzt2h_cpg_mux_clk_register(core, priv->cpg_base0, priv);
> +		break;
> +	default:
> +		goto fail;

I would prefer `clk = ERR_PTR(-EOPNOTSUPP);` here instead of at the top
of the function so that it's easier to see at a glance what is
happening.

> +	}
> +
> +	if (IS_ERR_OR_NULL(clk))
> +		goto fail;
> +
> +	priv->clks[id] = clk;
> +	return;
> +
> +fail:
> +	dev_err(dev, "Failed to register %s clock %s: %ld\n", "core",
> +		core->name, PTR_ERR(clk));
> +}
> +
> +/**
> + * struct mstp_clock - MSTP gating clock
> + *
> + * @hw: handle between common and hardware-specific interfaces
> + * @priv: CPG/MSTP private data
> + * @sibling: pointer to the other coupled clock
> + * @baseaddr: register base address
> + * @enabled: soft state of the clock, if it is coupled with another clock
> + * @off: register offset
> + * @bit: ON/MON bit
> + */
> +struct mstp_clock {
> +	struct rzt2h_cpg_priv *priv;
> +	struct mstp_clock *sibling;
> +	void __iomem *baseaddr;
> +	struct clk_hw hw;
> +	bool enabled;
> +	u32 off;
> +	u8 bit;
> +};
> +#define to_mod_clock(_hw) container_of(_hw, struct mstp_clock, hw)
> +static int rzt2h_mod_clock_is_enabled(struct clk_hw *hw)

Please add blank lines between these three definitions.

> +{
> +	struct mstp_clock *clock = to_mod_clock(hw);
> +	struct rzt2h_cpg_priv *priv = clock->priv;
> +	u32 bitmask = BIT(clock->bit);
> +	u32 value;
> +
> +	if (!clock->off) {
> +		dev_dbg(priv->dev, "%pC does not support ON/OFF\n",  hw->clk);
> +		return 1;
> +	}
> +	value = readl(clock->baseaddr + clock->off);
> +
> +	/* For all Module Stop registers, read bit meaning is as such:
> +	 * 0: Release from the module-stop state
> +	 * 1: Transition to the module-stop state is made
> +	*/
> +
> +	return !(value & bitmask);
> +}
> +
> +static const struct clk_ops rzt2h_mod_clock_ops = {
> +	.is_enabled = rzt2h_mod_clock_is_enabled,
> +};
> +
> +static void __init
> +rzt2h_cpg_register_mod_clk(const struct rzt2h_mod_clk *mod,
> +			   const struct rzt2h_cpg_info *info,
> +			   struct rzt2h_cpg_priv *priv)
> +{
> +	struct mstp_clock *clock = NULL;
> +	struct device *dev = priv->dev;
> +	unsigned int id = mod->id;
> +	struct clk_init_data init;
> +	struct clk *parent, *clk;
> +	const char *parent_name;
> +	unsigned int i;
> +
> +	WARN_DEBUG(id < priv->num_core_clks);
> +	WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks);
> +	WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks);
> +	WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
> +
> +	/* Skip NULLified clock */
> +	if (!mod->name)
> +		return;
> +
> +	parent = priv->clks[mod->parent];
> +	if (IS_ERR(parent)) {
> +		clk = parent;
> +		goto fail;
> +	}
> +
> +	clock = devm_kzalloc(dev, sizeof(*clock), GFP_KERNEL);
> +	if (!clock) {
> +		clk = ERR_PTR(-ENOMEM);
> +		goto fail;
> +	}
> +
> +	init.name = mod->name;
> +	init.ops = &rzt2h_mod_clock_ops;
> +	init.flags = CLK_SET_RATE_PARENT;
> +	for (i = 0; i < info->num_crit_mod_clks; i++)
> +		if (id == info->crit_mod_clks[i]) {
> +			dev_dbg(dev, "CPG %s setting CLK_IS_CRITICAL\n",
> +				mod->name);
> +			init.flags |= CLK_IS_CRITICAL;
> +			break;
> +		}
> +
> +	parent_name = __clk_get_name(parent);
> +	init.parent_names = &parent_name;
> +	init.num_parents = 1;
> +
> +	clock->off = mod->addr;
> +	clock->bit = mod->bit;
> +	clock->baseaddr = mod->sel_base ? priv->cpg_base1 : priv->cpg_base0;
> +	clock->priv = priv;
> +	clock->hw.init = &init;

Both init and parent_name are local variables and can't be used after we
return from this function. So we mustn't store pointers to them into
objects that have a longer lifetime.

Could we add init and parent_name members to struct mstp_clock, then use
clock->init and clock->parent_name instead of the local variables?

> +
> +	clk = devm_clk_register(dev, &clock->hw);
> +	if (IS_ERR(clk))
> +		goto fail;
> +
> +	priv->clks[id] = clk;
> +
> +	return;
> +
> +fail:
> +	dev_err(dev, "Failed to register %s clock %s: %ld\n", "module",
> +		mod->name, PTR_ERR(clk));
> +}
> +
> +static bool rzt2h_cpg_is_pm_clk(const struct of_phandle_args *clkspec)
> +{
> +	if (clkspec->args_count != 2)
> +		return false;
> +
> +	switch (clkspec->args[0]) {
> +	case CPG_MOD:
> +		return true;
> +
> +	default:
> +		return false;
> +	}

Can we replace this switch statement with:

    return (clkspec->args[0] == CPG_MOD);

> +}
> +
> +static int rzt2h_cpg_attach_dev(struct generic_pm_domain *unused, struct device *dev)
> +{
> +	struct device_node *np = dev->of_node;
> +	struct of_phandle_args clkspec;
> +	unsigned int i = 0;
> +	bool once = true;
> +	struct clk *clk;
> +	int error;
> +
> +	while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
> +					   &clkspec)) {
> +		if (!rzt2h_cpg_is_pm_clk(&clkspec)) {
> +			of_node_put(clkspec.np);
> +			continue;
> +		}
> +
> +		if (once) {

Can we just use `if (!i)` here and drop the `once` variable?

> +			once = false;
> +			error = pm_clk_create(dev);
> +			if (error) {
> +				of_node_put(clkspec.np);
> +				goto err;
> +			}
> +		}
> +		clk = of_clk_get_from_provider(&clkspec);
> +		of_node_put(clkspec.np);
> +		if (IS_ERR(clk)) {
> +			error = PTR_ERR(clk);
> +			goto fail_destroy;
> +		}
> +		error = pm_clk_add_clk(dev, clk);
> +		if (error) {
> +			dev_err(dev, "pm_clk_add_clk failed %d\n", error);
> +			goto fail_put;
> +		}
> +		i++;
> +	}
> +
> +	return 0;
> +
> +fail_put:
> +	clk_put(clk);
> +
> +fail_destroy:
> +	pm_clk_destroy(dev);
> +err:
> +	return error;
> +}

[snip]

> +static const struct of_device_id rzt2h_cpg_match[] = {
> +#ifdef CONFIG_CLK_R9A09G077
> +	{
> +		.compatible = "renesas,r9a09g077-cpg",
> +		.data = &r9a09g077_cpg_info,
> +	},
> +#endif

CONFIG_CLK_R9A09G077 and r9a09g077_cpg_info are not defined until the
subsequent patch. We should move this entry to the next patch, and leave
this array empty here.

For comparison see how the RZ/V2H CPG driver was added in the following
commits:

    dd22e5621749 ("clk: renesas: Add family-specific clock driver for RZ/V2H(P)")
    36932cbc3e6c ("clk: renesas: Add RZ/V2H(P) CPG driver")

> +	{ /* sentinel */ }
> +};

[snip]

> diff --git a/drivers/clk/renesas/rzt2h-cpg.h b/drivers/clk/renesas/rzt2h-cpg.h
> new file mode 100644
> index 000000000000..d9d28608e4c3
> --- /dev/null
> +++ b/drivers/clk/renesas/rzt2h-cpg.h

[snip]

> +/**
> + * struct rzt2_cpg_info - SoC-specific CPG Description
> + *
> + * @core_clks: Array of Core Clock definitions
> + * @num_core_clks: Number of entries in core_clks[]
> + * @last_dt_core_clk: ID of the last Core Clock exported to DT
> + * @num_total_core_clks: Total number of Core Clocks (exported + internal)
> + *
> + * @mod_clks: Array of Module Clock definitions
> + * @num_mod_clks: Number of entries in mod_clks[]
> + * @num_hw_mod_clks: Number of Module Clocks supported by the hardware
> + *
> + * @resets: Array of Module Reset definitions
> + * @num_resets: Number of entries in resets[]
> + *
> + * @crit_mod_clks: Array with Module Clock IDs of critical clocks that
> + *                 should not be disabled without a knowledgeable driver
> + * @num_crit_mod_clks: Number of entries in crit_mod_clks[]
> + */
> +struct rzt2h_cpg_info {
> +	/* Core Clocks */
> +	const struct cpg_core_clk *core_clks;
> +	unsigned int num_core_clks;
> +	unsigned int last_dt_core_clk;
> +	unsigned int num_total_core_clks;
> +
> +	/* Module Clocks */
> +	const struct rzt2h_mod_clk *mod_clks;
> +	unsigned int num_mod_clks;
> +	unsigned int num_hw_mod_clks;
> +
> +	/* Resets */
> +	const struct rzt2h_reset *resets;
> +	unsigned int num_resets;
> +
> +	/* Critical Module Clocks that should not be disabled */
> +	const unsigned int *crit_mod_clks;
> +	unsigned int num_crit_mod_clks;

It looks like resets and crit_mod_clks are not populated in this initial
patch series. We can drop support for both of these from this patch
series.

> +};
> +
> +extern const struct rzt2h_cpg_info r9a09g077_cpg_info;
> +
> +#endif

-- 
Paul Barker

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Re: [PATCH 07/14] clk: renesas: Add support for R9A09G077 SoC

[Paul Barker]

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On 29/01/2025 16:37, Thierry Bultel wrote:
> Add the R9A09G077 SoC specific definitions to the CPG driver.
> 
> Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
> ---
>  drivers/clk/renesas/Kconfig         |   5 ++
>  drivers/clk/renesas/Makefile        |   1 +
>  drivers/clk/renesas/r9a09g077-cpg.c | 100 ++++++++++++++++++++++++++++
>  3 files changed, 106 insertions(+)
>  create mode 100644 drivers/clk/renesas/r9a09g077-cpg.c
> 
> diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
> index 7ad59be2099d..017ae990d50c 100644
> --- a/drivers/clk/renesas/Kconfig
> +++ b/drivers/clk/renesas/Kconfig
> @@ -41,6 +41,7 @@ config CLK_RENESAS
>  	select CLK_R9A08G045 if ARCH_R9A08G045
>  	select CLK_R9A09G011 if ARCH_R9A09G011
>  	select CLK_R9A09G057 if ARCH_R9A09G057
> +	select CLK_R9A09G077 if ARCH_R9A09G077
>  	select CLK_SH73A0 if ARCH_SH73A0
>  
>  if CLK_RENESAS
> @@ -198,6 +199,10 @@ config CLK_R9A09G057
>         bool "RZ/V2H(P) clock support" if COMPILE_TEST
>         select CLK_RZV2H
>  
> +config CLK_R9A09G077
> +	bool "RZ/T2H clock support" if COMPILE_TEST
> +	select CLK_RZT2H
> +
>  config CLK_SH73A0
>  	bool "SH-Mobile AG5 clock support" if COMPILE_TEST
>  	select CLK_RENESAS_CPG_MSTP
> diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
> index bd9f0b54fcda..fe11b10bc451 100644
> --- a/drivers/clk/renesas/Makefile
> +++ b/drivers/clk/renesas/Makefile
> @@ -38,6 +38,7 @@ obj-$(CONFIG_CLK_R9A07G054)		+= r9a07g044-cpg.o
>  obj-$(CONFIG_CLK_R9A08G045)		+= r9a08g045-cpg.o
>  obj-$(CONFIG_CLK_R9A09G011)		+= r9a09g011-cpg.o
>  obj-$(CONFIG_CLK_R9A09G057)		+= r9a09g057-cpg.o
> +obj-$(CONFIG_CLK_R9A09G077)		+= r9a09g077-cpg.o
>  obj-$(CONFIG_CLK_SH73A0)		+= clk-sh73a0.o
>  
>  # Family
> diff --git a/drivers/clk/renesas/r9a09g077-cpg.c b/drivers/clk/renesas/r9a09g077-cpg.c
> new file mode 100644
> index 000000000000..0b2895c796d1
> --- /dev/null
> +++ b/drivers/clk/renesas/r9a09g077-cpg.c
> @@ -0,0 +1,100 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * r9a09g077 Clock Pulse Generator / Module Standby and Software Reset
> + *
> + * Copyright (C) 2025 Renesas Electronics Corp.
> + *
> + */
> +
> +#include <linux/device.h>
> +#include <linux/clk-provider.h>
> +#include <linux/init.h>
> +#include <linux/kernel.h>

Please use alphabetical order for these includes.

> +
> +#include <dt-bindings/clock/r9a09g077-cpg.h>
> +
> +#include "rzt2h-cpg.h"
> +
> +enum clk_ids {
> +	/* Core Clock Outputs exported to DT */
> +	/* External Input Clocks */
> +	LAST_DT_CORE_CLK = R9A09G077_LCDC_CLKD,
> +	CLK_EXTAL,
> +	CLK_LOCO,

I think the above lines have got slightly mixed up, it should be:

    /* Core Clock Outputs exported to DT */
    LAST_DT_CORE_CLK = R9A09G077_LCDC_CLKD,

    /* External Input Clocks */
    CLK_EXTAL,
    CLK_LOCO,

With these minor changes,
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>

-- 
Paul Barker

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Re: [PATCH 08/14] serial: sh-sci: Fix a comment about SCIFA

[Paul Barker]

[-- Attachment #1.1.1: Type: text/plain, Size: 1378 bytes --]

On 29/01/2025 16:37, Thierry Bultel wrote:
> RZ/T1 has SCIFA, 'T' is not relevant.
> 
> Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>

It'd be good to explain this better in the commit message, something like:

    The comment was correct when it was added, at that time RZ/T1 was
    the only SoC in the RZ/T line. Since then, further SoCs have been
    added with RZ/T names which do not use the same SCIFA register
    layout and so the comment is now misleading.

    So we update the comment to explicitly reference only RZ/T1 SoCs.

> ---
>  drivers/tty/serial/sh-sci.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
> index 924b803af440..5ba25a6a5432 100644
> --- a/drivers/tty/serial/sh-sci.c
> +++ b/drivers/tty/serial/sh-sci.c
> @@ -291,7 +291,7 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
>  	},
>  
>  	/*
> -	 * The "SCIFA" that is in RZ/A2, RZ/G2L and RZ/T.
> +	 * The "SCIFA" that is in RZ/A2, RZ/G2L and RZ/T1

Please keep the full stop at the end of the sentence for consistency.

>  	 * It looks like a normal SCIF with FIFO data, but with a
>  	 * compressed address space. Also, the break out of interrupts
>  	 * are different: ERI/BRI, RXI, TXI, TEI, DRI.

Thanks,

-- 
Paul Barker

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Re: [PATCH 09/14] serial: sh-sci: Introduced function pointers

[Paul Barker]

[-- Attachment #1.1.1: Type: text/plain, Size: 5299 bytes --]

Hi Thierry,

I've just had time to review the header file changes in this patch
today.

On 29/01/2025 16:37, Thierry Bultel wrote:
> The aim here is to prepare support for new sci controllers like
> the T2H/RSCI whose registers are too much different for being
> handled in common code.
> 
> This named serial controller also has 32 bits register,
> so some return types had to be changed.
> 
> The needed generic functions are no longer static, with prototypes
> defined in sh-sci-common.h so that they can be used from specific
> implementation in a separate file, to keep this driver as little
> changed as possible.
> 
> For doing so, a set of 'ops' is added to struct sci_port.
> 
> Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
> ---
>  drivers/tty/serial/sh-sci.c        | 339 +++++++++++++++--------------
>  drivers/tty/serial/sh-sci_common.h | 178 +++++++++++++++
>  2 files changed, 349 insertions(+), 168 deletions(-)
>  create mode 100644 drivers/tty/serial/sh-sci_common.h

[snip]

> diff --git a/drivers/tty/serial/sh-sci_common.h b/drivers/tty/serial/sh-sci_common.h
> new file mode 100644
> index 000000000000..cbfacdc1a836
> --- /dev/null
> +++ b/drivers/tty/serial/sh-sci_common.h
> @@ -0,0 +1,178 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +
> +#ifndef __SH_SCI_COMMON_H__
> +#define __SH_SCI_COMMON_H__
> +
> +#define SCI_MAJOR	204
> +#define SCI_MINOR_START	8
> +
> +#include <linux/serial_core.h>
> +
> +enum SCI_CLKS {
> +	SCI_FCK,		/* Functional Clock */
> +	SCI_SCK,		/* Optional External Clock */
> +	SCI_BRG_INT,		/* Optional BRG Internal Clock Source */
> +	SCI_SCIF_CLK,		/* Optional BRG External Clock Source */
> +	SCI_NUM_CLKS
> +};
> +
> +/* Offsets into the sci_port->irqs array */
> +enum {
> +	SCIx_ERI_IRQ,
> +	SCIx_RXI_IRQ,
> +	SCIx_TXI_IRQ,
> +	SCIx_BRI_IRQ,
> +	SCIx_DRI_IRQ,
> +	SCIx_TEI_IRQ,
> +	SCIx_NR_IRQS,
> +
> +	SCIx_MUX_IRQ = SCIx_NR_IRQS,	/* special case */
> +};
> +
> +/* Bit x set means sampling rate x + 1 is supported */
> +#define SCI_SR(x)		BIT((x) - 1)
> +
> +extern void sci_release_port(struct uart_port *port);
> +extern int sci_request_port(struct uart_port *port);
> +extern void sci_config_port(struct uart_port *port, int flags);
> +extern int sci_verify_port(struct uart_port *port, struct serial_struct *ser);
> +extern void sci_pm(struct uart_port *port, unsigned int state,
> +		   unsigned int oldstate);
> +extern void sci_enable_ms(struct uart_port *port);
> +
> +#ifdef CONFIG_CONSOLE_POLL
> +extern int sci_poll_get_char(struct uart_port *port);
> +extern void sci_poll_put_char(struct uart_port *port, unsigned char c);

The extern keyword isn't needed for function definitions in header
files.

> +#endif /* CONFIG_CONSOLE_POLL */
> +
> +struct plat_sci_reg {
> +	u8 offset, size;

Please define struct members on separate lines.

> +};
> +
> +/* The actual number of needed registers depends on the sci controller;
> + * using this value as a max covers both sci and rsci cases
> + */
> +#define SCI_NR_REGS 20
> +
> +struct sci_port_params_bits {
> +	unsigned int rxtx_enable;
> +	unsigned int te_clear;
> +	unsigned int poll_sent_bits;
> +};
> +
> +struct sci_common_regs {
> +	unsigned int status;
> +	unsigned int control;
> +};
> +
> +struct sci_port_params {
> +	const struct plat_sci_reg regs[SCI_NR_REGS];

I don't see any usage of the regs field of this struct - is it needed?
If not, can we also get rid of SCI_NR_REGS?

> +	const struct sci_common_regs *common_regs;
> +	unsigned int fifosize;
> +	unsigned int overrun_reg;
> +	unsigned int overrun_mask;
> +	unsigned int sampling_rate_mask;
> +	unsigned int error_mask;
> +	unsigned int error_clear;
> +	struct sci_port_params_bits param_bits;

It looks like we always initialise param_bits via a `static const struct
sci_port_params_bits` instance. Is there any reason we copy the contents
of this into the sci_port_params instance instead of using a pointer?

> +};
> +
> +struct sci_port_ops {
> +	u32 (*read_reg)(struct uart_port *port, int reg);
> +	void (*write_reg)(struct uart_port *port, int reg, int value);
> +	void (*clear_SCxSR)(struct uart_port *port, unsigned int mask);
> +
> +	void (*transmit_chars)(struct uart_port *port);
> +	void (*receive_chars)(struct uart_port *port);
> +
> +	void (*poll_put_char)(struct uart_port *port, unsigned char c);
> +
> +	int (*set_rtrg)(struct uart_port *port, int rx_trig);
> +	int (*rtrg_enabled)(struct uart_port *port);
> +
> +	void (*shutdown_complete)(struct uart_port *port);
> +
> +	unsigned int (*get_ctrl_temp)(struct uart_port *port, unsigned int ctrl);

I think we need a better name for this one. ctrl_temp is just the name
of the value we want to write to the control register in the
serial_console_write function, the name doesn't give any clue as to its
intended function.

Perhaps it would be better to define a prepare_console_write operation
which modifies the control register state and returns the old control
register state (so that it can later be restored). That would result in
a little more code duplication but it'd be easier to understand.

> +};

[snipped the rest]

Thanks,

-- 
Paul Barker

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Re: [PATCH 01/14] dt-bindings: soc: Document Renesas RZ/T2H (R9A09G077) SoC

[Geert Uytterhoeven]

Hi Thierry,

On Wed, 29 Jan 2025 at 17:51, Thierry Bultel
<thierry.bultel.yh@bp.renesas.com> wrote:
> Add RZ/T2H (R9A09G077) and variants in documentation.
>
> Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>

Thanks for your patch!

> --- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> +++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> @@ -535,6 +535,14 @@ properties:
>                - renesas,r9a09g057h44 # RZ/V2HP with Mali-G31 + Mali-C55 support
>            - const: renesas,r9a09g057
>
> +      - description: RZ/T2H (R9A09G077)
> +        items:
> +          - enum:
> +            - renesas,r9a09g077 # RZ/T2H with Quad Cortex-A55 + Dual Cortex-R52
> +            - renesas,r9a09g077m04 # RZ/T2H with Single Cortex-A55 + Dual Cortex-R52 - no security
> +            - renesas,r9a09g077m24 # RZ/T2H with Dual Cortex-A55 + Dual Cortex-R52 - no security
> +            - renesas,r9a09g077m44 # RZ/T2H with Quad Cortex-A55 + Dual Cortex-R52 - no security

While the part numbers match, the grouping (variant-specific + fallback).
do not.

> +
>  additionalProperties: true

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 02/14] dt-bindings: serial: Document sci bindings for the Renesas RZ/T2H (a.k.a r9a09g077) SoC

[Geert Uytterhoeven]

Hi Thierry,

On Wed, 29 Jan 2025 at 17:52, Thierry Bultel
<thierry.bultel.yh@bp.renesas.com> wrote:
> Document RZ/T2H (a.k.a r9a09g077) in SCI binding.
>
> Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>

Thanks for your patch!

> --- /dev/null
> +++ b/Documentation/devicetree/bindings/serial/renesas,rzsci.yaml
> @@ -0,0 +1,100 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/serial/renesas,rzsci.yaml#

"rzsci" is IMHO a bad name, as SCI on RZ/T2 differs from the
similar-named "SCI" (sometimes called "RSCI" or "SCIg") on RZ/A1H,
RZ/A2M, RZ/G2L, RZ/V2L, and RZ/G3S (and most old SuperH SoCs).

BTW, I believe the variant on RZ/T2 is also used on RZ/N2, RZ/V2H,
and RZ/G3E?

However, binding-wise, they all seem to be very similar.
So perhaps you can just add this to the existing
Documentation/devicetree/bindings/serial/renesas,sci.yaml?

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH 02/14] dt-bindings: serial: Document sci bindings for the Renesas RZ/T2H (a.k.a r9a09g077) SoC

[Biju Das]

Hi Geert,

> -----Original Message-----
> From: Geert Uytterhoeven <geert@linux-m68k.org>
> Sent: 10 February 2025 13:15
> Subject: Re: [PATCH 02/14] dt-bindings: serial: Document sci bindings for the Renesas RZ/T2H (a.k.a
> r9a09g077) SoC
> 
> Hi Thierry,
> 
> On Wed, 29 Jan 2025 at 17:52, Thierry Bultel <thierry.bultel.yh@bp.renesas.com> wrote:
> > Document RZ/T2H (a.k.a r9a09g077) in SCI binding.
> >
> > Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
> 
> Thanks for your patch!
> 
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/serial/renesas,rzsci.yaml
> > @@ -0,0 +1,100 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/serial/renesas,rzsci.yaml#
> 
> "rzsci" is IMHO a bad name, as SCI on RZ/T2 differs from the similar-named "SCI" (sometimes called
> "RSCI" or "SCIg") on RZ/A1H, RZ/A2M, RZ/G2L, RZ/V2L, and RZ/G3S (and most old SuperH SoCs).
> 
> BTW, I believe the variant on RZ/T2 is also used on RZ/N2, RZ/V2H, and RZ/G3E?
> 
> However, binding-wise, they all seem to be very similar.
> So perhaps you can just add this to the existing
> Documentation/devicetree/bindings/serial/renesas,sci.yaml?

It is present in RZ/G3E as well.
RSCI supports sci, scif, i2c and spi that is the reason renesas,rzsci.yaml introduced.

You mean add this in renesas,sci.yaml and then expand??

Cheers,
Biju

Re: [PATCH 03/14] dt-bindings: soc: Document the Renesas RZ/T2H Evaluation board for the R9A09G077 SoC

[Geert Uytterhoeven]

Hi Thierry,

Thanks for your patch!

On Wed, 29 Jan 2025 at 17:52, Thierry Bultel
<thierry.bultel.yh@bp.renesas.com> wrote:
> Add the RZ/T2H Evaluation board (r9a9g077m44-dev) in documentation.

This is the Evaluation Board Kit for RZ/T2H, "RZ/T2H-EVKIT" aka "rzt2hevb"?

> Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>

> --- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> +++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> @@ -537,6 +537,8 @@ properties:
>
>        - description: RZ/T2H (R9A09G077)
>          items:
> +          - enum:
> +            - renesas,r9a9g077m44-dev # RZ/T2H Evaluation Board

Perhaps "renesas,rzt2hevb" or "renesas,rzt2h-evb"?

>            - enum:
>              - renesas,r9a09g077 # RZ/T2H with Quad Cortex-A55 + Dual Cortex-R52
>              - renesas,r9a09g077m04 # RZ/T2H with Single Cortex-A55 + Dual Cortex-R52 - no security

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 04/14] dt-bindings: clock: Document cpg bindings for the Renesas RZ/T2H SoC

[Geert Uytterhoeven]

Hi Thierry,

On Wed, 29 Jan 2025 at 17:52, Thierry Bultel
<thierry.bultel.yh@bp.renesas.com> wrote:
> Document RZ/T2H (a.k.a r9a09g077) CPG (Clock Pulse Generator) binding.
> Add the header file for the resets and clocks definitions.
>
> Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>

Thanks for your patch!

> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/renesas,rzt2h-cpg.yaml
> @@ -0,0 +1,73 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/renesas,rzt2h-cpg.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas RZ/T2H(P) Clock Pulse Generator (CPG)
> +
> +maintainers:
> +  - Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
> +
> +description:
> +  On Renesas RZ/T2H SoCs, the CPG (Clock Pulse Generator) handles generation
> +  and control of clock signals for the IP modules, generation and control of resets,
> +  and control over booting, low power consumption and power supply domains.
> +
> +properties:
> +  compatible:
> +    const: renesas,r9a09g077-cpg
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    items:
> +      - description: EXTAL clock input
> +      - description: LOCO clock input
> +
> +  clock-names:
> +    items:
> +      - const: extal
> +      - const: loco
> +
> +  '#clock-cells':
> +    description: |
> +      - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
> +        and a core clock reference, as defined in
> +        <dt-bindings/clock/renesas,r9a09g077-cpg.h>,
> +      - For module clocks, the two clock specifier cells must be "CPG_MOD" and
> +        a module number, also defined <dt-bindings/clock/r9a09g077-cpg.h>,

As there is a set of 32-bit Module Stop Control Registers (albeit
inconveniently named A, B, C, and so on (including some gaps)),
the hardware documentation does provide you with a number space like
on R-Car.  Hence I think you're better off without defining module numbers
in the DT bindings header file.

> +    const: 2
> +
> +  '#power-domain-cells':
> +    const: 0
> +
> +  '#reset-cells':
> +    description:
> +      The single reset specifier cell must be the reset number, as defined in
> +      <dt-bindings/clock/r9a09g077-cpg.h>.

Likewise for the Module Reset Control Registers and the reset numbers.

> +    const: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - clock-names
> +  - '#clock-cells'
> +  - '#power-domain-cells'
> +  - '#reset-cells'
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    clock-controller@10420000 {

That address can't be right ;-)

> +        compatible = "renesas,r9a09g077-cpg";
> +        reg = <0x10420000 0x10000>;
> +        clocks = <&extal>, <&loco>;
> +        clock-names = "extal", "loco";
> +        #clock-cells = <2>;
> +        #power-domain-cells = <0>;
> +        #reset-cells = <1>;
> +    };

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 05/14] soc: renesas: Add RZ/T2H (R9A09G077) config option

[Geert Uytterhoeven]

On Wed, 29 Jan 2025 at 17:52, Thierry Bultel
<thierry.bultel.yh@bp.renesas.com> wrote:
> Add a configuration option for the RZ/T2H SoC.
>
> Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 06/14] clk: renesas: Add support for RZ/T2H family clock

[Geert Uytterhoeven]

Hi Thierry,

On Wed, 29 Jan 2025 at 17:52, Thierry Bultel
<thierry.bultel.yh@bp.renesas.com> wrote:
> Add the CPG driver for T2H family.
>
> Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>

Thanks for your patch!

> --- /dev/null
> +++ b/drivers/clk/renesas/rzt2h-cpg.c
> @@ -0,0 +1,549 @@

> +static void __init
> +rzt2h_cpg_register_mod_clk(const struct rzt2h_mod_clk *mod,
> +                          const struct rzt2h_cpg_info *info,
> +                          struct rzt2h_cpg_priv *priv)
> +{
> +       struct mstp_clock *clock = NULL;
> +       struct device *dev = priv->dev;
> +       unsigned int id = mod->id;
> +       struct clk_init_data init;
> +       struct clk *parent, *clk;
> +       const char *parent_name;
> +       unsigned int i;
> +
> +       WARN_DEBUG(id < priv->num_core_clks);
> +       WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks);
> +       WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks);
> +       WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
> +
> +       /* Skip NULLified clock */
> +       if (!mod->name)
> +               return;

Copied from rzg2l-cpg.c (which copied from renesas-cpg-mssr.c)?
Do you need this?

Given RZ/T2 does not use the "write bit 16 + n when touching bit
n"-scheme (like RZ/G2L and RZ/V2H), I am wondering if it would be easier
to use renesas-cpg-mssr.c instead, like R-Car and RZ/A2M are doing?

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 02/14] dt-bindings: serial: Document sci bindings for the Renesas RZ/T2H (a.k.a r9a09g077) SoC

[Geert Uytterhoeven]

Hi Biju,

On Mon, 10 Feb 2025 at 14:19, Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > -----Original Message-----
> > From: Geert Uytterhoeven <geert@linux-m68k.org>
> > Sent: 10 February 2025 13:15
> > Subject: Re: [PATCH 02/14] dt-bindings: serial: Document sci bindings for the Renesas RZ/T2H (a.k.a
> > r9a09g077) SoC
> >
> > On Wed, 29 Jan 2025 at 17:52, Thierry Bultel <thierry.bultel.yh@bp.renesas.com> wrote:
> > > Document RZ/T2H (a.k.a r9a09g077) in SCI binding.
> > >
> > > Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
> >
> > Thanks for your patch!
> >
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/serial/renesas,rzsci.yaml
> > > @@ -0,0 +1,100 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > > +---
> > > +$id: http://devicetree.org/schemas/serial/renesas,rzsci.yaml#
> >
> > "rzsci" is IMHO a bad name, as SCI on RZ/T2 differs from the similar-named "SCI" (sometimes called
> > "RSCI" or "SCIg") on RZ/A1H, RZ/A2M, RZ/G2L, RZ/V2L, and RZ/G3S (and most old SuperH SoCs).
> >
> > BTW, I believe the variant on RZ/T2 is also used on RZ/N2, RZ/V2H, and RZ/G3E?
> >
> > However, binding-wise, they all seem to be very similar.
> > So perhaps you can just add this to the existing
> > Documentation/devicetree/bindings/serial/renesas,sci.yaml?
>
> It is present in RZ/G3E as well.
> RSCI supports sci, scif, i2c and spi that is the reason renesas,rzsci.yaml introduced.

If you plan to add support for I2C and SPI, you will need different
bindings under Documentation/devicetree/bindings/{i2c,spi}/.

Note that we already have drivers/spi/spi-sh-sci.c (without DT support),
but it's definitely sub-optimal for the fancy new variant in RZ/T2...

> You mean add this in renesas,sci.yaml and then expand??

Indeed. Differences seem to be minimal.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH 02/14] dt-bindings: serial: Document sci bindings for the Renesas RZ/T2H (a.k.a r9a09g077) SoC

[Biju Das]

Hi Geert,

> -----Original Message-----
> From: Geert Uytterhoeven <geert@linux-m68k.org>
> Sent: 10 February 2025 14:15
> Subject: Re: [PATCH 02/14] dt-bindings: serial: Document sci bindings for the Renesas RZ/T2H (a.k.a
> r9a09g077) SoC
> 
> Hi Biju,
> 
> On Mon, 10 Feb 2025 at 14:19, Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > > -----Original Message-----
> > > From: Geert Uytterhoeven <geert@linux-m68k.org>
> > > Sent: 10 February 2025 13:15
> > > Subject: Re: [PATCH 02/14] dt-bindings: serial: Document sci
> > > bindings for the Renesas RZ/T2H (a.k.a
> > > r9a09g077) SoC
> > >
> > > On Wed, 29 Jan 2025 at 17:52, Thierry Bultel <thierry.bultel.yh@bp.renesas.com> wrote:
> > > > Document RZ/T2H (a.k.a r9a09g077) in SCI binding.
> > > >
> > > > Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
> > >
> > > Thanks for your patch!
> > >
> > > > --- /dev/null
> > > > +++ b/Documentation/devicetree/bindings/serial/renesas,rzsci.yaml
> > > > @@ -0,0 +1,100 @@
> > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML
> > > > +1.2
> > > > +---
> > > > +$id: http://devicetree.org/schemas/serial/renesas,rzsci.yaml#
> > >
> > > "rzsci" is IMHO a bad name, as SCI on RZ/T2 differs from the
> > > similar-named "SCI" (sometimes called "RSCI" or "SCIg") on RZ/A1H, RZ/A2M, RZ/G2L, RZ/V2L, and
> RZ/G3S (and most old SuperH SoCs).
> > >
> > > BTW, I believe the variant on RZ/T2 is also used on RZ/N2, RZ/V2H, and RZ/G3E?
> > >
> > > However, binding-wise, they all seem to be very similar.
> > > So perhaps you can just add this to the existing
> > > Documentation/devicetree/bindings/serial/renesas,sci.yaml?
> >
> > It is present in RZ/G3E as well.
> > RSCI supports sci, scif, i2c and spi that is the reason renesas,rzsci.yaml introduced.
> 
> If you plan to add support for I2C and SPI, you will need different bindings under
> Documentation/devicetree/bindings/{i2c,spi}/.

OK, I thought since it is a single IP, we need to use a single compatible and instantiate appropriate device based on
the device property rather than separate SCI, i2c and spi compatible.
 
Yes, I agree having different device compatible for same IP make life easier, no need to add specific
vendor property. 

Cheers,
Biju

Re: [PATCH 02/14] dt-bindings: serial: Document sci bindings for the Renesas RZ/T2H (a.k.a r9a09g077) SoC

[Geert Uytterhoeven]

Hi Biju,

On Mon, 10 Feb 2025 at 15:26, Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > -----Original Message-----
> > From: Geert Uytterhoeven <geert@linux-m68k.org>
> > Sent: 10 February 2025 14:15
> > Subject: Re: [PATCH 02/14] dt-bindings: serial: Document sci bindings for the Renesas RZ/T2H (a.k.a
> > r9a09g077) SoC
> >
> > On Mon, 10 Feb 2025 at 14:19, Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > > > -----Original Message-----
> > > > From: Geert Uytterhoeven <geert@linux-m68k.org>
> > > > Sent: 10 February 2025 13:15
> > > > Subject: Re: [PATCH 02/14] dt-bindings: serial: Document sci
> > > > bindings for the Renesas RZ/T2H (a.k.a
> > > > r9a09g077) SoC
> > > >
> > > > On Wed, 29 Jan 2025 at 17:52, Thierry Bultel <thierry.bultel.yh@bp.renesas.com> wrote:
> > > > > Document RZ/T2H (a.k.a r9a09g077) in SCI binding.
> > > > >
> > > > > Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
> > > >
> > > > Thanks for your patch!
> > > >
> > > > > --- /dev/null
> > > > > +++ b/Documentation/devicetree/bindings/serial/renesas,rzsci.yaml
> > > > > @@ -0,0 +1,100 @@
> > > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML
> > > > > +1.2
> > > > > +---
> > > > > +$id: http://devicetree.org/schemas/serial/renesas,rzsci.yaml#
> > > >
> > > > "rzsci" is IMHO a bad name, as SCI on RZ/T2 differs from the
> > > > similar-named "SCI" (sometimes called "RSCI" or "SCIg") on RZ/A1H, RZ/A2M, RZ/G2L, RZ/V2L, and
> > RZ/G3S (and most old SuperH SoCs).
> > > >
> > > > BTW, I believe the variant on RZ/T2 is also used on RZ/N2, RZ/V2H, and RZ/G3E?
> > > >
> > > > However, binding-wise, they all seem to be very similar.
> > > > So perhaps you can just add this to the existing
> > > > Documentation/devicetree/bindings/serial/renesas,sci.yaml?
> > >
> > > It is present in RZ/G3E as well.
> > > RSCI supports sci, scif, i2c and spi that is the reason renesas,rzsci.yaml introduced.
> >
> > If you plan to add support for I2C and SPI, you will need different bindings under
> > Documentation/devicetree/bindings/{i2c,spi}/.
>
> OK, I thought since it is a single IP, we need to use a single compatible and instantiate appropriate device based on
> the device property rather than separate SCI, i2c and spi compatible.
>
> Yes, I agree having different device compatible for same IP make life easier, no need to add specific
> vendor property.

I said "different bindings", not "different compatible values"!

Cfr. "renesas,tpu" having bindings in both
Documentation/devicetree/bindings/timer/renesas,tpu.yaml and
Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.yaml.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH 02/14] dt-bindings: serial: Document sci bindings for the Renesas RZ/T2H (a.k.a r9a09g077) SoC

[Biju Das]

Hi Geert,

> -----Original Message-----
> From: Geert Uytterhoeven <geert@linux-m68k.org>
> Sent: 10 February 2025 14:35
> Subject: Re: [PATCH 02/14] dt-bindings: serial: Document sci bindings for the Renesas RZ/T2H (a.k.a
> r9a09g077) SoC
> 
> Hi Biju,
> 
> On Mon, 10 Feb 2025 at 15:26, Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > > -----Original Message-----
> > > From: Geert Uytterhoeven <geert@linux-m68k.org>
> > > Sent: 10 February 2025 14:15
> > > Subject: Re: [PATCH 02/14] dt-bindings: serial: Document sci
> > > bindings for the Renesas RZ/T2H (a.k.a
> > > r9a09g077) SoC
> > >
> > > On Mon, 10 Feb 2025 at 14:19, Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > > > > -----Original Message-----
> > > > > From: Geert Uytterhoeven <geert@linux-m68k.org>
> > > > > Sent: 10 February 2025 13:15
> > > > > Subject: Re: [PATCH 02/14] dt-bindings: serial: Document sci
> > > > > bindings for the Renesas RZ/T2H (a.k.a
> > > > > r9a09g077) SoC
> > > > >
> > > > > On Wed, 29 Jan 2025 at 17:52, Thierry Bultel <thierry.bultel.yh@bp.renesas.com> wrote:
> > > > > > Document RZ/T2H (a.k.a r9a09g077) in SCI binding.
> > > > > >
> > > > > > Signed-off-by: Thierry Bultel
> > > > > > <thierry.bultel.yh@bp.renesas.com>
> > > > >
> > > > > Thanks for your patch!
> > > > >
> > > > > > --- /dev/null
> > > > > > +++ b/Documentation/devicetree/bindings/serial/renesas,rzsci.y
> > > > > > +++ aml
> > > > > > @@ -0,0 +1,100 @@
> > > > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > > > > +%YAML
> > > > > > +1.2
> > > > > > +---
> > > > > > +$id: http://devicetree.org/schemas/serial/renesas,rzsci.yaml#
> > > > >
> > > > > "rzsci" is IMHO a bad name, as SCI on RZ/T2 differs from the
> > > > > similar-named "SCI" (sometimes called "RSCI" or "SCIg") on
> > > > > RZ/A1H, RZ/A2M, RZ/G2L, RZ/V2L, and
> > > RZ/G3S (and most old SuperH SoCs).
> > > > >
> > > > > BTW, I believe the variant on RZ/T2 is also used on RZ/N2, RZ/V2H, and RZ/G3E?
> > > > >
> > > > > However, binding-wise, they all seem to be very similar.
> > > > > So perhaps you can just add this to the existing
> > > > > Documentation/devicetree/bindings/serial/renesas,sci.yaml?
> > > >
> > > > It is present in RZ/G3E as well.
> > > > RSCI supports sci, scif, i2c and spi that is the reason renesas,rzsci.yaml introduced.
> > >
> > > If you plan to add support for I2C and SPI, you will need different
> > > bindings under Documentation/devicetree/bindings/{i2c,spi}/.
> >
> > OK, I thought since it is a single IP, we need to use a single
> > compatible and instantiate appropriate device based on the device property rather than separate SCI,
> i2c and spi compatible.
> >
> > Yes, I agree having different device compatible for same IP make life
> > easier, no need to add specific vendor property.
> 
> I said "different bindings", not "different compatible values"!
> 
> Cfr. "renesas,tpu" having bindings in both Documentation/devicetree/bindings/timer/renesas,tpu.yaml
> and Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.yaml.

Thanks for clarification. This is simple solution.

Cheers,
Biju

Re: [PATCH 09/14] serial: sh-sci: Introduced function pointers

[Geert Uytterhoeven]

Hi Thierry,

On Wed, 29 Jan 2025 at 18:03, Thierry Bultel
<thierry.bultel.yh@bp.renesas.com> wrote:
> The aim here is to prepare support for new sci controllers like
> the T2H/RSCI whose registers are too much different for being
> handled in common code.
>
> This named serial controller also has 32 bits register,
> so some return types had to be changed.
>
> The needed generic functions are no longer static, with prototypes
> defined in sh-sci-common.h so that they can be used from specific
> implementation in a separate file, to keep this driver as little
> changed as possible.
>
> For doing so, a set of 'ops' is added to struct sci_port.
>
> Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>

Thanks for your patch!

I can't say I am super-enthusiastic about this approach.
The SCI variant in RZ/T2 seems to differ a lot from the already
supported SCI, SCIF, SCIFA, SCIFB, and HSCIF variants. The latter
are very similar, but usually have just more features/registers, and
further differ in a few different register offsets and bit locations.
If you compare the RZ/T2 SCI block diagram with the SH7751 SCI block
diagram (or even the R-Car SCIF block diagram), the most striking
similarity is that both have a baud rate generator that can divide
Pclk by 1, 4, 16, or 64 ;-)
So perhaps you're better off adding a completely new driver?

What do other people think?
Thanks!

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH 02/14] dt-bindings: serial: Document sci bindings for the Renesas RZ/T2H (a.k.a r9a09g077) SoC

[Biju Das]

Hi Geert,


> -----Original Message-----
> From: Biju Das <biju.das.jz@bp.renesas.com>
> Sent: 10 February 2025 14:42
> To: Geert Uytterhoeven <geert@linux-m68k.org>
> Subject: RE: [PATCH 02/14] dt-bindings: serial: Document sci bindings for the Renesas RZ/T2H (a.k.a
> r9a09g077) SoC
> 
> Hi Geert,
> 
> > -----Original Message-----
> > From: Geert Uytterhoeven <geert@linux-m68k.org>
> > Sent: 10 February 2025 14:35
> > Subject: Re: [PATCH 02/14] dt-bindings: serial: Document sci bindings
> > for the Renesas RZ/T2H (a.k.a
> > r9a09g077) SoC
> >
> > Hi Biju,
> >
> > On Mon, 10 Feb 2025 at 15:26, Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > > > -----Original Message-----
> > > > From: Geert Uytterhoeven <geert@linux-m68k.org>
> > > > Sent: 10 February 2025 14:15
> > > > Subject: Re: [PATCH 02/14] dt-bindings: serial: Document sci
> > > > bindings for the Renesas RZ/T2H (a.k.a
> > > > r9a09g077) SoC
> > > >
> > > > On Mon, 10 Feb 2025 at 14:19, Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > > > > > -----Original Message-----
> > > > > > From: Geert Uytterhoeven <geert@linux-m68k.org>
> > > > > > Sent: 10 February 2025 13:15
> > > > > > Subject: Re: [PATCH 02/14] dt-bindings: serial: Document sci
> > > > > > bindings for the Renesas RZ/T2H (a.k.a
> > > > > > r9a09g077) SoC
> > > > > >
> > > > > > On Wed, 29 Jan 2025 at 17:52, Thierry Bultel <thierry.bultel.yh@bp.renesas.com> wrote:
> > > > > > > Document RZ/T2H (a.k.a r9a09g077) in SCI binding.
> > > > > > >
> > > > > > > Signed-off-by: Thierry Bultel
> > > > > > > <thierry.bultel.yh@bp.renesas.com>
> > > > > >
> > > > > > Thanks for your patch!
> > > > > >
> > > > > > > --- /dev/null
> > > > > > > +++ b/Documentation/devicetree/bindings/serial/renesas,rzsci
> > > > > > > +++ .y
> > > > > > > +++ aml
> > > > > > > @@ -0,0 +1,100 @@
> > > > > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > > > > > +%YAML
> > > > > > > +1.2
> > > > > > > +---
> > > > > > > +$id:
> > > > > > > +http://devicetree.org/schemas/serial/renesas,rzsci.yaml#
> > > > > >
> > > > > > "rzsci" is IMHO a bad name, as SCI on RZ/T2 differs from the
> > > > > > similar-named "SCI" (sometimes called "RSCI" or "SCIg") on
> > > > > > RZ/A1H, RZ/A2M, RZ/G2L, RZ/V2L, and
> > > > RZ/G3S (and most old SuperH SoCs).
> > > > > >
> > > > > > BTW, I believe the variant on RZ/T2 is also used on RZ/N2, RZ/V2H, and RZ/G3E?
> > > > > >
> > > > > > However, binding-wise, they all seem to be very similar.
> > > > > > So perhaps you can just add this to the existing
> > > > > > Documentation/devicetree/bindings/serial/renesas,sci.yaml?
> > > > >
> > > > > It is present in RZ/G3E as well.
> > > > > RSCI supports sci, scif, i2c and spi that is the reason renesas,rzsci.yaml introduced.
> > > >
> > > > If you plan to add support for I2C and SPI, you will need
> > > > different bindings under Documentation/devicetree/bindings/{i2c,spi}/.
> > >
> > > OK, I thought since it is a single IP, we need to use a single
> > > compatible and instantiate appropriate device based on the device
> > > property rather than separate SCI,
> > i2c and spi compatible.
> > >
> > > Yes, I agree having different device compatible for same IP make
> > > life easier, no need to add specific vendor property.
> >
> > I said "different bindings", not "different compatible values"!
> >
> > Cfr. "renesas,tpu" having bindings in both
> > Documentation/devicetree/bindings/timer/renesas,tpu.yaml
> > and Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.yaml.
> 
> Thanks for clarification. This is simple solution.

But, here we need to decide, which channels to be used in SCI, I2C and SPI
in SoC dtsi

or

Maybe define all the channels as sci as default and override it in board dts for
I2c and spi based on customer use case??

Cheers,
Biju

Re: [PATCH 02/14] dt-bindings: serial: Document sci bindings for the Renesas RZ/T2H (a.k.a r9a09g077) SoC

[Geert Uytterhoeven]

Hi Biju,

On Mon, 10 Feb 2025 at 15:46, Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > From: Biju Das <biju.das.jz@bp.renesas.com>
> > > From: Geert Uytterhoeven <geert@linux-m68k.org>
> > > On Mon, 10 Feb 2025 at 15:26, Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > > > > From: Geert Uytterhoeven <geert@linux-m68k.org>
> > > > > On Mon, 10 Feb 2025 at 14:19, Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > > > > > > From: Geert Uytterhoeven <geert@linux-m68k.org>
> > > > > > > On Wed, 29 Jan 2025 at 17:52, Thierry Bultel <thierry.bultel.yh@bp.renesas.com> wrote:
> > > > > > > > Document RZ/T2H (a.k.a r9a09g077) in SCI binding.
> > > > > > > >
> > > > > > > > Signed-off-by: Thierry Bultel
> > > > > > > > <thierry.bultel.yh@bp.renesas.com>
> > > > > > >
> > > > > > > Thanks for your patch!
> > > > > > >
> > > > > > > > --- /dev/null
> > > > > > > > +++ b/Documentation/devicetree/bindings/serial/renesas,rzsci
> > > > > > > > +++ .y
> > > > > > > > +++ aml
> > > > > > > > @@ -0,0 +1,100 @@
> > > > > > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > > > > > > +%YAML
> > > > > > > > +1.2
> > > > > > > > +---
> > > > > > > > +$id:
> > > > > > > > +http://devicetree.org/schemas/serial/renesas,rzsci.yaml#
> > > > > > >
> > > > > > > "rzsci" is IMHO a bad name, as SCI on RZ/T2 differs from the
> > > > > > > similar-named "SCI" (sometimes called "RSCI" or "SCIg") on
> > > > > > > RZ/A1H, RZ/A2M, RZ/G2L, RZ/V2L, and
> > > > > RZ/G3S (and most old SuperH SoCs).
> > > > > > >
> > > > > > > BTW, I believe the variant on RZ/T2 is also used on RZ/N2, RZ/V2H, and RZ/G3E?
> > > > > > >
> > > > > > > However, binding-wise, they all seem to be very similar.
> > > > > > > So perhaps you can just add this to the existing
> > > > > > > Documentation/devicetree/bindings/serial/renesas,sci.yaml?
> > > > > >
> > > > > > It is present in RZ/G3E as well.
> > > > > > RSCI supports sci, scif, i2c and spi that is the reason renesas,rzsci.yaml introduced.
> > > > >
> > > > > If you plan to add support for I2C and SPI, you will need
> > > > > different bindings under Documentation/devicetree/bindings/{i2c,spi}/.
> > > >
> > > > OK, I thought since it is a single IP, we need to use a single
> > > > compatible and instantiate appropriate device based on the device
> > > > property rather than separate SCI,
> > > i2c and spi compatible.
> > > >
> > > > Yes, I agree having different device compatible for same IP make
> > > > life easier, no need to add specific vendor property.
> > >
> > > I said "different bindings", not "different compatible values"!
> > >
> > > Cfr. "renesas,tpu" having bindings in both
> > > Documentation/devicetree/bindings/timer/renesas,tpu.yaml
> > > and Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.yaml.
> >
> > Thanks for clarification. This is simple solution.
>
> But, here we need to decide, which channels to be used in SCI, I2C and SPI
> in SoC dtsi
>
> or
>
> Maybe define all the channels as sci as default and override it in board dts for
> I2c and spi based on customer use case??

The latter, please.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 11/14] serial: sh-sci: Add support for RZ/T2H SCI

[Geert Uytterhoeven]

Hi Thierry,

On Wed, 29 Jan 2025 at 17:52, Thierry Bultel
<thierry.bultel.yh@bp.renesas.com> wrote:
> Define a new RZSCI port type, and the RSCI 32 bits registers set.
> The RZ/T2H SCI has a a fifo, and a quite different set of registers
> from the orginal SH SCI ones.
> DMA is not supported yet.
>
> Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>

Thanks for your patch!

> --- /dev/null
> +++ b/drivers/tty/serial/rzsci.c
> @@ -0,0 +1,484 @@

> +/* RDR (Receive Data Register) */
> +#define RDR_FER                        BIT(28) /* Framing Error */
> +#define RDR_PER                        BIT(27) /* Parity Error */
> +#define RDR_ORER               BIT(24) /* Overrun Error */
> +#define RDR_FFER               BIT(12) /* FIFO Framing Error */
> +#define RDR_FPER               BIT(11) /* FIFO Parity Error */
> +#define RDR_DR                 BIT(10) /* Incoming Data Ready */
> +#define RDR_MPB                        BIT(9)  /* Multiprocessor Bit */

None of the above are used...

> +#define        RDR_RDAT_MSK            GENMASK(8, 0)

...

> +static void rzsci_receive_chars(struct uart_port *port)
> +{
> +       struct tty_port *tport = &port->state->port;
> +       int i, count, copied = 0;
> +       u32 status, frsr_status = 0;
> +       unsigned char flag;
> +
> +       status = rzsci_serial_in(port, CSR);
> +       frsr_status = rzsci_serial_in(port, FRSR);
> +
> +       if (!(status & CSR_RDRF) && !(frsr_status & FRSR_DR))
> +               return;
> +
> +       while (1) {
> +               /* Don't copy more bytes than there is room for in the buffer */
> +               count = tty_buffer_request_room(tport, rzsci_rxfill(port));
> +
> +               /* If for any reason we can't copy more data, we're done! */
> +               if (count == 0)
> +                       break;
> +
> +               for (i = 0; i < count; i++) {
> +                       char c;
> +
> +                       status = rzsci_serial_in(port, CSR);

Isn't the point of the RDR_* status bits in the top part of the RDR
register that you don't need to read the CSR register anymore?

> +                       c = rzsci_serial_in(port, RDR) & RDR_RDAT_MSK;

Note that this drops bit 8.

> +
> +                       if (uart_handle_sysrq_char(port, c)) {
> +                               count--;
> +                               i--;
> +                               continue;
> +                       }
> +
> +                       /* Store data and status */
> +                       if (status & CSR_FER) {
> +                               flag = TTY_FRAME;
> +                               port->icount.frame++;
> +                       } else if (status & CSR_PER) {
> +                               flag = TTY_PARITY;
> +                               port->icount.parity++;
> +                       } else
> +                               flag = TTY_NORMAL;
> +
> +                       tty_insert_flip_char(tport, c, flag);
> +               }
> +
> +               rzsci_serial_in(port, CSR); /* dummy read */
> +               rzsci_clear_DRxC(port);
> +
> +               copied += count;
> +               port->icount.rx += count;
> +       }

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 09/14] serial: sh-sci: Introduced function pointers

[Geert Uytterhoeven]

CC linux-renesas-soc

On Mon, 10 Feb 2025 at 15:45, Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Thierry,
>
> On Wed, 29 Jan 2025 at 18:03, Thierry Bultel
> <thierry.bultel.yh@bp.renesas.com> wrote:
> > The aim here is to prepare support for new sci controllers like
> > the T2H/RSCI whose registers are too much different for being
> > handled in common code.
> >
> > This named serial controller also has 32 bits register,
> > so some return types had to be changed.
> >
> > The needed generic functions are no longer static, with prototypes
> > defined in sh-sci-common.h so that they can be used from specific
> > implementation in a separate file, to keep this driver as little
> > changed as possible.
> >
> > For doing so, a set of 'ops' is added to struct sci_port.
> >
> > Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
>
> Thanks for your patch!
>
> I can't say I am super-enthusiastic about this approach.
> The SCI variant in RZ/T2 seems to differ a lot from the already
> supported SCI, SCIF, SCIFA, SCIFB, and HSCIF variants. The latter
> are very similar, but usually have just more features/registers, and
> further differ in a few different register offsets and bit locations.
> If you compare the RZ/T2 SCI block diagram with the SH7751 SCI block
> diagram (or even the R-Car SCIF block diagram), the most striking
> similarity is that both have a baud rate generator that can divide
> Pclk by 1, 4, 16, or 64 ;-)
> So perhaps you're better off adding a completely new driver?
>
> What do other people think?
> Thanks!

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 10/14] serial: sh-sci: Introduced sci_of_data

[Geert Uytterhoeven]

Hi Thierry,

On Wed, 29 Jan 2025 at 17:56, Thierry Bultel
<thierry.bultel.yh@bp.renesas.com> wrote:
> The aim here is to provide an easier support to more different SCI
> controllers, like the RZ/T2H one.
>
> The existing .data field of_sci_match is changed to a structure containing
> all what that can be statically initialized, and avoid a call to
> 'sci_probe_regmap', in both 'sci_init_single', and 'early_console_setup'.
>
> 'sci_probe_regmap' is now assumed to be called in the only case where the
> device description is from a board file instead of a dts.
>
> In this way, there is no need to patch 'sci_probe_regmap' for adding new
> SCI type, and also, the specific sci_port_params for a new SCI type can be
> provided by an external file.
>
> Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>

Thanks for your patch!

> --- a/drivers/tty/serial/sh-sci.c
> +++ b/drivers/tty/serial/sh-sci.c
> @@ -2968,9 +2968,7 @@ static int sci_init_single(struct platform_device *dev,
>         int ret;
>
>         sci_port->cfg   = p;
> -       sci_port->ops   = &sci_port_ops;
>
> -       port->ops       = &sci_uart_ops;

This relies on sci_parse_dt() having filled in both ops, which is not
done in the non-DT case (i.e. legacy SuperH).

>         port->iotype    = UPIO_MEM;
>         port->line      = index;
>         port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_SH_SCI_CONSOLE);
> @@ -3010,7 +3008,16 @@ static int sci_init_single(struct platform_device *dev,
>                 for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++)
>                         sci_port->irqs[i] = sci_port->irqs[0];
>
> -       sci_port->params = sci_probe_regmap(p);
> +       /*
> +        * sci_port->params params can be NULL when using a board file instead
> +        * of a dts.
> +        */
> +       if (sci_port->params == NULL) {
> +               sci_port->params = sci_probe_regmap(p);

... hence sci_probe_regmap() should fill in the ops.

> +               if (unlikely(sci_port->params == NULL))
> +                       return -EINVAL;

This case is already handled below.

> +       }
> +
>         if (unlikely(sci_port->params == NULL))
>                 return -EINVAL;
>

> @@ -3336,7 +3348,7 @@ static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
>         struct reset_control *rstc;
>         struct plat_sci_port *p;
>         struct sci_port *sp;
> -       const void *data;
> +       const struct sci_of_data *data;
>         int id, ret;
>
>         if (!IS_ENABLED(CONFIG_OF) || !np)
> @@ -3382,8 +3394,12 @@ static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
>         sp = &sci_ports[id];
>         *dev_id = id;
>
> -       p->type = SCI_OF_TYPE(data);
> -       p->regtype = SCI_OF_REGTYPE(data);
> +       p->type = data->type;
> +       p->regtype = data->regtype;
> +
> +       sp->ops = data->ops;
> +       sp->port.ops = data->uart_ops;
> +       sp->params = data->params;
>
>         sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts");
>

> --- a/drivers/tty/serial/sh-sci_common.h
> +++ b/drivers/tty/serial/sh-sci_common.h

"struct sci_of_data" should be introduced here, instead of in the
previous patch.

> @@ -172,7 +172,8 @@ extern void sci_flush_buffer(struct uart_port *port);
>  #define max_sr(_port)          fls((_port)->sampling_rate_mask)
>
>  #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
> -extern int __init early_console_setup(struct earlycon_device *device, int);
> +extern int __init early_console_setup(struct earlycon_device *device,
> +                                     const struct sci_of_data *data);
>  #endif
>
>  #endif /* __SH_SCI_COMMON_H__ */

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 12/14] arm64: dts: renesas: Add initial support for renesas RZ/T2H SoC

[Geert Uytterhoeven]

Hi Thierry,

On Wed, 29 Jan 2025 at 17:52, Thierry Bultel
<thierry.bultel.yh@bp.renesas.com> wrote:
> Add the initial dtsi for the RZ/T2H Soc:
>
> - gic
> - armv8-timer
> - cpg clock
> - sci0 uart
>
> also add arch/arm64/boot/dts/renesas/r9a09g077m44.dtsi, that keeps
> all 4 CPUs enabled, for consistency with later support of -m24
> and -m04 SoC revisions, that only have 2 and 1 Cortex-A55, respectively,
> and that will use /delete-node/ to disable the missing CPUs.
>
> Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>

Thanks for your patch!

> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
> @@ -0,0 +1,129 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Device Tree Source for the RZ/T2H SoC
> + *
> + * Copyright (C) 2025 Renesas Electronics Corp.
> + */
> +
> +#include <dt-bindings/clock/r9a09g077-cpg.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> +       compatible = "renesas,r9a09g077";
> +       #address-cells = <2>;
> +       #size-cells = <2>;
> +
> +       extal: extal {
> +               compatible = "fixed-clock";
> +               #clock-cells = <0>;
> +               /* This value must be overridden by the board */
> +               clock-frequency = <0>;
> +       };
> +
> +       loco: loco {
> +               compatible = "fixed-clock";
> +               #clock-cells = <0>;
> +               /* This value must be overridden by the board */
> +               clock-frequency = <0>;
> +       };
> +
> +       cpus {

Please sort nodes without unit addresses alphabetically, by node name.

> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/r9a09g077m44.dtsi
> @@ -0,0 +1,8 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Device Tree Source for the RZ/T2H 4-core SoC
> + *
> + * Copyright (C) 2025 Renesas Electronics Corp.
> + */
> +
> +#include "r9a09g077.dtsi"

compatible = "renesas,r9a09g077m44", "renesas,r9a09g077";

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 13/14] arm64: dts: renesas: Add initial support for renesas RZ/T2H eval board

[Geert Uytterhoeven]

Hi Thierry,

On Wed, 29 Jan 2025 at 17:53, Thierry Bultel
<thierry.bultel.yh@bp.renesas.com> wrote:
> Add the initial device tree for the RZ/T2H evaluation board.
>
> Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>

Thanks for your patch!

> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
> @@ -0,0 +1,37 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Device Tree Source for the RZ/T2H Development EVK board
> + *
> + * Copyright (C) 2025 Renesas Electronics Corp.
> + */
> +
> +/dts-v1/;
> +
> +#include "r9a09g077m44.dtsi"
> +
> +/ {
> +       model = "Renesas Development EVK based on r9a09g077m44";
> +       compatible = "renesas,r9a9g077m44-rzt2h-evk", "renesas,r9a9g077";

"renesas,r9a9g077m44-rzt2h-evk" is undocumented.
Missing "renesas,r9a9g077m44" in between.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds