From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1B92E1DE8A9 for ; Wed, 29 Jan 2025 18:40:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738176043; cv=none; b=flOGct8OrIZkvUF8jsPAK8f8jFsHX6TLIuDjcE8oRVYIRqEXrKk/wPhf60XELCvS8WjuMBUdu1lqmvJVQmyzuhkaM55vrzukFfmmfUgU8o4pXLiuUMhIc73BtXq3/OLfILd3XDyONR1EAfYkd5ThBNyRj+IGSx0Kh8Y8/Tj84eI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738176043; c=relaxed/simple; bh=KSn6f2pCC2NTeRapeVjoL866O5TE/jyIkxUpdCYNXmE=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=cMaFgCsjNRZ7H1dF3oIHbb4aj0ZdL59XnB66ct9u24Eb1w4kjl7urREjkXy8FlFXiLstCI5eSsoSPUvZH31xBDObizJHt5R7myOTL4RhY62fjNcfBYF55AewX6iDMFjipibEszlAq+lhWyfLZ2dqEN8owR3ZQN90Ed0hUeSLjl8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=MBvsR78C; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="MBvsR78C" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4F0EFC4CED1; Wed, 29 Jan 2025 18:40:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1738176043; bh=KSn6f2pCC2NTeRapeVjoL866O5TE/jyIkxUpdCYNXmE=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=MBvsR78CDkj5WQJJl0nUIZys5s9cEZn+pJj3onV1p7Uj458iQURkb3a8r8HhU5vTL 65oBAw3UrofVEz6GSCoIPWMGHewkhU4zEbamIR1VQGGRiQ/P1ejx0BuTEfxa6mqZVW SLQvxUgz9mHDBkks5OKVqrmZM6+xF0QZVt+Tqe+1hAAAYGLPZXZ+owV7FFUnhX6WuB QK2WNN01gedwAKFFqeHNW6URyH9nMlr/wY8owIiYvii9gez5anpHrzeULhryvnMSnU 87LJ1Xkv5/hd6feabGl+z6D1qaLfZcjZrqoj9QEiD83CjwpE7chN75wQ42L9g8+ZuK UnF6G0GUFiUtg== Message-ID: Date: Wed, 29 Jan 2025 19:40:38 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 14/14] defconfig: Enable RZ/T2H Soc and RZ_SCI To: Thierry Bultel , Catalin Marinas , Will Deacon , Arnd Bergmann Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20250129165122.2980-1-thierry.bultel.yh@bp.renesas.com> <20250129165122.2980-15-thierry.bultel.yh@bp.renesas.com> Content-Language: en-US From: Krzysztof Kozlowski Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 29/01/2025 17:37, Thierry Bultel wrote: > Signed-off-by: Thierry Bultel > --- > arch/arm64/configs/defconfig | 2 ++ > 1 file changed, 2 insertions(+) > Cc list does not look here correct. Actually for entire set is not correct. You should always Cc your soc maintainers. > diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig > index c62831e61586..a1cc7a37386d 100644 > --- a/arch/arm64/configs/defconfig > +++ b/arch/arm64/configs/defconfig > @@ -486,6 +486,7 @@ CONFIG_SERIAL_TEGRA_TCU=y > CONFIG_SERIAL_IMX=y > CONFIG_SERIAL_IMX_CONSOLE=y > CONFIG_SERIAL_SH_SCI=y > +CONFIG_SERIAL_RZ_SCI=y > CONFIG_SERIAL_MSM=y > CONFIG_SERIAL_MSM_CONSOLE=y > CONFIG_SERIAL_QCOM_GENI=y > @@ -1457,6 +1458,7 @@ CONFIG_ARCH_R9A07G054=y > CONFIG_ARCH_R9A08G045=y > CONFIG_ARCH_R9A09G011=y > CONFIG_ARCH_R9A09G057=y > +CONFIG_ARCH_R9A09G077=y Folks, you need to stop adding user-selectable SoC-choices. This is really odd for arm64, like some old arm32 style. None of the platforms do it, including much, much bigger ones like Qualcomm. The defconfig is supposed to select only top-level ARCH for given vendor or family of devices. $ git grep ARCH_R[89] -- arch/arm64/configs/defconfig | wc -l 23 Best regards, Krzysztof