Re: increased translation cache footprint in v2.6

Marcelo Tosatti
2005-06-27T01:06:13Z

On Sun, Jun 26, 2005 at 05:33:38PM -0700, David S. Miller wrote:
> From: Marcelo Tosatti <marcelo.tosatti@cyclades.com>
> Date: Sun, 26 Jun 2005 15:52:10 -0300
>
> > Well, a TLB entry might cache different sized pages. The platform
> > support 4kb, 16kb and 8Mb (IIRC, maybe some other size also). The
> > bigger pages (8Mb) are only used to map 8Mbytes of instruction at
> > KERNELBASE, 24Mbytes of data (3 8Mbyte entries) also at KERNELBASE
> > and another 8Mbytes of the configuration registers memory space,
> > which lives outside RAM space.
>
> Why don't you use 8MB TLB entries when there is a miss to
> one of the PAGE_OFFSET pages? I'm not saying to lock them,
> just to use large 8MB TLB entries when a miss is taken for
> kernel data accesses to where the kernel maps all of lowmem.

David,

Thats a very interesting idea, will probably optimize performance in
general ("why did nobody thought of it before?" kind).

The increase in TLB miss handler size might be offset by the reduced
kernel misses...

Dan, what do you think?