From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 6063023392B for ; Fri, 10 Jul 2026 06:37:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783665463; cv=none; b=uGtIoqkDhzC3QY0GkBaLstmgbx1EvOgktb3M0nOxunPbwxHKGwfs5d85mlOutq0XEbmeHYrm0stOJmHw76Hc0b9mxONddf44j5LGdctEZGI9IKqLal/E0vzFAEShF/KaSg9ihjD8l2ASLblxZn4w48rGmoKubtL5YbYkt+GwO2w= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783665463; c=relaxed/simple; bh=DvcgE2AI+oYci9aiT+oSIXc5m/0uljUESJ/kUwIL7Rc=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=a9YM37qnrIUObyHcWlYZacyDeo7zAU95W5H6WrrKqpbTcmmjbKbGWsZS/5tyqdwzqzGsQASf6ZQbXkjcpf/lZ79duEPPckycPfPxqAGm7sGRtABmaJNrwNQhWeqf/eZLk0GxuqbQ2RRe8qPJdahNaWXql3YqDE8FAYO8UDdZu8k= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=GgjX0U5A; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="GgjX0U5A" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 88932168F; Thu, 9 Jul 2026 23:37:37 -0700 (PDT) Received: from [10.174.42.251] (unknown [10.174.42.251]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1E76B3F66F; Thu, 9 Jul 2026 23:37:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1783665461; bh=DvcgE2AI+oYci9aiT+oSIXc5m/0uljUESJ/kUwIL7Rc=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=GgjX0U5ADuLeUqFfFaF6opP4iZ82Mb09TzqfFUEt9HxxtMUYkhvg02dbbnuDoa/TF wpnqfgYP6YbCfpg1nr34ihdZD5MfLpTnbG3ENpLnv5X855TgBkihbvRqJ1lcq/IM+x lZpJv/5OpeVNCx/PsE+qW7iNpBmpT6vK+LfD2bw0= Message-ID: Date: Fri, 10 Jul 2026 12:07:36 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/6] arm64: cputype: Add C1-Nano definitions To: Linu Cherian , Catalin Marinas , Will Deacon , Ryan Roberts , Kevin Brodsky , Suzuki K Poulose , Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20260708144331.679816-1-linu.cherian@arm.com> <20260708144331.679816-3-linu.cherian@arm.com> Content-Language: en-US From: Anshuman Khandual In-Reply-To: <20260708144331.679816-3-linu.cherian@arm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 08/07/26 8:13 PM, Linu Cherian wrote: > Add cputype definitions for C1-Nano. > > The definition can be found in C1-Nano TRM, > https://developer.arm.com/documentation/107753/0002 > as part of MIDR_EL1 bit descriptions. > > This is going to be used in the bbml3 support list. > > Signed-off-by: Linu Cherian > --- > arch/arm64/include/asm/cputype.h | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h > index e41fae46426b..1fa29616e586 100644 > --- a/arch/arm64/include/asm/cputype.h > +++ b/arch/arm64/include/asm/cputype.h > @@ -100,6 +100,7 @@ > #define ARM_CPU_PART_CORTEX_A720AE 0xD89 > #define ARM_CPU_PART_C1_ULTRA 0xD8C > #define ARM_CPU_PART_NEOVERSE_N3 0xD8E > +#define ARM_CPU_PART_C1_NANO 0xD8A > #define ARM_CPU_PART_C1_PRO 0xD8B > #define ARM_CPU_PART_C1_PREMIUM 0xD90 > > @@ -195,6 +196,7 @@ > #define MIDR_CORTEX_A720AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720AE) > #define MIDR_C1_ULTRA MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_ULTRA) > #define MIDR_NEOVERSE_N3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N3) > +#define MIDR_C1_NANO MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_NANO) > #define MIDR_C1_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_PRO) > #define MIDR_C1_PREMIUM MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_PREMIUM) > #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) Reviewed-by: Anshuman Khandual