From: "Liang, Kan" <kan.liang@linux.intel.com>
To: Peter Zijlstra <peterz@infradead.org>
Cc: mingo@redhat.com, acme@kernel.org, tglx@linutronix.de,
bp@alien8.de, x86@kernel.org, linux-kernel@vger.kernel.org,
mark.rutland@arm.com, alexander.shishkin@linux.intel.com,
jolsa@redhat.com, namhyung@kernel.org, dave.hansen@intel.com,
yu-cheng.yu@intel.com, bigeasy@linutronix.de, gorcunov@gmail.com,
hpa@zytor.com, alexey.budankov@linux.intel.com,
eranian@google.com, ak@linux.intel.com, like.xu@linux.intel.com,
yao.jin@linux.intel.com, wei.w.wang@intel.com
Subject: Re: [PATCH V3 13/23] perf/x86/intel/lbr: Factor out intel_pmu_store_lbr
Date: Mon, 6 Jul 2020 18:29:58 -0400 [thread overview]
Message-ID: <ddfcd90f-ca77-edf4-09b8-183efb2ae2f2@linux.intel.com> (raw)
In-Reply-To: <bf63dee4-d25f-89d8-1893-572d84cfa667@linux.intel.com>
On 7/3/2020 4:59 PM, Liang, Kan wrote:
>
>
> On 7/3/2020 3:50 PM, Peter Zijlstra wrote:
>> On Fri, Jul 03, 2020 at 05:49:19AM -0700, kan.liang@linux.intel.com
>> wrote:
>>> +static void intel_pmu_store_lbr(struct cpu_hw_events *cpuc,
>>> + struct lbr_entry *entries)
>>> +{
>>> + struct perf_branch_entry *e;
>>> + struct lbr_entry *lbr;
>>> + u64 from, to, info;
>>> + int i;
>>> +
>>> + for (i = 0; i < x86_pmu.lbr_nr; i++) {
>>> + lbr = entries ? &entries[i] : NULL;
>>> + e = &cpuc->lbr_entries[i];
>>> +
>>> + from = rdlbr_from(i, lbr);
>>> + /*
>>> + * Read LBR entries until invalid entry (0s) is detected.
>>> + */
>>> + if (!from)
>>> + break;
>>> +
>>> + to = rdlbr_to(i, lbr);
>>> + info = rdlbr_info(i, lbr);
>>> +
>>> + e->from = from;
>>> + e->to = to;
>>> + e->mispred = !!(info & LBR_INFO_MISPRED);
>>> + e->predicted = !(info & LBR_INFO_MISPRED);
>>> + e->in_tx = !!(info & LBR_INFO_IN_TX);
>>> + e->abort = !!(info & LBR_INFO_ABORT);
>>> + e->cycles = info & LBR_INFO_CYCLES;
>>> + e->type = 0;
>>> + e->reserved = 0;
>>> + }
>>> +
>>> + cpuc->lbr_stack.nr = i;
>>> +}
>>
>> If I'm not mistaken, this correctly deals with LBR_FORMAT_INFO, so can't
>> we also use the intel_pmu_arch_lbr_read() function for that case?
>
There is another more severe issue which prevents sharing the read of
Arch LBR with LBR_FORMAT_INFO. Sorry I missed it.
For the legacy LBR, the youngest branch is stored in TOS MSR. The next
youngest is in (TOS - 1)...
For Arch LBR and LBR PEBS, the youngest branch is always in entry 0. The
next youngest is in entry 1...
The growth of the legacy LBR is in a reversed order of Arch LBR and LBR
PEBS. The legacy LBR also relies on TOS. I'm afraid we cannot use the
intel_pmu_arch_lbr_read() function for LBR_FORMAT_INFO.
I think I will only send a patch to support NO_{CYCLES,FLAGS} for all
LBR formats.
Thanks,
Kan
next prev parent reply other threads:[~2020-07-06 22:30 UTC|newest]
Thread overview: 59+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-03 12:49 [PATCH V3 00/23] Support Architectural LBR kan.liang
2020-07-03 12:49 ` [PATCH V3 01/23] x86/cpufeatures: Add Architectural LBRs feature bit kan.liang
2020-07-08 9:51 ` [tip: perf/core] " tip-bot2 for Kan Liang
2020-07-09 23:00 ` Dave Hansen
2020-07-10 9:51 ` Peter Zijlstra
2020-07-10 14:09 ` Liang, Kan
2020-07-03 12:49 ` [PATCH V3 02/23] perf/x86/intel/lbr: Add a function pointer for LBR reset kan.liang
2020-07-08 9:51 ` [tip: perf/core] " tip-bot2 for Kan Liang
2020-07-03 12:49 ` [PATCH V3 03/23] perf/x86/intel/lbr: Add a function pointer for LBR read kan.liang
2020-07-08 9:51 ` [tip: perf/core] " tip-bot2 for Kan Liang
2020-07-03 12:49 ` [PATCH V3 04/23] perf/x86/intel/lbr: Add the function pointers for LBR save and restore kan.liang
2020-07-08 9:51 ` [tip: perf/core] " tip-bot2 for Kan Liang
2020-07-03 12:49 ` [PATCH V3 05/23] perf/x86/intel/lbr: Factor out a new struct for generic optimization kan.liang
2020-07-08 9:51 ` [tip: perf/core] " tip-bot2 for Kan Liang
2020-07-03 12:49 ` [PATCH V3 06/23] perf/x86/intel/lbr: Use dynamic data structure for task_ctx kan.liang
2020-07-08 9:51 ` [tip: perf/core] " tip-bot2 for Kan Liang
2020-07-03 12:49 ` [PATCH V3 07/23] x86/msr-index: Add bunch of MSRs for Arch LBR kan.liang
2020-07-08 9:51 ` [tip: perf/core] " tip-bot2 for Kan Liang
2020-07-03 12:49 ` [PATCH V3 08/23] perf/x86: Expose CPUID enumeration bits for arch LBR kan.liang
2020-07-08 9:51 ` [tip: perf/core] " tip-bot2 for Kan Liang
2020-07-03 12:49 ` [PATCH V3 09/23] perf/x86/intel/lbr: Support LBR_CTL kan.liang
2020-07-08 9:51 ` [tip: perf/core] " tip-bot2 for Kan Liang
2020-07-03 12:49 ` [PATCH V3 10/23] perf/x86/intel/lbr: Unify the stored format of LBR information kan.liang
2020-07-08 9:51 ` [tip: perf/core] " tip-bot2 for Kan Liang
2020-07-03 12:49 ` [PATCH V3 11/23] perf/x86/intel/lbr: Mark the {rd,wr}lbr_{to,from} wrappers __always_inline kan.liang
2020-07-08 9:51 ` [tip: perf/core] " tip-bot2 for Kan Liang
2020-07-03 12:49 ` [PATCH V3 12/23] perf/x86/intel/lbr: Factor out rdlbr_all() and wrlbr_all() kan.liang
2020-07-08 9:51 ` [tip: perf/core] " tip-bot2 for Kan Liang
2020-07-03 12:49 ` [PATCH V3 13/23] perf/x86/intel/lbr: Factor out intel_pmu_store_lbr kan.liang
2020-07-03 19:50 ` Peter Zijlstra
2020-07-03 20:59 ` Liang, Kan
2020-07-06 10:25 ` Peter Zijlstra
2020-07-06 13:32 ` Liang, Kan
2020-07-06 14:25 ` Peter Zijlstra
2020-07-06 22:29 ` Liang, Kan [this message]
2020-07-07 7:40 ` Peter Zijlstra
2020-07-08 9:51 ` [tip: perf/core] " tip-bot2 for Kan Liang
2020-07-03 12:49 ` [PATCH V3 14/23] perf/x86/intel/lbr: Support Architectural LBR kan.liang
2020-07-08 9:51 ` [tip: perf/core] " tip-bot2 for Kan Liang
2020-07-03 12:49 ` [PATCH V3 15/23] perf/core: Factor out functions to allocate/free the task_ctx_data kan.liang
2020-07-08 9:51 ` [tip: perf/core] " tip-bot2 for Kan Liang
2020-07-03 12:49 ` [PATCH V3 16/23] perf/core: Use kmem_cache to allocate the PMU specific data kan.liang
2020-07-08 9:51 ` [tip: perf/core] " tip-bot2 for Kan Liang
2020-07-03 12:49 ` [PATCH V3 17/23] perf/x86/intel/lbr: Create kmem_cache for the LBR context data kan.liang
2020-07-08 9:51 ` [tip: perf/core] " tip-bot2 for Kan Liang
2020-07-03 12:49 ` [PATCH V3 18/23] perf/x86: Remove task_ctx_size kan.liang
2020-07-08 9:51 ` [tip: perf/core] " tip-bot2 for Kan Liang
2020-07-03 12:49 ` [PATCH V3 19/23] x86/fpu: Use proper mask to replace full instruction mask kan.liang
2020-07-08 9:51 ` [tip: perf/core] " tip-bot2 for Kan Liang
2020-07-03 12:49 ` [PATCH V3 20/23] x86/fpu/xstate: Support dynamic supervisor feature for LBR kan.liang
2020-07-08 9:51 ` [tip: perf/core] " tip-bot2 for Kan Liang
2021-05-27 22:15 ` Thomas Gleixner
2020-07-03 12:49 ` [PATCH V3 21/23] x86/fpu/xstate: Add helpers for LBR dynamic supervisor feature kan.liang
2020-07-08 9:51 ` [tip: perf/core] " tip-bot2 for Kan Liang
2020-07-03 12:49 ` [PATCH V3 22/23] perf/x86/intel/lbr: Support XSAVES/XRSTORS for LBR context switch kan.liang
2020-07-08 9:51 ` [tip: perf/core] " tip-bot2 for Kan Liang
2020-07-03 12:49 ` [PATCH V3 23/23] perf/x86/intel/lbr: Support XSAVES for arch LBR read kan.liang
2020-07-08 9:51 ` [tip: perf/core] " tip-bot2 for Kan Liang
2020-07-03 19:34 ` [PATCH V3 00/23] Support Architectural LBR Peter Zijlstra
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