Re: [PATCH V4 12/15] dt-bindings: reset: mediatek: Add infra_ao reset bit for MT8192/MT8195

Rex-BC Chen
2022-04-28T11:18:57Z

On Thu, 2022-04-28 at 15:18 +0800, Krzysztof Kozlowski wrote:
> On 27/04/2022 05:09, Rex-BC Chen wrote:
> > - To support reset of infra_ao, add the bit definition of
> > thermal/PCIe/SVS for MT8192.
> > - To support reset of infra_ao, add the bit definition of
> > thermal/SVS for MT8195.
> > - Add the driver comment to separate the reset index for
> > TOPRGU and INFRA.
> >
> > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> > ---
> > include/dt-bindings/reset/mt8192-resets.h | 8 ++++++++
> > include/dt-bindings/reset/mt8195-resets.h | 6 ++++++
> > 2 files changed, 14 insertions(+)
> >
> > diff --git a/include/dt-bindings/reset/mt8192-resets.h
> > b/include/dt-bindings/reset/mt8192-resets.h
> > index be9a7ca245b9..ee0ca02a39bf 100644
> > --- a/include/dt-bindings/reset/mt8192-resets.h
> > +++ b/include/dt-bindings/reset/mt8192-resets.h
> > @@ -7,6 +7,7 @@
> > #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8192
> > #define _DT_BINDINGS_RESET_CONTROLLER_MT8192
> >
> > +/* TOPRGU resets */
> > #define MT8192_TOPRGU_MM_SW_RST
> > 1
> > #define MT8192_TOPRGU_MFG_SW_RST 2
> > #define MT8192_TOPRGU_VENC_SW_RST 3
> > @@ -27,4 +28,11 @@
> >
> > #define MT8192_TOPRGU_SW_RST_NUM 23
> >
> > +/* INFRA resets */
> > +#define MT8192_INFRA_THERMAL_CTRL_RST 0
> > +#define MT8192_INFRA_PEXTP_PHY_RST 79
> > +#define MT8192_INFRA_PTP_RST
> > 101
> > +#define MT8192_INFRA_RST4_PCIE_TOP 129
> > +#define MT8192_INFRA_THERMAL_CTRL_MCU_RST 140
>
> This is still wrong. I gave you exactly what has to be used:
> 0
> 1
> 2
> ...
>
> It's a decimal number incremented by one.
>
>
> > +
> > #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */
> > diff --git a/include/dt-bindings/reset/mt8195-resets.h
> > b/include/dt-bindings/reset/mt8195-resets.h
> > index a26bccc8b957..a3226f40779c 100644
> > --- a/include/dt-bindings/reset/mt8195-resets.h
> > +++ b/include/dt-bindings/reset/mt8195-resets.h
> > @@ -7,6 +7,7 @@
> > #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8195
> > #define _DT_BINDINGS_RESET_CONTROLLER_MT8195
> >
> > +/* TOPRGU resets */
> > #define MT8195_TOPRGU_CONN_MCU_SW_RST 0
> > #define MT8195_TOPRGU_INFRA_GRST_SW_RST 1
> > #define MT8195_TOPRGU_APU_SW_RST 2
> > @@ -26,4 +27,9 @@
> >
> > #define MT8195_TOPRGU_SW_RST_NUM 16
> >
> > +/* INFRA resets */
> > +#define MT8195_INFRA_THERMAL_AP_RST 0
> > +#define MT8195_INFRA_PTP_RST 101
> > +#define MT8195_INFRA_THERMAL_MCU_RST 138
>
> Same issue.
>
>
> Best regards,
> Krzysztof

Hello Krzysztof,

Thanks for your review.
As mentioned in prvious mail, I will add all reset bits in MT8192 and
MT8195.

BRs,
Rex