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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-af91a0766d1sm2630993066b.18.2025.08.14.10.52.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 14 Aug 2025 10:52:16 -0700 (PDT) Message-ID: Date: Thu, 14 Aug 2025 19:52:13 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] drm/msm: adreno: a6xx: enable GMU bandwidth voting for x1e80100 GPU To: Akhil P Oommen , Neil Armstrong , Rob Clark , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov References: <20250725-topic-x1e80100-gpu-bwvote-v2-1-58d2fbb6a127@linaro.org> <33442cc4-a205-46a8-a2b8-5c85c236c8d4@oss.qualcomm.com> <269506b6-f51b-45cc-b7cc-7ad0e5ceea47@linaro.org> <1727374d-0461-4442-ab35-9acb8ef7f666@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <1727374d-0461-4442-ab35-9acb8ef7f666@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODExMDA3NSBTYWx0ZWRfX719I2MqaIPRD +ZHII6Zd2XFVs2poxXwqQex2peV0mmgkOQbhJnA0mM4d7gPObP4U1gvwq7uZR68J3yefKBruYVX KXFTmqzIDZFqLZwyYbHeaM8+XuXwdp1BxznmsgBAap9gUdlPARhCPfy2a34y7EtD6Xzoli9kx5A h/6hn9T0HKpTKak62TTBTHIRBpNibVlIQFmXcC8JfSCz7ka14YsrI+61c2H5eT/fnFUMBWQ4E49 85uFLS6eul5KifSLHVq4aX7HVRGOuXfRNzV4jKb7LrXi+HZKpE32V6CiaOG3NUprjoCq3Ltt0UB xONNW+3Sxn08mVQ0MBOQK13E39Qm3pdZjKr4WBzXO0NOzxYbueeBHoQKqiYGSgPD42KMj+Dy3SF RISZJiOr X-Authority-Analysis: v=2.4 cv=TLZFS0la c=1 sm=1 tr=0 ts=689e2253 cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=KKAkSRfTAAAA:8 a=06jlRiaS0U7peylTb-kA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=dawVfQjAaf238kedN5IG:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: sxgzODXPLM6qYy8QHK-F-mIF2AZRA9Mm X-Proofpoint-ORIG-GUID: sxgzODXPLM6qYy8QHK-F-mIF2AZRA9Mm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-13_02,2025-08-14_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 phishscore=0 malwarescore=0 spamscore=0 priorityscore=1501 bulkscore=0 adultscore=0 impostorscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508110075 On 8/14/25 6:38 PM, Akhil P Oommen wrote: > On 8/14/2025 7:56 PM, Neil Armstrong wrote: >> Hi, >> >> On 14/08/2025 13:22, Konrad Dybcio wrote: >>> On 8/14/25 1:21 PM, Konrad Dybcio wrote: >>>> On 7/31/25 12:19 PM, Konrad Dybcio wrote: >>>>> On 7/25/25 10:35 AM, Neil Armstrong wrote: >>>>>> The Adreno GPU Management Unit (GMU) can also scale DDR Bandwidth >>>>>> along >>>>>> the Frequency and Power Domain level, but by default we leave the >>>>>> OPP core scale the interconnect ddr path. >>>>>> >>>>>> Declare the Bus Control Modules (BCMs) and the corresponding >>>>>> parameters >>>>>> in the GPU info struct to allow the GMU to vote for the bandwidth. >>>>>> >>>>>> Reviewed-by: Dmitry Baryshkov >>>>>> Signed-off-by: Neil Armstrong >>>>>> --- >>>>>> Changes in v2: >>>>>> - Used proper ACV perfmode bit/freq >>>>>> - Link to v1: https://lore.kernel.org/r/20250721-topic-x1e80100- >>>>>> gpu-bwvote-v1-1-946619b0f73a@linaro.org >>>>>> --- >>>>>>   drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 11 +++++++++++ >>>>>>   1 file changed, 11 insertions(+) >>>>>> >>>>>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/ >>>>>> gpu/drm/msm/adreno/a6xx_catalog.c >>>>>> index >>>>>> 00e1afd46b81546eec03e22cda9e9a604f6f3b60..892f98b1f2ae582268adebd758437ff60456cdd5 100644 >>>>>> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >>>>>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >>>>>> @@ -1440,6 +1440,17 @@ static const struct adreno_info a7xx_gpus[] = { >>>>>>               .pwrup_reglist = &a7xx_pwrup_reglist, >>>>>>               .gmu_chipid = 0x7050001, >>>>>>               .gmu_cgc_mode = 0x00020202, >>>>>> +            .bcms = (const struct a6xx_bcm[]) { >>>>>> +                { .name = "SH0", .buswidth = 16 }, >>>>>> +                { .name = "MC0", .buswidth = 4 }, >>>>>> +                { >>>>>> +                    .name = "ACV", >>>>>> +                    .fixed = true, >>>>>> +                    .perfmode = BIT(3), >>>>>> +                    .perfmode_bw = 16500000, >>>>> >>>>> Reviewed-by: Konrad Dybcio >>>> >>>> Actually no, BIT(3) is for the CPU (OS), GPU should use BIT(2) > > You are right that BIT(2) is GPU specific, but that support was > commercialized from A7XX_GEN3. Anyway, the Win KMD uses BIT(2), so lets > use that in Linux too. > > I know some docs show BIT(2) support, but lets not bring in untested > configurations. Eh, then let's get the docs fixed if you don't trust them because we can't work like that.. FWIW this is information from per-platform RPMh cmd-db data Konrad