From: Krzysztof Kozlowski <krzk@kernel.org>
To: Xianwei Zhao <xianwei.zhao@amlogic.com>,
Neil Armstrong <neil.armstrong@linaro.org>,
Jerome Brunet <jbrunet@baylibre.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Chuan Liu <chuan.liu@amlogic.com>,
Kevin Hilman <khilman@baylibre.com>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 2/3] arm64: dts: amlogic: add some device nodes for C3
Date: Wed, 7 Aug 2024 08:38:54 +0200 [thread overview]
Message-ID: <dfcc71af-678b-47bb-b0a3-e72ada0b85bf@kernel.org> (raw)
In-Reply-To: <49b41346-a98a-470b-9572-0f81557eea29@amlogic.com>
On 07/08/2024 07:54, Xianwei Zhao wrote:
> Hi Krzysztof,
> Thanks for your reply.
>
> On 2024/8/6 21:13, Krzysztof Kozlowski wrote:
>> [ EXTERNAL EMAIL ]
>>
>> On 06/08/2024 12:27, Xianwei Zhao via B4 Relay wrote:
>>> From: Xianwei Zhao <xianwei.zhao@amlogic.com>
>>>
>>> Add some device nodes for SoC C3, including periphs clock controller
>>> node, PLL clock controller node, SPICC node, regulator node, NAND
>>> controller node, sdcard node, Ethernet MAC and PHY node.
>>>
>>> Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
>>> ---
>>> .../boot/dts/amlogic/amlogic-c3-c302x-aw409.dts | 249 +++++++++++
>>> arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi | 487 ++++++++++++++++++++-
>>> 2 files changed, 735 insertions(+), 1 deletion(-)
>>>
>>
>>
>> ...
>>
>>
>>> +
>>> + sd: mmc@8a000 {
>>> + compatible = "amlogic,meson-axg-mmc";
>>> + reg = <0x0 0x8a000 0x0 0x800>;
>>> + interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;
>>> + power-domains = <&pwrc PWRC_C3_SDCARD_ID>;
>>> + clocks = <&clkc_periphs CLKID_SYS_SD_EMMC_B>,
>>> + <&clkc_periphs CLKID_SD_EMMC_B>,
>>> + <&clkc_pll CLKID_FCLK_DIV2>;
>>> + clock-names = "core", "clkin0", "clkin1";
>>> + no-mmc;
>>> + no-sdio;
>>
>> Hm? Why are these blocks incomplete that they do not handle SDIO? Aren't
>> you putting board properties into SoC?
>> The sdacrd (mmc@8a000) depends on regulator and pinctrl(select), So some
> property fields are placed at the board level. The SDIO is connect with
> the firmware (wifi&bt). Now I'll remove SDIO implementation and wait
> until later to submit it with the firmware.
My comment applied to all your nodes.
Best regards,
Krzysztof
next prev parent reply other threads:[~2024-08-07 6:39 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-06 10:27 [PATCH 0/3] add some node for amlogic c3 Xianwei Zhao via B4 Relay
2024-08-06 10:27 ` [PATCH 1/3] dt-bindings: clock: fix C3 PLL input parameter Xianwei Zhao via B4 Relay
2024-08-06 13:10 ` Krzysztof Kozlowski
2024-08-07 1:55 ` Xianwei Zhao
2024-08-07 5:44 ` Krzysztof Kozlowski
2024-08-07 6:40 ` Xianwei Zhao
2024-08-07 7:01 ` Krzysztof Kozlowski
2024-08-07 7:56 ` Jerome Brunet
2024-08-07 8:07 ` Krzysztof Kozlowski
2024-08-07 8:23 ` Xianwei Zhao
2024-08-06 10:27 ` [PATCH 2/3] arm64: dts: amlogic: add some device nodes for C3 Xianwei Zhao via B4 Relay
2024-08-06 13:13 ` Krzysztof Kozlowski
2024-08-07 5:54 ` Xianwei Zhao
2024-08-07 6:38 ` Krzysztof Kozlowski [this message]
2024-08-06 10:27 ` [PATCH 3/3] arm64: dts: amlogic: add C3 AW419 board Xianwei Zhao via B4 Relay
2024-08-06 13:14 ` Krzysztof Kozlowski
2024-08-07 2:37 ` Xianwei Zhao
2024-08-07 5:44 ` Krzysztof Kozlowski
2024-08-07 7:25 ` Xianwei Zhao
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