From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
To: Konrad Dybcio <konrad.dybcio@linaro.org>,
Robert Marko <robimarko@gmail.com>,
linux-arm-msm@vger.kernel.org, andersson@kernel.org,
agross@kernel.org, krzysztof.kozlowski@linaro.org
Cc: marijn.suijten@somainline.org,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@somainline.org>,
Liam Girdwood <lgirdwood@gmail.com>,
Mark Brown <broonie@kernel.org>,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v9 5/6] soc: qcom: Add support for Core Power Reduction v3, v4 and Hardened
Date: Wed, 18 Jan 2023 13:50:39 +0100 [thread overview]
Message-ID: <dfecf744-30c6-e9b5-5a75-045aca840cae@collabora.com> (raw)
In-Reply-To: <233f0d52-4f9d-a512-0450-77e2fb4da878@linaro.org>
..snip..
>>> +
>>> +static const struct cpr_desc sdm630_cpr_desc = {
..snip..
>>> + },
>>> +};
>>
>> Hi Konrad, I am trying to add IPQ8074 support to CPR as its the last thing
>> missing for upstream CPU scaling, and I really want to get rid of the downstream driver.
>>
>> However, I am having hard time figuring some of these parameters, some are easy to
>> read from the DTS or driver defines, however arent the fuse corners supposed to be read
>> from the fuses and not hardcocded in the thread structures?
> They reside in socname-regulator.dtsi most of the time.
> Some parameters are read from fuses (per-unit capabilities
> that let your specific chip run at a specific voltage offset),
> but there's also some per-SoC-model data that needs to be
> taken into account when performing the calculations.. This
> is actually a smart move from Qualcomm (well, for them
> anyway), as they put as little data in fuses as possible,
> saving them space on this tiiiiny ROM.
>
>>
>> Mind you, I dont have any docs so I am mostly using the downstream kernel as the reference.
> This driver doesn't do anything more than its downstream
> counterpart, everything we need should be there on msm-X.Y.
>
> One flaw in this revision is that it doesn't yet support
> multiple speed bins, so if your SoC has n of those, you
> may get confused by n sets of values.. This is easy to
> improve on in future, but this initial submission is
> already very fat to begin with..
>
>
Hello Robert, Konrad,
since it is a bit difficult to find and follow discussions started/written in
a random place of a file (and reviews, as well), can you please cut off the
unnecessary text before sending out a reply?
Anyway, the fuse corners are actually read from fuses; the values that you see
hardcoded are references and safety min/max values which purpose is to both
perform calculation after fuse reading and to ensure safety (example: you put
a wrong bits range to read from fuses, the driver saves you by refusing to set
a very high voltage on the CPU core[s]).
As for where to find the values, I personally don't precisely remember, as that
was done more than 1.5 years ago, but what I recall is that they're scattered
across multiple files, including devicetree and drivers.
I also remember that I had to add debugging prints to the downstream driver in
order to get one of the values right... but that may have been due to MSM8998
values being a bit strange.
Thanks,
Angelo
next prev parent reply other threads:[~2023-01-18 13:24 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20230116093845.72621-1-konrad.dybcio@linaro.org>
2023-01-16 9:38 ` [PATCH v9 1/6] MAINTAINERS: Add entry for Qualcomm CPRv3/v4/Hardened driver Konrad Dybcio
2023-01-16 9:38 ` [PATCH v9 2/6] dt-bindings: soc: qcom: cpr3: Add bindings for CPR3 driver Konrad Dybcio
2023-01-16 9:43 ` Konrad Dybcio
2023-01-16 11:26 ` Konrad Dybcio
2023-01-16 16:36 ` Rob Herring
2023-01-16 17:03 ` Konrad Dybcio
2023-01-16 9:38 ` [PATCH v9 3/6] dt-bindings: opp: v2-qcom-level: Let qcom,opp-fuse-level be a 2-long array Konrad Dybcio
2023-01-16 9:42 ` Viresh Kumar
2023-01-16 9:38 ` [PATCH v9 4/6] soc: qcom: cpr: Move common functions to new file Konrad Dybcio
2023-01-16 9:38 ` [PATCH v9 5/6] soc: qcom: Add support for Core Power Reduction v3, v4 and Hardened Konrad Dybcio
2023-01-17 12:17 ` Robert Marko
2023-01-18 12:37 ` Konrad Dybcio
2023-01-18 12:50 ` AngeloGioacchino Del Regno [this message]
2023-01-16 9:38 ` [PATCH v9 6/6] arm64: dts: qcom: msm8998: Configure CPRh Konrad Dybcio
2023-01-16 14:30 ` Konrad Dybcio
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=dfecf744-30c6-e9b5-5a75-045aca840cae@collabora.com \
--to=angelogioacchino.delregno@collabora.com \
--cc=agross@kernel.org \
--cc=andersson@kernel.org \
--cc=angelogioacchino.delregno@somainline.org \
--cc=broonie@kernel.org \
--cc=konrad.dybcio@linaro.org \
--cc=krzysztof.kozlowski@linaro.org \
--cc=lgirdwood@gmail.com \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=marijn.suijten@somainline.org \
--cc=robimarko@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox