From: Sergei Shtylyov <sergei.shtylyov@gmail.com>
To: Nikita Yushchenko <nikita.yoush@cogentembedded.com>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>
Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] clk: renesas: r8a7799[05]: Add MLP clocks
Date: Sun, 26 Dec 2021 20:46:50 +0300 [thread overview]
Message-ID: <e0a56147-e800-914b-1df3-51ca7003a69d@gmail.com> (raw)
In-Reply-To: <20211225193957.2195012-1-nikita.yoush@cogentembedded.com>
On 25.12.2021 22:39, Nikita Yushchenko wrote:
> Add clocks for MLP modules on Renesas R-Car E3 and D3 SoCs.
>
> Similar to other R-Car Gen3 SoC, exact information on parent for MLP
> clock on E3 and D3 is not available. However, since parent for this
> clocl is not anyhow software-controllable, the only harm from this
s/clocl/clock/. :-)
> is inexact information exported via debugfs. So just keep the parent
> set in the same way as with other Gen3 SoCs.
>
> Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
[...]
MBR, Sergey
next prev parent reply other threads:[~2021-12-26 17:47 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-25 19:39 [PATCH] clk: renesas: r8a7799[05]: Add MLP clocks Nikita Yushchenko
2021-12-26 17:46 ` Sergei Shtylyov [this message]
2022-01-10 15:06 ` Geert Uytterhoeven
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