From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 729231428F4 for ; Fri, 13 Feb 2026 00:34:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770942843; cv=none; b=FD5xBUyjOAS37ktylvDs1onn/cyf2CuT1YgV8qoAGjcMyw99O5YVkkY+NDWAgxuYp1YtnwlgoDIwBheT0ErfUN8p6xgB5gsmx4iyo01kDBGCBtKzMMhcmqajaxT+Gd+hHEJxPBiwuNxNdER+PUJpPi3XmQKhKOgaVr3XX/pOKNc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770942843; c=relaxed/simple; bh=b02J84ZDm/mvQQL0gYw8sAXPPl6ARimM8FJDFIIMhJE=; h=Date:From:To:cc:Subject:In-Reply-To:Message-ID:References: MIME-Version:Content-Type; b=UnjKTE46SYYeYpYXOVsnFwmYhkXXLaEnRCmhT+6sbNSCm2i3WjSJZ7TTAutEC98ITBqwg95Ku6oSofOl2qeY73M543mZo/+XDGbK5ObYX1etV5eIkSmokOAj6KsuePQan0hobN7kNjqaBOoz0tPDLDkDZosNwhFrclBdefwz2lA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=pJAuRH6w; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="pJAuRH6w" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5D413C4CEF7; Fri, 13 Feb 2026 00:34:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1770942843; bh=b02J84ZDm/mvQQL0gYw8sAXPPl6ARimM8FJDFIIMhJE=; h=Date:From:To:cc:Subject:In-Reply-To:References:From; b=pJAuRH6wYxE+aUos01e0VtF2nlAvNajbbA3+RaG/FnIE9cMZ45VEIYZvg17hLQT4Q vjOH/qfHXmI1G8ixpiWP006JCwFSCmm8uw5oj39jEsMC+0sxQpE/UgQhTFgmm6Kqz9 Xe6pYNRO9+9jFswMs+xqrxLcHuUT+ypxsf3G+km/5ZbzvD2LQDC3Tqe9heOgcpt23+ MuEiQZ4d1NM80MCa+dB6cwNAM429psbv3IMz6vlJ6mGt2l7Xk+3Fq93TkOixvOzUgJ Mk0//LhvYT8ldCz8FKgyAEL0bWWQvdR8jXf7cRUBI1fMWZoG0+hEbOnaIJvVAqUIOK v883q6aTFkSgg== Date: Thu, 12 Feb 2026 17:34:00 -0700 (MST) From: Paul Walmsley To: Himanshu Chauhan cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, shuah@kernel.org Subject: Re: [PATCH v2 0/2] riscv: Introduce support for hardware break/watchpoints In-Reply-To: <20260106082021.2680658-1-himanshu.chauhan@oss.qualcomm.com> Message-ID: References: <20260106082021.2680658-1-himanshu.chauhan@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Hi Himanshu, On Tue, 6 Jan 2026, Himanshu Chauhan wrote: > This patchset adds support of hardware breakpoints and watchpoints in RISC-V > architecture. The framework is built on top of perf subsystem and SBI debug > trigger extension. > > Currently following features are not supported and are in works: > - Ptrace support > - Single stepping > - Virtualization of debug triggers > > The SBI debug trigger extension proposal can be found in Chapter-19 of SBI specification: > https://github.com/riscv-non-isa/riscv-sbi-doc/releases/download/v3.0/riscv-sbi.pdf > > The Sdtrig ISA is part of RISC-V debug specification which can be found at: > https://github.com/riscv/riscv-debug-spec Can you fix the checkpatch issues with this series? Please use --strict. In the meantime, I'll add it as an experimental branch, until those get sorted out. - Paul