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Wysocki" , Viresh Kumar , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Dhananjay Ugwekar , Huang Rui , Perry Yuan , Meng Li References: <20250411081439.27652-1-kprateek.nayak@amd.com> Content-Language: en-US From: Mario Limonciello In-Reply-To: <20250411081439.27652-1-kprateek.nayak@amd.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: SA9P221CA0006.NAMP221.PROD.OUTLOOK.COM (2603:10b6:806:25::11) To MN0PR12MB6101.namprd12.prod.outlook.com (2603:10b6:208:3cb::10) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN0PR12MB6101:EE_|MW4PR12MB6950:EE_ X-MS-Office365-Filtering-Correlation-Id: 17fcab04-a210-4637-1b4d-08dd791dd2c5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|366016; X-Microsoft-Antispam-Message-Info: =?utf-8?B?ZktDTGVNUVVmQXNFL0pRbm5LeGc5b2x2T1lnZ2FZQTZjSGJDaEw5UFRwTHpP?= =?utf-8?B?cDZyOFM3cmxSSWJUbmh2cnhFSDBKUkhaYzlrUkVQdm53QU4rc0RQaTFJMVp5?= =?utf-8?B?QW5nWG52azFRMkdib1BqK28yNDBZcWR2V2ZQZmZoZENYb3VCRDdCMFlwazZR?= =?utf-8?B?R1VCajBqNVVwSFN1ZG9pSm43c2xJMkFZaDBNbWFTeDlackcremovMThNa0dC?= =?utf-8?B?dHY1TkZETXdtaGsxYk9DQm05TUNSL2pweEJWZTBYcjNEWGlNODhWeElmUjRt?= =?utf-8?B?Qm1hRkV6dVl2bDUxZUJMMm5NSkpra1ErSU44a3hIMThXMTBjVzhCNTd4aExE?= =?utf-8?B?T1JZMmxJckd4SWNDbWFuSUNXOUdzVjFUTzhzRGgzcXFJNVhrUmFlZEhobjRk?= =?utf-8?B?OVN3OG9LL2Y4RmNCNzQzSkl0bUZTcEtXOTBNb2h4U09XMm82SDc0dUY5VHhT?= =?utf-8?B?Q2t3cUNyVnMrQ1c5aEVyc1VERTdwRDhNbVhFUXhneU5nMXp5SmtuUENNQmNW?= =?utf-8?B?b0JMaG5tZnA3dU9jRC9MNXZTTENPZmNyWkt2eTN3QnV0bTZnRHo2L28rL251?= =?utf-8?B?K1U1dWNYeit4UE9GZkM2UnkvQkkvcmZZOURpTVhpOEZDNWd4ZlJydlBRUDl4?= =?utf-8?B?RGV1RnhYWkJLUTNCeXo5bVVsZlFKWExTMmZNQXNQOXlTQkJhQzgzNHlqOElv?= =?utf-8?B?VWhqWVl0aXgrRnRZZWVkanhUZWIwalBkZnFJWHJOeVpiMTFwamRNckR0Z2Z4?= =?utf-8?B?U2hZRy9RR2UvV1ZsMWRwRWZ6T25Sak5PR2F1WFpkN3lKcm5yeGZpRm5MWTNP?= =?utf-8?B?aEFpbkZGSmY3MHg4Zitoek9CSjF5SmFOdGdjbEhtZzVPVW5qY2pnVGYxZWY1?= =?utf-8?B?K3UzYXBseldCdThuakxhZVBaaEdWczlPL3dNN2R0dXVQaUFYOHlwZjV6T0FG?= =?utf-8?B?QWVCbllNL3JGcnpRclk2QjhFTnlEODZjZWFxa1NxUDl0ZElDVTVxZ1dDNnk2?= =?utf-8?B?MTFobXVKOThtQmVlRkJoOE8yWFpGanlrNXd5Rjc2MW15NXZnWmNzWmZrL3ZE?= =?utf-8?B?YW1reWJicHRBYm1UV3Z6SWRqYmhPa3JHT2ZtSksyUVo1RU1vbjJ0eUJrTXN4?= =?utf-8?B?MDBRaldzZzZqTWdNbGtkaXB6T3UySDBzQnRpUGFNUnN4eS8wUWN4c3RQMVh4?= =?utf-8?B?MDlNQXNSQnoyUGNDOG4xZy84S2hvWW1UWjdXaXUrNklhY1VYU0kyR2tiSmky?= =?utf-8?B?a3dQRU9CWk05YXdNYzB6S0Rsb0tBL2hITVdOeUVIM0g1RjNEMWJ2OElqOGxy?= =?utf-8?B?WndPYVp6MVMvc3dyUmxzRXJyNTJ6NS9YVSs0bVRNTzhONWhSNms0cVNneFdi?= =?utf-8?B?Wk5JaTJOaXdrREVjZXJIUHBOalIvUDQ2QzFBdG9lU2haN0RjK1FrRU9sVVQy?= =?utf-8?B?cXE4aGdKMnNQUitYaUF1ZjF4TVJDTlhZWWZvSWkvN29KOFNHVHJRbzBtc0c2?= =?utf-8?B?eDZSWGJBNDhLeGp3RVhzVkwzL0ZMNHhFK1hsQkE3eW9Vczlpakd1MnFvTWpV?= =?utf-8?B?eEkxcXpGWUVMU3BEc2xMQi9NS0RVcjhDRzlwZmJLK09aUjk3VlRBcnJkZlFz?= =?utf-8?B?MEtBSTZERk9aQkRzeDRmTTVNWER6NHQ5ME1ENUJwb3lKODVYcjBRMU81SzJw?= =?utf-8?B?SXB4WlU2WlZQaU90N05tNTV5SW1iK1AzUDc0K2VxaHpBbDJxa3JVVWs1d2RK?= =?utf-8?B?UU92WHdMaTZJaW50NHF5M2FOVDhOTE9uQVJYUncxKzEzSGE4OEVVSlVPb1R6?= =?utf-8?B?YXpkd1pXS1VTWDVPdTFMK1lNYTlwR1FhbWt3VlZXRFZza05lR2NjemxMRnFx?= =?utf-8?B?NWVMbVlJQ0Y4aW9meE9lTktScC9BOWxIK1RUVkxuaVRLMzBxVXFnbUczZERS?= =?utf-8?Q?5B9rlklDDw8=3D?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MN0PR12MB6101.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(376014)(366016);DIR:OUT;SFP:1101; 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On AMD systems that support Preferred Core rankings, sched > domains are rebuilt when ITMT support is enabled for the first time from > amd_pstate*_cpu_init(). > > Since amd_pstate*_cpu_init() is called to initialize the cpudata for > each CPU, the ITMT support is enabled after the first CPU initializes > its asym priority but this is too early since other CPUs have not yet > initialized their asym priorities and the sched domain is rebuilt only > once when the support is toggled on for the first time. > > Initialize the asym priorities first in amd_pstate*_cpu_init() and then > enable ITMT support later in amd_pstate_register_driver() to ensure all > CPUs have correctly initialized their asym priorities before sched > domain hierarchy is rebuilt. > > Clear the ITMT support when the amd-pstate driver unregisters since core > rankings cannot be trusted unless the update_limits() callback is > operational. > > Remove the delayed work mechanism now that ITMT support is only toggled > from the driver init path which is outside the cpuhp critical section. > > Fixes: f3a052391822 ("cpufreq: amd-pstate: Enable amd-pstate preferred core support") > Signed-off-by: K Prateek Nayak Reviewed-by: Mario Limonciello Will queue it up for testing. > --- > v1..v2: > > o Retained the name amd_pstate_init_prefcore() (Mario) > > o Moved sched_set_itmt_support() towards the end of > amd_pstate_register_driver() to address mode switch scenarios. > > o Disable ITMT support when driver unregisters to prevent incorrect ITMT > behavior in absence of update_limits() callback. > > v1: https://lore.kernel.org/lkml/20250409030004.23008-1-kprateek.nayak@amd.com/ > --- > drivers/cpufreq/amd-pstate.c | 25 ++++++++----------------- > 1 file changed, 8 insertions(+), 17 deletions(-) > > diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c > index c54c031939c8..b961f3a3b580 100644 > --- a/drivers/cpufreq/amd-pstate.c > +++ b/drivers/cpufreq/amd-pstate.c > @@ -794,16 +794,6 @@ static void amd_perf_ctl_reset(unsigned int cpu) > wrmsrl_on_cpu(cpu, MSR_AMD_PERF_CTL, 0); > } > > -/* > - * Set amd-pstate preferred core enable can't be done directly from cpufreq callbacks > - * due to locking, so queue the work for later. > - */ > -static void amd_pstste_sched_prefcore_workfn(struct work_struct *work) > -{ > - sched_set_itmt_support(); > -} > -static DECLARE_WORK(sched_prefcore_work, amd_pstste_sched_prefcore_workfn); > - > #define CPPC_MAX_PERF U8_MAX > > static void amd_pstate_init_prefcore(struct amd_cpudata *cpudata) > @@ -814,14 +804,8 @@ static void amd_pstate_init_prefcore(struct amd_cpudata *cpudata) > > cpudata->hw_prefcore = true; > > - /* > - * The priorities can be set regardless of whether or not > - * sched_set_itmt_support(true) has been called and it is valid to > - * update them at any time after it has been called. > - */ > + /* Priorities must be initialized before ITMT support can be toggled on. */ > sched_set_itmt_core_prio((int)READ_ONCE(cpudata->prefcore_ranking), cpudata->cpu); > - > - schedule_work(&sched_prefcore_work); > } > > static void amd_pstate_update_limits(unsigned int cpu) > @@ -1196,6 +1180,9 @@ static ssize_t show_energy_performance_preference( > > static void amd_pstate_driver_cleanup(void) > { > + if (amd_pstate_prefcore) > + sched_clear_itmt_support(); > + > cppc_state = AMD_PSTATE_DISABLE; > current_pstate_driver = NULL; > } > @@ -1238,6 +1225,10 @@ static int amd_pstate_register_driver(int mode) > return ret; > } > > + /* Enable ITMT support once all CPUs have initialized their asym priorities. */ > + if (amd_pstate_prefcore) > + sched_set_itmt_support(); > + > return 0; > } > > > base-commit: 56a49e19e1aea1374e9ba58cfd40260587bb7355