* [PATCH v4 01/30] drm/msm/dpu: stop passing mdss_ver to setup_timing_gen()
2025-05-19 16:04 [PATCH v4 00/30] drm/msm/dpu: rework HW block feature handling Dmitry Baryshkov
@ 2025-05-19 16:04 ` Dmitry Baryshkov
2025-05-19 19:26 ` neil.armstrong
2025-05-19 16:04 ` [PATCH v4 02/30] drm/msm/dpu: drop INTF_SC7280_MASK Dmitry Baryshkov
` (28 subsequent siblings)
29 siblings, 1 reply; 64+ messages in thread
From: Dmitry Baryshkov @ 2025-05-19 16:04 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Sean Paul, Marijn Suijten, David Airlie,
Simona Vetter, Vinod Koul, Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel,
Dmitry Baryshkov
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
As a preparation to further MDSS-revision cleanups stop passing MDSS
revision to the setup_timing_gen() callback. Instead store a pointer to
it inside struct dpu_hw_intf and use it diretly. It's not that the MDSS
revision can chance between dpu_hw_intf_init() and
dpu_encoder_phys_vid_setup_timing_engine().
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 3 +--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 7 ++++---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 5 +++--
3 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index 8a618841e3ea89acfe4a42d48319a6c54a1b3495..d35d15b60260037c5c0c369cb061e7759243b6fd 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -309,8 +309,7 @@ static void dpu_encoder_phys_vid_setup_timing_engine(
spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
phys_enc->hw_intf->ops.setup_timing_gen(phys_enc->hw_intf,
- &timing_params, fmt,
- phys_enc->dpu_kms->catalog->mdss_ver);
+ &timing_params, fmt);
phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg);
/* setup which pp blk will connect to this intf */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index fb1d25baa518057e74fec3406faffd48969d492b..1d56c21ac79095ab515aeb485346e1eb5793c260 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
@@ -98,8 +98,7 @@
static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *intf,
const struct dpu_hw_intf_timing_params *p,
- const struct msm_format *fmt,
- const struct dpu_mdss_version *mdss_ver)
+ const struct msm_format *fmt)
{
struct dpu_hw_blk_reg_map *c = &intf->hw;
u32 hsync_period, vsync_period;
@@ -180,7 +179,7 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *intf,
/* TODO: handle DSC+DP case, we only handle DSC+DSI case so far */
if (p->compression_en && !dp_intf &&
- mdss_ver->core_major_ver >= 7)
+ intf->mdss_ver->core_major_ver >= 7)
intf_cfg2 |= INTF_CFG2_DCE_DATA_COMPRESS;
hsync_data_start_x = hsync_start_x;
@@ -580,6 +579,8 @@ struct dpu_hw_intf *dpu_hw_intf_init(struct drm_device *dev,
c->idx = cfg->id;
c->cap = cfg;
+ c->mdss_ver = mdss_rev;
+
c->ops.setup_timing_gen = dpu_hw_intf_setup_timing_engine;
c->ops.setup_prg_fetch = dpu_hw_intf_setup_prg_fetch;
c->ops.get_status = dpu_hw_intf_get_status;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
index 114be272ac0ae67fe0d4dfc0c117baa4106f77c9..f31067a9aaf1d6b96c77157135122e5e8bccb7c4 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
@@ -81,8 +81,7 @@ struct dpu_hw_intf_cmd_mode_cfg {
struct dpu_hw_intf_ops {
void (*setup_timing_gen)(struct dpu_hw_intf *intf,
const struct dpu_hw_intf_timing_params *p,
- const struct msm_format *fmt,
- const struct dpu_mdss_version *mdss_ver);
+ const struct msm_format *fmt);
void (*setup_prg_fetch)(struct dpu_hw_intf *intf,
const struct dpu_hw_intf_prog_fetch *fetch);
@@ -126,6 +125,8 @@ struct dpu_hw_intf {
enum dpu_intf idx;
const struct dpu_intf_cfg *cap;
+ const struct dpu_mdss_version *mdss_ver;
+
/* ops */
struct dpu_hw_intf_ops ops;
};
--
2.39.5
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH v4 01/30] drm/msm/dpu: stop passing mdss_ver to setup_timing_gen()
2025-05-19 16:04 ` [PATCH v4 01/30] drm/msm/dpu: stop passing mdss_ver to setup_timing_gen() Dmitry Baryshkov
@ 2025-05-19 19:26 ` neil.armstrong
0 siblings, 0 replies; 64+ messages in thread
From: neil.armstrong @ 2025-05-19 19:26 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Abhinav Kumar, Sean Paul,
Marijn Suijten, David Airlie, Simona Vetter, Vinod Koul,
Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel,
Dmitry Baryshkov
On 19/05/2025 18:04, Dmitry Baryshkov wrote:
> From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>
> As a preparation to further MDSS-revision cleanups stop passing MDSS
> revision to the setup_timing_gen() callback. Instead store a pointer to
> it inside struct dpu_hw_intf and use it diretly. It's not that the MDSS
> revision can chance between dpu_hw_intf_init() and
> dpu_encoder_phys_vid_setup_timing_engine().
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 3 +--
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 7 ++++---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 5 +++--
> 3 files changed, 8 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> index 8a618841e3ea89acfe4a42d48319a6c54a1b3495..d35d15b60260037c5c0c369cb061e7759243b6fd 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> @@ -309,8 +309,7 @@ static void dpu_encoder_phys_vid_setup_timing_engine(
>
> spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
> phys_enc->hw_intf->ops.setup_timing_gen(phys_enc->hw_intf,
> - &timing_params, fmt,
> - phys_enc->dpu_kms->catalog->mdss_ver);
> + &timing_params, fmt);
> phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg);
>
> /* setup which pp blk will connect to this intf */
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> index fb1d25baa518057e74fec3406faffd48969d492b..1d56c21ac79095ab515aeb485346e1eb5793c260 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> @@ -98,8 +98,7 @@
>
> static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *intf,
> const struct dpu_hw_intf_timing_params *p,
> - const struct msm_format *fmt,
> - const struct dpu_mdss_version *mdss_ver)
> + const struct msm_format *fmt)
> {
> struct dpu_hw_blk_reg_map *c = &intf->hw;
> u32 hsync_period, vsync_period;
> @@ -180,7 +179,7 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *intf,
>
> /* TODO: handle DSC+DP case, we only handle DSC+DSI case so far */
> if (p->compression_en && !dp_intf &&
> - mdss_ver->core_major_ver >= 7)
> + intf->mdss_ver->core_major_ver >= 7)
> intf_cfg2 |= INTF_CFG2_DCE_DATA_COMPRESS;
>
> hsync_data_start_x = hsync_start_x;
> @@ -580,6 +579,8 @@ struct dpu_hw_intf *dpu_hw_intf_init(struct drm_device *dev,
> c->idx = cfg->id;
> c->cap = cfg;
>
> + c->mdss_ver = mdss_rev;
> +
> c->ops.setup_timing_gen = dpu_hw_intf_setup_timing_engine;
> c->ops.setup_prg_fetch = dpu_hw_intf_setup_prg_fetch;
> c->ops.get_status = dpu_hw_intf_get_status;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
> index 114be272ac0ae67fe0d4dfc0c117baa4106f77c9..f31067a9aaf1d6b96c77157135122e5e8bccb7c4 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
> @@ -81,8 +81,7 @@ struct dpu_hw_intf_cmd_mode_cfg {
> struct dpu_hw_intf_ops {
> void (*setup_timing_gen)(struct dpu_hw_intf *intf,
> const struct dpu_hw_intf_timing_params *p,
> - const struct msm_format *fmt,
> - const struct dpu_mdss_version *mdss_ver);
> + const struct msm_format *fmt);
>
> void (*setup_prg_fetch)(struct dpu_hw_intf *intf,
> const struct dpu_hw_intf_prog_fetch *fetch);
> @@ -126,6 +125,8 @@ struct dpu_hw_intf {
> enum dpu_intf idx;
> const struct dpu_intf_cfg *cap;
>
> + const struct dpu_mdss_version *mdss_ver;
> +
> /* ops */
> struct dpu_hw_intf_ops ops;
> };
>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH v4 02/30] drm/msm/dpu: drop INTF_SC7280_MASK
2025-05-19 16:04 [PATCH v4 00/30] drm/msm/dpu: rework HW block feature handling Dmitry Baryshkov
2025-05-19 16:04 ` [PATCH v4 01/30] drm/msm/dpu: stop passing mdss_ver to setup_timing_gen() Dmitry Baryshkov
@ 2025-05-19 16:04 ` Dmitry Baryshkov
2025-05-19 16:04 ` [PATCH v4 03/30] drm/msm/dpu: inline _setup_ctl_ops() Dmitry Baryshkov
` (27 subsequent siblings)
29 siblings, 0 replies; 64+ messages in thread
From: Dmitry Baryshkov @ 2025-05-19 16:04 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Sean Paul, Marijn Suijten, David Airlie,
Simona Vetter, Vinod Koul, Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel,
Dmitry Baryshkov
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
The INTF_SC7280_MASK is equal to the INTF_SC7180_MASK. Stop defining a
separate symbol and use the INTF_SC7180_MASK instead.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 8 ++++----
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 8 ++++----
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 6 +++---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 18 +++++++++---------
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 8 ++++----
.../gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 16 ++++++++--------
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 8 ++++----
.../gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h | 8 ++++----
.../gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 18 +++++++++---------
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 --
10 files changed, 49 insertions(+), 51 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
index ffc4d4257ae52553bada7a7a270ab02f566359f5..61420821a5f2dd5e56b8336c898290a2552c77fa 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
@@ -374,7 +374,7 @@ static const struct dpu_intf_cfg sm8650_intf[] = {
{
.name = "intf_0", .id = INTF_0,
.base = 0x34000, .len = 0x280,
- .features = INTF_SC7280_MASK,
+ .features = INTF_SC7180_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_0,
.prog_fetch_lines_worst_case = 24,
@@ -383,7 +383,7 @@ static const struct dpu_intf_cfg sm8650_intf[] = {
}, {
.name = "intf_1", .id = INTF_1,
.base = 0x35000, .len = 0x300,
- .features = INTF_SC7280_MASK,
+ .features = INTF_SC7180_MASK,
.type = INTF_DSI,
.controller_id = MSM_DSI_CONTROLLER_0,
.prog_fetch_lines_worst_case = 24,
@@ -393,7 +393,7 @@ static const struct dpu_intf_cfg sm8650_intf[] = {
}, {
.name = "intf_2", .id = INTF_2,
.base = 0x36000, .len = 0x300,
- .features = INTF_SC7280_MASK,
+ .features = INTF_SC7180_MASK,
.type = INTF_DSI,
.controller_id = MSM_DSI_CONTROLLER_1,
.prog_fetch_lines_worst_case = 24,
@@ -403,7 +403,7 @@ static const struct dpu_intf_cfg sm8650_intf[] = {
}, {
.name = "intf_3", .id = INTF_3,
.base = 0x37000, .len = 0x280,
- .features = INTF_SC7280_MASK,
+ .features = INTF_SC7180_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_1,
.prog_fetch_lines_worst_case = 24,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
index 90e86063a37277c0e15c6ba5b41c29fa769e25d8..e887e78059a81569fac8a4246ad63856dc48cfcb 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
@@ -318,7 +318,7 @@ static const struct dpu_intf_cfg sm8350_intf[] = {
{
.name = "intf_0", .id = INTF_0,
.base = 0x34000, .len = 0x280,
- .features = INTF_SC7280_MASK,
+ .features = INTF_SC7180_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_0,
.prog_fetch_lines_worst_case = 24,
@@ -327,7 +327,7 @@ static const struct dpu_intf_cfg sm8350_intf[] = {
}, {
.name = "intf_1", .id = INTF_1,
.base = 0x35000, .len = 0x2c4,
- .features = INTF_SC7280_MASK,
+ .features = INTF_SC7180_MASK,
.type = INTF_DSI,
.controller_id = MSM_DSI_CONTROLLER_0,
.prog_fetch_lines_worst_case = 24,
@@ -337,7 +337,7 @@ static const struct dpu_intf_cfg sm8350_intf[] = {
}, {
.name = "intf_2", .id = INTF_2,
.base = 0x36000, .len = 0x2c4,
- .features = INTF_SC7280_MASK,
+ .features = INTF_SC7180_MASK,
.type = INTF_DSI,
.controller_id = MSM_DSI_CONTROLLER_1,
.prog_fetch_lines_worst_case = 24,
@@ -347,7 +347,7 @@ static const struct dpu_intf_cfg sm8350_intf[] = {
}, {
.name = "intf_3", .id = INTF_3,
.base = 0x37000, .len = 0x280,
- .features = INTF_SC7280_MASK,
+ .features = INTF_SC7180_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_1,
.prog_fetch_lines_worst_case = 24,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
index e9625c48c5677ef221b8fc80e7f9df8957b847e2..1edec0644b078ac1fff129354d4d02eec015a331 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
@@ -183,7 +183,7 @@ static const struct dpu_intf_cfg sc7280_intf[] = {
{
.name = "intf_0", .id = INTF_0,
.base = 0x34000, .len = 0x280,
- .features = INTF_SC7280_MASK,
+ .features = INTF_SC7180_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_0,
.prog_fetch_lines_worst_case = 24,
@@ -192,7 +192,7 @@ static const struct dpu_intf_cfg sc7280_intf[] = {
}, {
.name = "intf_1", .id = INTF_1,
.base = 0x35000, .len = 0x2c4,
- .features = INTF_SC7280_MASK,
+ .features = INTF_SC7180_MASK,
.type = INTF_DSI,
.controller_id = MSM_DSI_CONTROLLER_0,
.prog_fetch_lines_worst_case = 24,
@@ -202,7 +202,7 @@ static const struct dpu_intf_cfg sc7280_intf[] = {
}, {
.name = "intf_5", .id = INTF_5,
.base = 0x39000, .len = 0x280,
- .features = INTF_SC7280_MASK,
+ .features = INTF_SC7180_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_1,
.prog_fetch_lines_worst_case = 24,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
index 139f11321fea8cf96d6315abf1a8d2f9b9663c02..9d60208745138bf29a7bdbd14ef28a2102f36f9f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
@@ -314,7 +314,7 @@ static const struct dpu_intf_cfg sc8280xp_intf[] = {
{
.name = "intf_0", .id = INTF_0,
.base = 0x34000, .len = 0x280,
- .features = INTF_SC7280_MASK,
+ .features = INTF_SC7180_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_0,
.prog_fetch_lines_worst_case = 24,
@@ -323,7 +323,7 @@ static const struct dpu_intf_cfg sc8280xp_intf[] = {
}, {
.name = "intf_1", .id = INTF_1,
.base = 0x35000, .len = 0x300,
- .features = INTF_SC7280_MASK,
+ .features = INTF_SC7180_MASK,
.type = INTF_DSI,
.controller_id = MSM_DSI_CONTROLLER_0,
.prog_fetch_lines_worst_case = 24,
@@ -333,7 +333,7 @@ static const struct dpu_intf_cfg sc8280xp_intf[] = {
}, {
.name = "intf_2", .id = INTF_2,
.base = 0x36000, .len = 0x300,
- .features = INTF_SC7280_MASK,
+ .features = INTF_SC7180_MASK,
.type = INTF_DSI,
.controller_id = MSM_DSI_CONTROLLER_1,
.prog_fetch_lines_worst_case = 24,
@@ -343,7 +343,7 @@ static const struct dpu_intf_cfg sc8280xp_intf[] = {
}, {
.name = "intf_3", .id = INTF_3,
.base = 0x37000, .len = 0x280,
- .features = INTF_SC7280_MASK,
+ .features = INTF_SC7180_MASK,
.type = INTF_NONE,
.controller_id = MSM_DP_CONTROLLER_0,
.prog_fetch_lines_worst_case = 24,
@@ -352,7 +352,7 @@ static const struct dpu_intf_cfg sc8280xp_intf[] = {
}, {
.name = "intf_4", .id = INTF_4,
.base = 0x38000, .len = 0x280,
- .features = INTF_SC7280_MASK,
+ .features = INTF_SC7180_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_1,
.prog_fetch_lines_worst_case = 24,
@@ -361,7 +361,7 @@ static const struct dpu_intf_cfg sc8280xp_intf[] = {
}, {
.name = "intf_5", .id = INTF_5,
.base = 0x39000, .len = 0x280,
- .features = INTF_SC7280_MASK,
+ .features = INTF_SC7180_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_3,
.prog_fetch_lines_worst_case = 24,
@@ -370,7 +370,7 @@ static const struct dpu_intf_cfg sc8280xp_intf[] = {
}, {
.name = "intf_6", .id = INTF_6,
.base = 0x3a000, .len = 0x280,
- .features = INTF_SC7280_MASK,
+ .features = INTF_SC7180_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_2,
.prog_fetch_lines_worst_case = 24,
@@ -379,7 +379,7 @@ static const struct dpu_intf_cfg sc8280xp_intf[] = {
}, {
.name = "intf_7", .id = INTF_7,
.base = 0x3b000, .len = 0x280,
- .features = INTF_SC7280_MASK,
+ .features = INTF_SC7180_MASK,
.type = INTF_NONE,
.controller_id = MSM_DP_CONTROLLER_2,
.prog_fetch_lines_worst_case = 24,
@@ -388,7 +388,7 @@ static const struct dpu_intf_cfg sc8280xp_intf[] = {
}, {
.name = "intf_8", .id = INTF_8,
.base = 0x3c000, .len = 0x280,
- .features = INTF_SC7280_MASK,
+ .features = INTF_SC7180_MASK,
.type = INTF_NONE,
.controller_id = MSM_DP_CONTROLLER_1,
.prog_fetch_lines_worst_case = 24,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
index 461294143a9004ac2d18afbd57c2dc235e676fea..631154059c31e8ce1b9e3631552ce49aa589d4cf 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
@@ -334,7 +334,7 @@ static const struct dpu_intf_cfg sm8450_intf[] = {
{
.name = "intf_0", .id = INTF_0,
.base = 0x34000, .len = 0x280,
- .features = INTF_SC7280_MASK,
+ .features = INTF_SC7180_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_0,
.prog_fetch_lines_worst_case = 24,
@@ -343,7 +343,7 @@ static const struct dpu_intf_cfg sm8450_intf[] = {
}, {
.name = "intf_1", .id = INTF_1,
.base = 0x35000, .len = 0x300,
- .features = INTF_SC7280_MASK,
+ .features = INTF_SC7180_MASK,
.type = INTF_DSI,
.controller_id = MSM_DSI_CONTROLLER_0,
.prog_fetch_lines_worst_case = 24,
@@ -353,7 +353,7 @@ static const struct dpu_intf_cfg sm8450_intf[] = {
}, {
.name = "intf_2", .id = INTF_2,
.base = 0x36000, .len = 0x300,
- .features = INTF_SC7280_MASK,
+ .features = INTF_SC7180_MASK,
.type = INTF_DSI,
.controller_id = MSM_DSI_CONTROLLER_1,
.prog_fetch_lines_worst_case = 24,
@@ -363,7 +363,7 @@ static const struct dpu_intf_cfg sm8450_intf[] = {
}, {
.name = "intf_3", .id = INTF_3,
.base = 0x37000, .len = 0x280,
- .features = INTF_SC7280_MASK,
+ .features = INTF_SC7180_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_1,
.prog_fetch_lines_worst_case = 24,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
index c248b3b55c410d8e374b8b659eeddbb657bbe854..3547fdfb28cae6cd8d1909b268b88676afad0be7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
@@ -344,7 +344,7 @@ static const struct dpu_intf_cfg sa8775p_intf[] = {
{
.name = "intf_0", .id = INTF_0,
.base = 0x34000, .len = 0x280,
- .features = INTF_SC7280_MASK,
+ .features = INTF_SC7180_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_0,
.prog_fetch_lines_worst_case = 24,
@@ -353,7 +353,7 @@ static const struct dpu_intf_cfg sa8775p_intf[] = {
}, {
.name = "intf_1", .id = INTF_1,
.base = 0x35000, .len = 0x300,
- .features = INTF_SC7280_MASK,
+ .features = INTF_SC7180_MASK,
.type = INTF_DSI,
.controller_id = MSM_DSI_CONTROLLER_0,
.prog_fetch_lines_worst_case = 24,
@@ -363,7 +363,7 @@ static const struct dpu_intf_cfg sa8775p_intf[] = {
}, {
.name = "intf_2", .id = INTF_2,
.base = 0x36000, .len = 0x300,
- .features = INTF_SC7280_MASK,
+ .features = INTF_SC7180_MASK,
.type = INTF_DSI,
.controller_id = MSM_DSI_CONTROLLER_1,
.prog_fetch_lines_worst_case = 24,
@@ -373,7 +373,7 @@ static const struct dpu_intf_cfg sa8775p_intf[] = {
}, {
.name = "intf_3", .id = INTF_3,
.base = 0x37000, .len = 0x280,
- .features = INTF_SC7280_MASK,
+ .features = INTF_SC7180_MASK,
.type = INTF_NONE,
.controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
.prog_fetch_lines_worst_case = 24,
@@ -382,7 +382,7 @@ static const struct dpu_intf_cfg sa8775p_intf[] = {
}, {
.name = "intf_4", .id = INTF_4,
.base = 0x38000, .len = 0x280,
- .features = INTF_SC7280_MASK,
+ .features = INTF_SC7180_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_1,
.prog_fetch_lines_worst_case = 24,
@@ -391,7 +391,7 @@ static const struct dpu_intf_cfg sa8775p_intf[] = {
}, {
.name = "intf_6", .id = INTF_6,
.base = 0x3A000, .len = 0x280,
- .features = INTF_SC7280_MASK,
+ .features = INTF_SC7180_MASK,
.type = INTF_NONE,
.controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
.prog_fetch_lines_worst_case = 24,
@@ -400,7 +400,7 @@ static const struct dpu_intf_cfg sa8775p_intf[] = {
}, {
.name = "intf_7", .id = INTF_7,
.base = 0x3b000, .len = 0x280,
- .features = INTF_SC7280_MASK,
+ .features = INTF_SC7180_MASK,
.type = INTF_NONE,
.controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
.prog_fetch_lines_worst_case = 24,
@@ -409,7 +409,7 @@ static const struct dpu_intf_cfg sa8775p_intf[] = {
}, {
.name = "intf_8", .id = INTF_8,
.base = 0x3c000, .len = 0x280,
- .features = INTF_SC7280_MASK,
+ .features = INTF_SC7180_MASK,
.type = INTF_NONE,
.controller_id = MSM_DP_CONTROLLER_1, /* pair with intf_4 for DP MST */
.prog_fetch_lines_worst_case = 24,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
index 59c7fdf28e890f0c4c15e869e549488003fcd087..e16e47a6f426359548434569ad632aa68f32908d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
@@ -329,7 +329,7 @@ static const struct dpu_intf_cfg sm8550_intf[] = {
{
.name = "intf_0", .id = INTF_0,
.base = 0x34000, .len = 0x280,
- .features = INTF_SC7280_MASK,
+ .features = INTF_SC7180_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_0,
.prog_fetch_lines_worst_case = 24,
@@ -338,7 +338,7 @@ static const struct dpu_intf_cfg sm8550_intf[] = {
}, {
.name = "intf_1", .id = INTF_1,
.base = 0x35000, .len = 0x300,
- .features = INTF_SC7280_MASK,
+ .features = INTF_SC7180_MASK,
.type = INTF_DSI,
.controller_id = MSM_DSI_CONTROLLER_0,
.prog_fetch_lines_worst_case = 24,
@@ -348,7 +348,7 @@ static const struct dpu_intf_cfg sm8550_intf[] = {
}, {
.name = "intf_2", .id = INTF_2,
.base = 0x36000, .len = 0x300,
- .features = INTF_SC7280_MASK,
+ .features = INTF_SC7180_MASK,
.type = INTF_DSI,
.controller_id = MSM_DSI_CONTROLLER_1,
.prog_fetch_lines_worst_case = 24,
@@ -358,7 +358,7 @@ static const struct dpu_intf_cfg sm8550_intf[] = {
}, {
.name = "intf_3", .id = INTF_3,
.base = 0x37000, .len = 0x280,
- .features = INTF_SC7280_MASK,
+ .features = INTF_SC7180_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_1,
.prog_fetch_lines_worst_case = 24,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
index 5667d055fbd1d8125c3231302daa3e05de5944c9..f85d5d7ae51d64203647a8bcec91f524c6e33528 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
@@ -329,7 +329,7 @@ static const struct dpu_intf_cfg sar2130p_intf[] = {
{
.name = "intf_0", .id = INTF_0,
.base = 0x34000, .len = 0x280,
- .features = INTF_SC7280_MASK,
+ .features = INTF_SC7180_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_0,
.prog_fetch_lines_worst_case = 24,
@@ -338,7 +338,7 @@ static const struct dpu_intf_cfg sar2130p_intf[] = {
}, {
.name = "intf_1", .id = INTF_1,
.base = 0x35000, .len = 0x300,
- .features = INTF_SC7280_MASK,
+ .features = INTF_SC7180_MASK,
.type = INTF_DSI,
.controller_id = MSM_DSI_CONTROLLER_0,
.prog_fetch_lines_worst_case = 24,
@@ -348,7 +348,7 @@ static const struct dpu_intf_cfg sar2130p_intf[] = {
}, {
.name = "intf_2", .id = INTF_2,
.base = 0x36000, .len = 0x300,
- .features = INTF_SC7280_MASK,
+ .features = INTF_SC7180_MASK,
.type = INTF_DSI,
.controller_id = MSM_DSI_CONTROLLER_1,
.prog_fetch_lines_worst_case = 24,
@@ -358,7 +358,7 @@ static const struct dpu_intf_cfg sar2130p_intf[] = {
}, {
.name = "intf_3", .id = INTF_3,
.base = 0x37000, .len = 0x280,
- .features = INTF_SC7280_MASK,
+ .features = INTF_SC7180_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_1,
.prog_fetch_lines_worst_case = 24,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
index 52cc10aec1f9f539a1ca26339704a053d5c38a82..0d6511f90975508b36b0fa00a92349a82eff4d52 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
@@ -330,7 +330,7 @@ static const struct dpu_intf_cfg x1e80100_intf[] = {
{
.name = "intf_0", .id = INTF_0,
.base = 0x34000, .len = 0x280,
- .features = INTF_SC7280_MASK,
+ .features = INTF_SC7180_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_0,
.prog_fetch_lines_worst_case = 24,
@@ -339,7 +339,7 @@ static const struct dpu_intf_cfg x1e80100_intf[] = {
}, {
.name = "intf_1", .id = INTF_1,
.base = 0x35000, .len = 0x300,
- .features = INTF_SC7280_MASK,
+ .features = INTF_SC7180_MASK,
.type = INTF_DSI,
.controller_id = MSM_DSI_CONTROLLER_0,
.prog_fetch_lines_worst_case = 24,
@@ -349,7 +349,7 @@ static const struct dpu_intf_cfg x1e80100_intf[] = {
}, {
.name = "intf_2", .id = INTF_2,
.base = 0x36000, .len = 0x300,
- .features = INTF_SC7280_MASK,
+ .features = INTF_SC7180_MASK,
.type = INTF_DSI,
.controller_id = MSM_DSI_CONTROLLER_1,
.prog_fetch_lines_worst_case = 24,
@@ -359,7 +359,7 @@ static const struct dpu_intf_cfg x1e80100_intf[] = {
}, {
.name = "intf_3", .id = INTF_3,
.base = 0x37000, .len = 0x280,
- .features = INTF_SC7280_MASK,
+ .features = INTF_SC7180_MASK,
.type = INTF_NONE,
.controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
.prog_fetch_lines_worst_case = 24,
@@ -368,7 +368,7 @@ static const struct dpu_intf_cfg x1e80100_intf[] = {
}, {
.name = "intf_4", .id = INTF_4,
.base = 0x38000, .len = 0x280,
- .features = INTF_SC7280_MASK,
+ .features = INTF_SC7180_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_1,
.prog_fetch_lines_worst_case = 24,
@@ -377,7 +377,7 @@ static const struct dpu_intf_cfg x1e80100_intf[] = {
}, {
.name = "intf_5", .id = INTF_5,
.base = 0x39000, .len = 0x280,
- .features = INTF_SC7280_MASK,
+ .features = INTF_SC7180_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_3,
.prog_fetch_lines_worst_case = 24,
@@ -386,7 +386,7 @@ static const struct dpu_intf_cfg x1e80100_intf[] = {
}, {
.name = "intf_6", .id = INTF_6,
.base = 0x3A000, .len = 0x280,
- .features = INTF_SC7280_MASK,
+ .features = INTF_SC7180_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_2,
.prog_fetch_lines_worst_case = 24,
@@ -395,7 +395,7 @@ static const struct dpu_intf_cfg x1e80100_intf[] = {
}, {
.name = "intf_7", .id = INTF_7,
.base = 0x3b000, .len = 0x280,
- .features = INTF_SC7280_MASK,
+ .features = INTF_SC7180_MASK,
.type = INTF_NONE,
.controller_id = MSM_DP_CONTROLLER_2, /* pair with intf_6 for DP MST */
.prog_fetch_lines_worst_case = 24,
@@ -404,7 +404,7 @@ static const struct dpu_intf_cfg x1e80100_intf[] = {
}, {
.name = "intf_8", .id = INTF_8,
.base = 0x3c000, .len = 0x280,
- .features = INTF_SC7280_MASK,
+ .features = INTF_SC7180_MASK,
.type = INTF_NONE,
.controller_id = MSM_DP_CONTROLLER_1, /* pair with intf_4 for DP MST */
.prog_fetch_lines_worst_case = 24,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index c878fe196aeb6c6b19fc3173fb8615f184ccf2d1..d383368c743b202d7256f6759deecaf9d756bb02 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -120,8 +120,6 @@
BIT(DPU_INTF_STATUS_SUPPORTED) | \
BIT(DPU_DATA_HCTL_EN))
-#define INTF_SC7280_MASK (INTF_SC7180_MASK)
-
#define WB_SDM845_MASK (BIT(DPU_WB_LINE_MODE) | \
BIT(DPU_WB_UBWC) | \
BIT(DPU_WB_YUV_CONFIG) | \
--
2.39.5
^ permalink raw reply related [flat|nested] 64+ messages in thread* [PATCH v4 03/30] drm/msm/dpu: inline _setup_ctl_ops()
2025-05-19 16:04 [PATCH v4 00/30] drm/msm/dpu: rework HW block feature handling Dmitry Baryshkov
2025-05-19 16:04 ` [PATCH v4 01/30] drm/msm/dpu: stop passing mdss_ver to setup_timing_gen() Dmitry Baryshkov
2025-05-19 16:04 ` [PATCH v4 02/30] drm/msm/dpu: drop INTF_SC7280_MASK Dmitry Baryshkov
@ 2025-05-19 16:04 ` Dmitry Baryshkov
2025-05-19 19:26 ` neil.armstrong
2025-05-19 16:04 ` [PATCH v4 04/30] drm/msm/dpu: inline _setup_dsc_ops() Dmitry Baryshkov
` (26 subsequent siblings)
29 siblings, 1 reply; 64+ messages in thread
From: Dmitry Baryshkov @ 2025-05-19 16:04 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Sean Paul, Marijn Suijten, David Airlie,
Simona Vetter, Vinod Koul, Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel,
Dmitry Baryshkov
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Inline the _setup_ctl_ops() function, it makes it easier to handle
different conditions involving CTL configuration.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 98 ++++++++++++++----------------
1 file changed, 47 insertions(+), 51 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index 573e42b06ad068445b947c59955281ba6e238dad..d58a0f1e8edb524ff3f21ff8c96688dd2ae49541 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -737,56 +737,6 @@ static void dpu_hw_ctl_set_active_fetch_pipes(struct dpu_hw_ctl *ctx,
DPU_REG_WRITE(&ctx->hw, CTL_FETCH_PIPE_ACTIVE, val);
}
-static void _setup_ctl_ops(struct dpu_hw_ctl_ops *ops,
- unsigned long cap)
-{
- if (cap & BIT(DPU_CTL_ACTIVE_CFG)) {
- ops->trigger_flush = dpu_hw_ctl_trigger_flush_v1;
- ops->setup_intf_cfg = dpu_hw_ctl_intf_cfg_v1;
- ops->reset_intf_cfg = dpu_hw_ctl_reset_intf_cfg_v1;
- ops->update_pending_flush_intf =
- dpu_hw_ctl_update_pending_flush_intf_v1;
-
- ops->update_pending_flush_periph =
- dpu_hw_ctl_update_pending_flush_periph_v1;
-
- ops->update_pending_flush_merge_3d =
- dpu_hw_ctl_update_pending_flush_merge_3d_v1;
- ops->update_pending_flush_wb = dpu_hw_ctl_update_pending_flush_wb_v1;
- ops->update_pending_flush_cwb = dpu_hw_ctl_update_pending_flush_cwb_v1;
- ops->update_pending_flush_dsc =
- dpu_hw_ctl_update_pending_flush_dsc_v1;
- ops->update_pending_flush_cdm = dpu_hw_ctl_update_pending_flush_cdm_v1;
- } else {
- ops->trigger_flush = dpu_hw_ctl_trigger_flush;
- ops->setup_intf_cfg = dpu_hw_ctl_intf_cfg;
- ops->update_pending_flush_intf =
- dpu_hw_ctl_update_pending_flush_intf;
- ops->update_pending_flush_wb = dpu_hw_ctl_update_pending_flush_wb;
- ops->update_pending_flush_cdm = dpu_hw_ctl_update_pending_flush_cdm;
- }
- ops->clear_pending_flush = dpu_hw_ctl_clear_pending_flush;
- ops->update_pending_flush = dpu_hw_ctl_update_pending_flush;
- ops->get_pending_flush = dpu_hw_ctl_get_pending_flush;
- ops->get_flush_register = dpu_hw_ctl_get_flush_register;
- ops->trigger_start = dpu_hw_ctl_trigger_start;
- ops->is_started = dpu_hw_ctl_is_started;
- ops->trigger_pending = dpu_hw_ctl_trigger_pending;
- ops->reset = dpu_hw_ctl_reset_control;
- ops->wait_reset_status = dpu_hw_ctl_wait_reset_status;
- ops->clear_all_blendstages = dpu_hw_ctl_clear_all_blendstages;
- ops->setup_blendstage = dpu_hw_ctl_setup_blendstage;
- ops->update_pending_flush_sspp = dpu_hw_ctl_update_pending_flush_sspp;
- ops->update_pending_flush_mixer = dpu_hw_ctl_update_pending_flush_mixer;
- if (cap & BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH))
- ops->update_pending_flush_dspp = dpu_hw_ctl_update_pending_flush_dspp_sub_blocks;
- else
- ops->update_pending_flush_dspp = dpu_hw_ctl_update_pending_flush_dspp;
-
- if (cap & BIT(DPU_CTL_FETCH_ACTIVE))
- ops->set_active_fetch_pipes = dpu_hw_ctl_set_active_fetch_pipes;
-};
-
/**
* dpu_hw_ctl_init() - Initializes the ctl_path hw driver object.
* Should be called before accessing any ctl_path register.
@@ -812,7 +762,53 @@ struct dpu_hw_ctl *dpu_hw_ctl_init(struct drm_device *dev,
c->hw.log_mask = DPU_DBG_MASK_CTL;
c->caps = cfg;
- _setup_ctl_ops(&c->ops, c->caps->features);
+
+ if (c->caps->features & BIT(DPU_CTL_ACTIVE_CFG)) {
+ c->ops.trigger_flush = dpu_hw_ctl_trigger_flush_v1;
+ c->ops.setup_intf_cfg = dpu_hw_ctl_intf_cfg_v1;
+ c->ops.reset_intf_cfg = dpu_hw_ctl_reset_intf_cfg_v1;
+ c->ops.update_pending_flush_intf =
+ dpu_hw_ctl_update_pending_flush_intf_v1;
+
+ c->ops.update_pending_flush_periph =
+ dpu_hw_ctl_update_pending_flush_periph_v1;
+
+ c->ops.update_pending_flush_merge_3d =
+ dpu_hw_ctl_update_pending_flush_merge_3d_v1;
+ c->ops.update_pending_flush_wb = dpu_hw_ctl_update_pending_flush_wb_v1;
+ c->ops.update_pending_flush_cwb = dpu_hw_ctl_update_pending_flush_cwb_v1;
+ c->ops.update_pending_flush_dsc =
+ dpu_hw_ctl_update_pending_flush_dsc_v1;
+ c->ops.update_pending_flush_cdm = dpu_hw_ctl_update_pending_flush_cdm_v1;
+ } else {
+ c->ops.trigger_flush = dpu_hw_ctl_trigger_flush;
+ c->ops.setup_intf_cfg = dpu_hw_ctl_intf_cfg;
+ c->ops.update_pending_flush_intf =
+ dpu_hw_ctl_update_pending_flush_intf;
+ c->ops.update_pending_flush_wb = dpu_hw_ctl_update_pending_flush_wb;
+ c->ops.update_pending_flush_cdm = dpu_hw_ctl_update_pending_flush_cdm;
+ }
+ c->ops.clear_pending_flush = dpu_hw_ctl_clear_pending_flush;
+ c->ops.update_pending_flush = dpu_hw_ctl_update_pending_flush;
+ c->ops.get_pending_flush = dpu_hw_ctl_get_pending_flush;
+ c->ops.get_flush_register = dpu_hw_ctl_get_flush_register;
+ c->ops.trigger_start = dpu_hw_ctl_trigger_start;
+ c->ops.is_started = dpu_hw_ctl_is_started;
+ c->ops.trigger_pending = dpu_hw_ctl_trigger_pending;
+ c->ops.reset = dpu_hw_ctl_reset_control;
+ c->ops.wait_reset_status = dpu_hw_ctl_wait_reset_status;
+ c->ops.clear_all_blendstages = dpu_hw_ctl_clear_all_blendstages;
+ c->ops.setup_blendstage = dpu_hw_ctl_setup_blendstage;
+ c->ops.update_pending_flush_sspp = dpu_hw_ctl_update_pending_flush_sspp;
+ c->ops.update_pending_flush_mixer = dpu_hw_ctl_update_pending_flush_mixer;
+ if (c->caps->features & BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH))
+ c->ops.update_pending_flush_dspp = dpu_hw_ctl_update_pending_flush_dspp_sub_blocks;
+ else
+ c->ops.update_pending_flush_dspp = dpu_hw_ctl_update_pending_flush_dspp;
+
+ if (c->caps->features & BIT(DPU_CTL_FETCH_ACTIVE))
+ c->ops.set_active_fetch_pipes = dpu_hw_ctl_set_active_fetch_pipes;
+
c->idx = cfg->id;
c->mixer_count = mixer_count;
c->mixer_hw_caps = mixer;
--
2.39.5
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH v4 03/30] drm/msm/dpu: inline _setup_ctl_ops()
2025-05-19 16:04 ` [PATCH v4 03/30] drm/msm/dpu: inline _setup_ctl_ops() Dmitry Baryshkov
@ 2025-05-19 19:26 ` neil.armstrong
0 siblings, 0 replies; 64+ messages in thread
From: neil.armstrong @ 2025-05-19 19:26 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Abhinav Kumar, Sean Paul,
Marijn Suijten, David Airlie, Simona Vetter, Vinod Koul,
Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel,
Dmitry Baryshkov
On 19/05/2025 18:04, Dmitry Baryshkov wrote:
> From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>
> Inline the _setup_ctl_ops() function, it makes it easier to handle
> different conditions involving CTL configuration.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 98 ++++++++++++++----------------
> 1 file changed, 47 insertions(+), 51 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> index 573e42b06ad068445b947c59955281ba6e238dad..d58a0f1e8edb524ff3f21ff8c96688dd2ae49541 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> @@ -737,56 +737,6 @@ static void dpu_hw_ctl_set_active_fetch_pipes(struct dpu_hw_ctl *ctx,
> DPU_REG_WRITE(&ctx->hw, CTL_FETCH_PIPE_ACTIVE, val);
> }
>
> -static void _setup_ctl_ops(struct dpu_hw_ctl_ops *ops,
> - unsigned long cap)
> -{
> - if (cap & BIT(DPU_CTL_ACTIVE_CFG)) {
> - ops->trigger_flush = dpu_hw_ctl_trigger_flush_v1;
> - ops->setup_intf_cfg = dpu_hw_ctl_intf_cfg_v1;
> - ops->reset_intf_cfg = dpu_hw_ctl_reset_intf_cfg_v1;
> - ops->update_pending_flush_intf =
> - dpu_hw_ctl_update_pending_flush_intf_v1;
> -
> - ops->update_pending_flush_periph =
> - dpu_hw_ctl_update_pending_flush_periph_v1;
> -
> - ops->update_pending_flush_merge_3d =
> - dpu_hw_ctl_update_pending_flush_merge_3d_v1;
> - ops->update_pending_flush_wb = dpu_hw_ctl_update_pending_flush_wb_v1;
> - ops->update_pending_flush_cwb = dpu_hw_ctl_update_pending_flush_cwb_v1;
> - ops->update_pending_flush_dsc =
> - dpu_hw_ctl_update_pending_flush_dsc_v1;
> - ops->update_pending_flush_cdm = dpu_hw_ctl_update_pending_flush_cdm_v1;
> - } else {
> - ops->trigger_flush = dpu_hw_ctl_trigger_flush;
> - ops->setup_intf_cfg = dpu_hw_ctl_intf_cfg;
> - ops->update_pending_flush_intf =
> - dpu_hw_ctl_update_pending_flush_intf;
> - ops->update_pending_flush_wb = dpu_hw_ctl_update_pending_flush_wb;
> - ops->update_pending_flush_cdm = dpu_hw_ctl_update_pending_flush_cdm;
> - }
> - ops->clear_pending_flush = dpu_hw_ctl_clear_pending_flush;
> - ops->update_pending_flush = dpu_hw_ctl_update_pending_flush;
> - ops->get_pending_flush = dpu_hw_ctl_get_pending_flush;
> - ops->get_flush_register = dpu_hw_ctl_get_flush_register;
> - ops->trigger_start = dpu_hw_ctl_trigger_start;
> - ops->is_started = dpu_hw_ctl_is_started;
> - ops->trigger_pending = dpu_hw_ctl_trigger_pending;
> - ops->reset = dpu_hw_ctl_reset_control;
> - ops->wait_reset_status = dpu_hw_ctl_wait_reset_status;
> - ops->clear_all_blendstages = dpu_hw_ctl_clear_all_blendstages;
> - ops->setup_blendstage = dpu_hw_ctl_setup_blendstage;
> - ops->update_pending_flush_sspp = dpu_hw_ctl_update_pending_flush_sspp;
> - ops->update_pending_flush_mixer = dpu_hw_ctl_update_pending_flush_mixer;
> - if (cap & BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH))
> - ops->update_pending_flush_dspp = dpu_hw_ctl_update_pending_flush_dspp_sub_blocks;
> - else
> - ops->update_pending_flush_dspp = dpu_hw_ctl_update_pending_flush_dspp;
> -
> - if (cap & BIT(DPU_CTL_FETCH_ACTIVE))
> - ops->set_active_fetch_pipes = dpu_hw_ctl_set_active_fetch_pipes;
> -};
> -
> /**
> * dpu_hw_ctl_init() - Initializes the ctl_path hw driver object.
> * Should be called before accessing any ctl_path register.
> @@ -812,7 +762,53 @@ struct dpu_hw_ctl *dpu_hw_ctl_init(struct drm_device *dev,
> c->hw.log_mask = DPU_DBG_MASK_CTL;
>
> c->caps = cfg;
> - _setup_ctl_ops(&c->ops, c->caps->features);
> +
> + if (c->caps->features & BIT(DPU_CTL_ACTIVE_CFG)) {
> + c->ops.trigger_flush = dpu_hw_ctl_trigger_flush_v1;
> + c->ops.setup_intf_cfg = dpu_hw_ctl_intf_cfg_v1;
> + c->ops.reset_intf_cfg = dpu_hw_ctl_reset_intf_cfg_v1;
> + c->ops.update_pending_flush_intf =
> + dpu_hw_ctl_update_pending_flush_intf_v1;
> +
> + c->ops.update_pending_flush_periph =
> + dpu_hw_ctl_update_pending_flush_periph_v1;
> +
> + c->ops.update_pending_flush_merge_3d =
> + dpu_hw_ctl_update_pending_flush_merge_3d_v1;
> + c->ops.update_pending_flush_wb = dpu_hw_ctl_update_pending_flush_wb_v1;
> + c->ops.update_pending_flush_cwb = dpu_hw_ctl_update_pending_flush_cwb_v1;
> + c->ops.update_pending_flush_dsc =
> + dpu_hw_ctl_update_pending_flush_dsc_v1;
> + c->ops.update_pending_flush_cdm = dpu_hw_ctl_update_pending_flush_cdm_v1;
> + } else {
> + c->ops.trigger_flush = dpu_hw_ctl_trigger_flush;
> + c->ops.setup_intf_cfg = dpu_hw_ctl_intf_cfg;
> + c->ops.update_pending_flush_intf =
> + dpu_hw_ctl_update_pending_flush_intf;
> + c->ops.update_pending_flush_wb = dpu_hw_ctl_update_pending_flush_wb;
> + c->ops.update_pending_flush_cdm = dpu_hw_ctl_update_pending_flush_cdm;
> + }
> + c->ops.clear_pending_flush = dpu_hw_ctl_clear_pending_flush;
> + c->ops.update_pending_flush = dpu_hw_ctl_update_pending_flush;
> + c->ops.get_pending_flush = dpu_hw_ctl_get_pending_flush;
> + c->ops.get_flush_register = dpu_hw_ctl_get_flush_register;
> + c->ops.trigger_start = dpu_hw_ctl_trigger_start;
> + c->ops.is_started = dpu_hw_ctl_is_started;
> + c->ops.trigger_pending = dpu_hw_ctl_trigger_pending;
> + c->ops.reset = dpu_hw_ctl_reset_control;
> + c->ops.wait_reset_status = dpu_hw_ctl_wait_reset_status;
> + c->ops.clear_all_blendstages = dpu_hw_ctl_clear_all_blendstages;
> + c->ops.setup_blendstage = dpu_hw_ctl_setup_blendstage;
> + c->ops.update_pending_flush_sspp = dpu_hw_ctl_update_pending_flush_sspp;
> + c->ops.update_pending_flush_mixer = dpu_hw_ctl_update_pending_flush_mixer;
> + if (c->caps->features & BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH))
> + c->ops.update_pending_flush_dspp = dpu_hw_ctl_update_pending_flush_dspp_sub_blocks;
> + else
> + c->ops.update_pending_flush_dspp = dpu_hw_ctl_update_pending_flush_dspp;
> +
> + if (c->caps->features & BIT(DPU_CTL_FETCH_ACTIVE))
> + c->ops.set_active_fetch_pipes = dpu_hw_ctl_set_active_fetch_pipes;
> +
> c->idx = cfg->id;
> c->mixer_count = mixer_count;
> c->mixer_hw_caps = mixer;
>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH v4 04/30] drm/msm/dpu: inline _setup_dsc_ops()
2025-05-19 16:04 [PATCH v4 00/30] drm/msm/dpu: rework HW block feature handling Dmitry Baryshkov
` (2 preceding siblings ...)
2025-05-19 16:04 ` [PATCH v4 03/30] drm/msm/dpu: inline _setup_ctl_ops() Dmitry Baryshkov
@ 2025-05-19 16:04 ` Dmitry Baryshkov
2025-05-19 19:27 ` neil.armstrong
2025-05-19 16:04 ` [PATCH v4 05/30] drm/msm/dpu: inline _setup_dspp_ops() Dmitry Baryshkov
` (25 subsequent siblings)
29 siblings, 1 reply; 64+ messages in thread
From: Dmitry Baryshkov @ 2025-05-19 16:04 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Sean Paul, Marijn Suijten, David Airlie,
Simona Vetter, Vinod Koul, Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel,
Dmitry Baryshkov
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Inline the _setup_dsc_ops() function, it makes it easier to handle
different conditions involving DSC configuration.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 17 ++++++-----------
1 file changed, 6 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
index cec6d4e8baec4d00282465cfd2885d365f835976..c7db917afd27e3daf1e8aad2ad671246bf6c8fbf 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
@@ -181,16 +181,6 @@ static void dpu_hw_dsc_bind_pingpong_blk(
DPU_REG_WRITE(c, dsc_ctl_offset, mux_cfg);
}
-static void _setup_dsc_ops(struct dpu_hw_dsc_ops *ops,
- unsigned long cap)
-{
- ops->dsc_disable = dpu_hw_dsc_disable;
- ops->dsc_config = dpu_hw_dsc_config;
- ops->dsc_config_thresh = dpu_hw_dsc_config_thresh;
- if (cap & BIT(DPU_DSC_OUTPUT_CTRL))
- ops->dsc_bind_pingpong_blk = dpu_hw_dsc_bind_pingpong_blk;
-};
-
/**
* dpu_hw_dsc_init() - Initializes the DSC hw driver object.
* @dev: Corresponding device for devres management
@@ -213,7 +203,12 @@ struct dpu_hw_dsc *dpu_hw_dsc_init(struct drm_device *dev,
c->idx = cfg->id;
c->caps = cfg;
- _setup_dsc_ops(&c->ops, c->caps->features);
+
+ c->ops.dsc_disable = dpu_hw_dsc_disable;
+ c->ops.dsc_config = dpu_hw_dsc_config;
+ c->ops.dsc_config_thresh = dpu_hw_dsc_config_thresh;
+ if (c->caps->features & BIT(DPU_DSC_OUTPUT_CTRL))
+ c->ops.dsc_bind_pingpong_blk = dpu_hw_dsc_bind_pingpong_blk;
return c;
}
--
2.39.5
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH v4 04/30] drm/msm/dpu: inline _setup_dsc_ops()
2025-05-19 16:04 ` [PATCH v4 04/30] drm/msm/dpu: inline _setup_dsc_ops() Dmitry Baryshkov
@ 2025-05-19 19:27 ` neil.armstrong
0 siblings, 0 replies; 64+ messages in thread
From: neil.armstrong @ 2025-05-19 19:27 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Abhinav Kumar, Sean Paul,
Marijn Suijten, David Airlie, Simona Vetter, Vinod Koul,
Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel,
Dmitry Baryshkov
On 19/05/2025 18:04, Dmitry Baryshkov wrote:
> From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>
> Inline the _setup_dsc_ops() function, it makes it easier to handle
> different conditions involving DSC configuration.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 17 ++++++-----------
> 1 file changed, 6 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
> index cec6d4e8baec4d00282465cfd2885d365f835976..c7db917afd27e3daf1e8aad2ad671246bf6c8fbf 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
> @@ -181,16 +181,6 @@ static void dpu_hw_dsc_bind_pingpong_blk(
> DPU_REG_WRITE(c, dsc_ctl_offset, mux_cfg);
> }
>
> -static void _setup_dsc_ops(struct dpu_hw_dsc_ops *ops,
> - unsigned long cap)
> -{
> - ops->dsc_disable = dpu_hw_dsc_disable;
> - ops->dsc_config = dpu_hw_dsc_config;
> - ops->dsc_config_thresh = dpu_hw_dsc_config_thresh;
> - if (cap & BIT(DPU_DSC_OUTPUT_CTRL))
> - ops->dsc_bind_pingpong_blk = dpu_hw_dsc_bind_pingpong_blk;
> -};
> -
> /**
> * dpu_hw_dsc_init() - Initializes the DSC hw driver object.
> * @dev: Corresponding device for devres management
> @@ -213,7 +203,12 @@ struct dpu_hw_dsc *dpu_hw_dsc_init(struct drm_device *dev,
>
> c->idx = cfg->id;
> c->caps = cfg;
> - _setup_dsc_ops(&c->ops, c->caps->features);
> +
> + c->ops.dsc_disable = dpu_hw_dsc_disable;
> + c->ops.dsc_config = dpu_hw_dsc_config;
> + c->ops.dsc_config_thresh = dpu_hw_dsc_config_thresh;
> + if (c->caps->features & BIT(DPU_DSC_OUTPUT_CTRL))
> + c->ops.dsc_bind_pingpong_blk = dpu_hw_dsc_bind_pingpong_blk;
>
> return c;
> }
>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH v4 05/30] drm/msm/dpu: inline _setup_dspp_ops()
2025-05-19 16:04 [PATCH v4 00/30] drm/msm/dpu: rework HW block feature handling Dmitry Baryshkov
` (3 preceding siblings ...)
2025-05-19 16:04 ` [PATCH v4 04/30] drm/msm/dpu: inline _setup_dsc_ops() Dmitry Baryshkov
@ 2025-05-19 16:04 ` Dmitry Baryshkov
2025-05-20 8:06 ` neil.armstrong
2025-05-19 16:04 ` [PATCH v4 06/30] drm/msm/dpu: inline _setup_mixer_ops() Dmitry Baryshkov
` (24 subsequent siblings)
29 siblings, 1 reply; 64+ messages in thread
From: Dmitry Baryshkov @ 2025-05-19 16:04 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Sean Paul, Marijn Suijten, David Airlie,
Simona Vetter, Vinod Koul, Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel,
Dmitry Baryshkov
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Inline the _setup_dspp_ops() function, it makes it easier to handle
different conditions involving DSPP configuration.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c | 10 ++--------
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
index 829ca272873e45b122c04bea7da22dc569732e10..0f5a74398e66642fba48c112db41ffc75ae2a79f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
@@ -63,13 +63,6 @@ static void dpu_setup_dspp_pcc(struct dpu_hw_dspp *ctx,
DPU_REG_WRITE(&ctx->hw, base, PCC_EN);
}
-static void _setup_dspp_ops(struct dpu_hw_dspp *c,
- unsigned long features)
-{
- if (test_bit(DPU_DSPP_PCC, &features))
- c->ops.setup_pcc = dpu_setup_dspp_pcc;
-}
-
/**
* dpu_hw_dspp_init() - Initializes the DSPP hw driver object.
* should be called once before accessing every DSPP.
@@ -97,7 +90,8 @@ struct dpu_hw_dspp *dpu_hw_dspp_init(struct drm_device *dev,
/* Assign ops */
c->idx = cfg->id;
c->cap = cfg;
- _setup_dspp_ops(c, c->cap->features);
+ if (test_bit(DPU_DSPP_PCC, &c->cap->features))
+ c->ops.setup_pcc = dpu_setup_dspp_pcc;
return c;
}
--
2.39.5
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH v4 05/30] drm/msm/dpu: inline _setup_dspp_ops()
2025-05-19 16:04 ` [PATCH v4 05/30] drm/msm/dpu: inline _setup_dspp_ops() Dmitry Baryshkov
@ 2025-05-20 8:06 ` neil.armstrong
0 siblings, 0 replies; 64+ messages in thread
From: neil.armstrong @ 2025-05-20 8:06 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Abhinav Kumar, Sean Paul,
Marijn Suijten, David Airlie, Simona Vetter, Vinod Koul,
Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel,
Dmitry Baryshkov
On 19/05/2025 18:04, Dmitry Baryshkov wrote:
> From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>
> Inline the _setup_dspp_ops() function, it makes it easier to handle
> different conditions involving DSPP configuration.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c | 10 ++--------
> 1 file changed, 2 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
> index 829ca272873e45b122c04bea7da22dc569732e10..0f5a74398e66642fba48c112db41ffc75ae2a79f 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
> @@ -63,13 +63,6 @@ static void dpu_setup_dspp_pcc(struct dpu_hw_dspp *ctx,
> DPU_REG_WRITE(&ctx->hw, base, PCC_EN);
> }
>
> -static void _setup_dspp_ops(struct dpu_hw_dspp *c,
> - unsigned long features)
> -{
> - if (test_bit(DPU_DSPP_PCC, &features))
> - c->ops.setup_pcc = dpu_setup_dspp_pcc;
> -}
> -
> /**
> * dpu_hw_dspp_init() - Initializes the DSPP hw driver object.
> * should be called once before accessing every DSPP.
> @@ -97,7 +90,8 @@ struct dpu_hw_dspp *dpu_hw_dspp_init(struct drm_device *dev,
> /* Assign ops */
> c->idx = cfg->id;
> c->cap = cfg;
> - _setup_dspp_ops(c, c->cap->features);
> + if (test_bit(DPU_DSPP_PCC, &c->cap->features))
> + c->ops.setup_pcc = dpu_setup_dspp_pcc;
>
> return c;
> }
>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH v4 06/30] drm/msm/dpu: inline _setup_mixer_ops()
2025-05-19 16:04 [PATCH v4 00/30] drm/msm/dpu: rework HW block feature handling Dmitry Baryshkov
` (4 preceding siblings ...)
2025-05-19 16:04 ` [PATCH v4 05/30] drm/msm/dpu: inline _setup_dspp_ops() Dmitry Baryshkov
@ 2025-05-19 16:04 ` Dmitry Baryshkov
2025-05-20 7:58 ` neil.armstrong
2025-05-19 16:04 ` [PATCH v4 07/30] drm/msm/dpu: remove DSPP_SC7180_MASK Dmitry Baryshkov
` (23 subsequent siblings)
29 siblings, 1 reply; 64+ messages in thread
From: Dmitry Baryshkov @ 2025-05-19 16:04 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Sean Paul, Marijn Suijten, David Airlie,
Simona Vetter, Vinod Koul, Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel,
Dmitry Baryshkov
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Inline the _setup_mixer_ops() function, it makes it easier to handle
different conditions involving LM configuration.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 24 +++++++++---------------
1 file changed, 9 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
index 81b56f066519a68c9e72f0b42df12652139ab83a..4f57cfca89bd3962e7e512952809db0300cb9baf 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
@@ -144,20 +144,6 @@ static void dpu_hw_lm_setup_color3(struct dpu_hw_mixer *ctx,
DPU_REG_WRITE(c, LM_OP_MODE, op_mode);
}
-static void _setup_mixer_ops(struct dpu_hw_lm_ops *ops,
- unsigned long features)
-{
- ops->setup_mixer_out = dpu_hw_lm_setup_out;
- if (test_bit(DPU_MIXER_COMBINED_ALPHA, &features))
- ops->setup_blend_config = dpu_hw_lm_setup_blend_config_combined_alpha;
- else
- ops->setup_blend_config = dpu_hw_lm_setup_blend_config;
- ops->setup_alpha_out = dpu_hw_lm_setup_color3;
- ops->setup_border_color = dpu_hw_lm_setup_border_color;
- ops->setup_misr = dpu_hw_lm_setup_misr;
- ops->collect_misr = dpu_hw_lm_collect_misr;
-}
-
/**
* dpu_hw_lm_init() - Initializes the mixer hw driver object.
* should be called once before accessing every mixer.
@@ -186,7 +172,15 @@ struct dpu_hw_mixer *dpu_hw_lm_init(struct drm_device *dev,
/* Assign ops */
c->idx = cfg->id;
c->cap = cfg;
- _setup_mixer_ops(&c->ops, c->cap->features);
+ c->ops.setup_mixer_out = dpu_hw_lm_setup_out;
+ if (test_bit(DPU_MIXER_COMBINED_ALPHA, &c->cap->features))
+ c->ops.setup_blend_config = dpu_hw_lm_setup_blend_config_combined_alpha;
+ else
+ c->ops.setup_blend_config = dpu_hw_lm_setup_blend_config;
+ c->ops.setup_alpha_out = dpu_hw_lm_setup_color3;
+ c->ops.setup_border_color = dpu_hw_lm_setup_border_color;
+ c->ops.setup_misr = dpu_hw_lm_setup_misr;
+ c->ops.collect_misr = dpu_hw_lm_collect_misr;
return c;
}
--
2.39.5
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH v4 06/30] drm/msm/dpu: inline _setup_mixer_ops()
2025-05-19 16:04 ` [PATCH v4 06/30] drm/msm/dpu: inline _setup_mixer_ops() Dmitry Baryshkov
@ 2025-05-20 7:58 ` neil.armstrong
0 siblings, 0 replies; 64+ messages in thread
From: neil.armstrong @ 2025-05-20 7:58 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Abhinav Kumar, Sean Paul,
Marijn Suijten, David Airlie, Simona Vetter, Vinod Koul,
Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel,
Dmitry Baryshkov
On 19/05/2025 18:04, Dmitry Baryshkov wrote:
> From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>
> Inline the _setup_mixer_ops() function, it makes it easier to handle
> different conditions involving LM configuration.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 24 +++++++++---------------
> 1 file changed, 9 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
> index 81b56f066519a68c9e72f0b42df12652139ab83a..4f57cfca89bd3962e7e512952809db0300cb9baf 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
> @@ -144,20 +144,6 @@ static void dpu_hw_lm_setup_color3(struct dpu_hw_mixer *ctx,
> DPU_REG_WRITE(c, LM_OP_MODE, op_mode);
> }
>
> -static void _setup_mixer_ops(struct dpu_hw_lm_ops *ops,
> - unsigned long features)
> -{
> - ops->setup_mixer_out = dpu_hw_lm_setup_out;
> - if (test_bit(DPU_MIXER_COMBINED_ALPHA, &features))
> - ops->setup_blend_config = dpu_hw_lm_setup_blend_config_combined_alpha;
> - else
> - ops->setup_blend_config = dpu_hw_lm_setup_blend_config;
> - ops->setup_alpha_out = dpu_hw_lm_setup_color3;
> - ops->setup_border_color = dpu_hw_lm_setup_border_color;
> - ops->setup_misr = dpu_hw_lm_setup_misr;
> - ops->collect_misr = dpu_hw_lm_collect_misr;
> -}
> -
> /**
> * dpu_hw_lm_init() - Initializes the mixer hw driver object.
> * should be called once before accessing every mixer.
> @@ -186,7 +172,15 @@ struct dpu_hw_mixer *dpu_hw_lm_init(struct drm_device *dev,
> /* Assign ops */
> c->idx = cfg->id;
> c->cap = cfg;
> - _setup_mixer_ops(&c->ops, c->cap->features);
> + c->ops.setup_mixer_out = dpu_hw_lm_setup_out;
> + if (test_bit(DPU_MIXER_COMBINED_ALPHA, &c->cap->features))
> + c->ops.setup_blend_config = dpu_hw_lm_setup_blend_config_combined_alpha;
> + else
> + c->ops.setup_blend_config = dpu_hw_lm_setup_blend_config;
> + c->ops.setup_alpha_out = dpu_hw_lm_setup_color3;
> + c->ops.setup_border_color = dpu_hw_lm_setup_border_color;
> + c->ops.setup_misr = dpu_hw_lm_setup_misr;
> + c->ops.collect_misr = dpu_hw_lm_collect_misr;
>
> return c;
> }
>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH v4 07/30] drm/msm/dpu: remove DSPP_SC7180_MASK
2025-05-19 16:04 [PATCH v4 00/30] drm/msm/dpu: rework HW block feature handling Dmitry Baryshkov
` (5 preceding siblings ...)
2025-05-19 16:04 ` [PATCH v4 06/30] drm/msm/dpu: inline _setup_mixer_ops() Dmitry Baryshkov
@ 2025-05-19 16:04 ` Dmitry Baryshkov
2025-05-20 7:58 ` neil.armstrong
2025-05-19 16:04 ` [PATCH v4 08/30] drm/msm/dpu: get rid of DPU_CTL_HAS_LAYER_EXT4 Dmitry Baryshkov
` (22 subsequent siblings)
29 siblings, 1 reply; 64+ messages in thread
From: Dmitry Baryshkov @ 2025-05-19 16:04 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Sean Paul, Marijn Suijten, David Airlie,
Simona Vetter, Vinod Koul, Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel,
Dmitry Baryshkov
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Stop declaring DPU_DSPP_PCC as a part of the DSPP features, use the
presence of the PCC sblk to check whether PCC is present in the hardware
or not.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 4 ----
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h | 2 --
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 2 --
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h | 2 --
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 4 ----
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h | 2 --
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 4 ----
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 4 ----
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h | 2 --
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 4 ----
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 4 ----
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 4 ----
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 4 ----
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 4 ----
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 4 ----
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h | 4 ----
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 4 ----
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 --
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c | 2 +-
31 files changed, 1 insertion(+), 73 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
index 61420821a5f2dd5e56b8336c898290a2552c77fa..b14d0d6886f019c8fa06047baf734e38696f14ce 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
@@ -189,22 +189,18 @@ static const struct dpu_dspp_cfg sm8650_dspp[] = {
{
.name = "dspp_0", .id = DSPP_0,
.base = 0x54000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &sdm845_dspp_sblk,
}, {
.name = "dspp_1", .id = DSPP_1,
.base = 0x56000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &sdm845_dspp_sblk,
}, {
.name = "dspp_2", .id = DSPP_2,
.base = 0x58000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &sdm845_dspp_sblk,
}, {
.name = "dspp_3", .id = DSPP_3,
.base = 0x5a000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &sdm845_dspp_sblk,
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h
index 39027a21c6feecfba2d164799d9d982fc282d06b..c0b4db94777c42efd941fdd52993b854ab54c694 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h
@@ -116,7 +116,6 @@ static const struct dpu_dspp_cfg msm8937_dspp[] = {
{
.name = "dspp_0", .id = DSPP_0,
.base = 0x54000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &msm8998_dspp_sblk,
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h
index 8d1b43ea1663cfbf35bed7b913d5d0bd16757162..d3e4c48be306a04b457cc002910eb018a3f13154 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h
@@ -103,7 +103,6 @@ static const struct dpu_dspp_cfg msm8917_dspp[] = {
{
.name = "dspp_0", .id = DSPP_0,
.base = 0x54000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &msm8998_dspp_sblk,
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h
index 16c12499b24bb4cb4a7f126dd6580d9d366142d8..c488b88332d0e69cfb23bcf4e41a2e4f4be6844d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h
@@ -116,7 +116,6 @@ static const struct dpu_dspp_cfg msm8953_dspp[] = {
{
.name = "dspp_0", .id = DSPP_0,
.base = 0x54000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &msm8998_dspp_sblk,
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
index 91f514d28ac62deeafa843b5fbd0c8eb856fa49e..8fe07a5683f734a058e7e7250f0811e3b7b7cf07 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
@@ -223,12 +223,10 @@ static const struct dpu_dspp_cfg msm8996_dspp[] = {
{
.name = "dspp_0", .id = DSPP_0,
.base = 0x54000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &msm8998_dspp_sblk,
}, {
.name = "dspp_1", .id = DSPP_1,
.base = 0x56000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &msm8998_dspp_sblk,
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
index 413cd59dc0c4270973b34fc3a19405feff5b47e3..91285519c540025abce5c51f2f28442ed9d479b0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
@@ -212,12 +212,10 @@ static const struct dpu_dspp_cfg msm8998_dspp[] = {
{
.name = "dspp_0", .id = DSPP_0,
.base = 0x54000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &msm8998_dspp_sblk,
}, {
.name = "dspp_1", .id = DSPP_1,
.base = 0x56000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &msm8998_dspp_sblk,
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h
index b2eb7ca699e3ddacee441216be647784c9bbfcb5..50e0e3aec23c02acc1ce2d2a8a5658d6d49a62ac 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h
@@ -183,12 +183,10 @@ static const struct dpu_dspp_cfg sdm660_dspp[] = {
{
.name = "dspp_0", .id = DSPP_0,
.base = 0x54000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &msm8998_dspp_sblk,
}, {
.name = "dspp_1", .id = DSPP_1,
.base = 0x56000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &msm8998_dspp_sblk,
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h
index 85e121ad84a0f35fe2ba45cb76856ad83effdf44..1c299491e61f0465a164be74b7a754435f347cb6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h
@@ -133,7 +133,6 @@ static const struct dpu_dspp_cfg sdm630_dspp[] = {
{
.name = "dspp_0", .id = DSPP_0,
.base = 0x54000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &msm8998_dspp_sblk,
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
index 49363d7d5b9384dd66ed02ee9ada05b24355f1bf..50e40405a5271ea6b12caa7a931ff7fe3f2478a8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
@@ -170,22 +170,18 @@ static const struct dpu_dspp_cfg sdm845_dspp[] = {
{
.name = "dspp_0", .id = DSPP_0,
.base = 0x54000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &sdm845_dspp_sblk,
}, {
.name = "dspp_1", .id = DSPP_1,
.base = 0x56000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &sdm845_dspp_sblk,
}, {
.name = "dspp_2", .id = DSPP_2,
.base = 0x58000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &sdm845_dspp_sblk,
}, {
.name = "dspp_3", .id = DSPP_3,
.base = 0x5a000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &sdm845_dspp_sblk,
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h
index c2fde980fb521d9259a9f1e3bf88cc81f46fdfe8..3a60432a758a942eb1541f143018bd466b2bdf20 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h
@@ -103,12 +103,10 @@ static const struct dpu_dspp_cfg sdm670_dspp[] = {
{
.name = "dspp_0", .id = DSPP_0,
.base = 0x54000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &sdm845_dspp_sblk,
}, {
.name = "dspp_1", .id = DSPP_1,
.base = 0x56000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &sdm845_dspp_sblk,
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
index 08d38e1d420c1ceb9cc527b260c08edcddb139f4..b2ee5ee01870507d9f01020443c30dc573414c72 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
@@ -193,22 +193,18 @@ static const struct dpu_dspp_cfg sm8150_dspp[] = {
{
.name = "dspp_0", .id = DSPP_0,
.base = 0x54000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &sdm845_dspp_sblk,
}, {
.name = "dspp_1", .id = DSPP_1,
.base = 0x56000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &sdm845_dspp_sblk,
}, {
.name = "dspp_2", .id = DSPP_2,
.base = 0x58000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &sdm845_dspp_sblk,
}, {
.name = "dspp_3", .id = DSPP_3,
.base = 0x5a000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &sdm845_dspp_sblk,
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
index d6f8b1030c68a428a144428b422b63b960c2fdba..6db04c668a87a9f7baea01a9ea2a0f1bbb1212bf 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
@@ -193,22 +193,18 @@ static const struct dpu_dspp_cfg sc8180x_dspp[] = {
{
.name = "dspp_0", .id = DSPP_0,
.base = 0x54000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &sdm845_dspp_sblk,
}, {
.name = "dspp_1", .id = DSPP_1,
.base = 0x56000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &sdm845_dspp_sblk,
}, {
.name = "dspp_2", .id = DSPP_2,
.base = 0x58000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &sdm845_dspp_sblk,
}, {
.name = "dspp_3", .id = DSPP_3,
.base = 0x5a000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &sdm845_dspp_sblk,
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
index 71ba48b0565648a02044d444d0242fe04cb34478..6f61ce85c536e36b65b98ba4740711cb495a7c9a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
@@ -150,12 +150,10 @@ static const struct dpu_dspp_cfg sm7150_dspp[] = {
{
.name = "dspp_0", .id = DSPP_0,
.base = 0x54000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &sdm845_dspp_sblk,
}, {
.name = "dspp_1", .id = DSPP_1,
.base = 0x56000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &sdm845_dspp_sblk,
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
index da11830d44072666e47b0505e2edc3ae7717eb23..dc6d8fd05c2e3afbe5182b1ae8dd9fea8b6543e5 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
@@ -136,7 +136,6 @@ static const struct dpu_dspp_cfg sm6150_dspp[] = {
{
.name = "dspp_0", .id = DSPP_0,
.base = 0x54000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &sdm845_dspp_sblk,
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
index fcfb3774f7a18d8e01546a3ac72aa29f7b750443..192e90b570dbf8f5c3c24f572443e111f6cf3db2 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
@@ -117,7 +117,6 @@ static const struct dpu_dspp_cfg sm6125_dspp[] = {
{
.name = "dspp_0", .id = DSPP_0,
.base = 0x54000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &sdm845_dspp_sblk,
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
index a86fdb33ebddc7f2a9914ef04899397e3271b79e..bdd92b5a61eabc6a1d5e0bfe740ed6d9f1e8e94f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
@@ -191,22 +191,18 @@ static const struct dpu_dspp_cfg sm8250_dspp[] = {
{
.name = "dspp_0", .id = DSPP_0,
.base = 0x54000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &sdm845_dspp_sblk,
}, {
.name = "dspp_1", .id = DSPP_1,
.base = 0x56000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &sdm845_dspp_sblk,
}, {
.name = "dspp_2", .id = DSPP_2,
.base = 0x58000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &sdm845_dspp_sblk,
}, {
.name = "dspp_3", .id = DSPP_3,
.base = 0x5a000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &sdm845_dspp_sblk,
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
index 842fcc5887fef15789fbc686fe2156b6b509b45c..ce2ec6af5f53e2177009ca8826ca510fa08c03c7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
@@ -106,7 +106,6 @@ static const struct dpu_dspp_cfg sc7180_dspp[] = {
{
.name = "dspp_0", .id = DSPP_0,
.base = 0x54000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &sdm845_dspp_sblk,
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
index c5fd89dd7c89046bdbf1b1bf223aac2e3c4c0b26..986179b53f8b59200d10f5159cac630732dc7196 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
@@ -69,7 +69,6 @@ static const struct dpu_dspp_cfg sm6115_dspp[] = {
{
.name = "dspp_0", .id = DSPP_0,
.base = 0x54000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &sdm845_dspp_sblk,
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
index a234bb289d247d065b336564faea8dc35b00def9..c2321a4a7d3894d85062d083b45402950122007b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
@@ -115,7 +115,6 @@ static const struct dpu_dspp_cfg sm6350_dspp[] = {
{
.name = "dspp_0", .id = DSPP_0,
.base = 0x54000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &sdm845_dspp_sblk,
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
index 53f3be28f6f61bb7e3f519b0efa4cb2f68d38810..c3dd2383bd5f32926b50d98c937da25ed59d7cb3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
@@ -69,7 +69,6 @@ static const struct dpu_dspp_cfg qcm2290_dspp[] = {
{
.name = "dspp_0", .id = DSPP_0,
.base = 0x54000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &sdm845_dspp_sblk,
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
index 3a3bc8e429be0ba86185741b6b27d8a62489779f..abeaa2b8e06fdf6ce5cec2c1a4fd025a342f5a2f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
@@ -71,7 +71,6 @@ static const struct dpu_dspp_cfg sm6375_dspp[] = {
{
.name = "dspp_0", .id = DSPP_0,
.base = 0x54000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &sdm845_dspp_sblk,
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
index e887e78059a81569fac8a4246ad63856dc48cfcb..bbef0e1c597299d24a923e1f0d977c99afedb8fb 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
@@ -191,22 +191,18 @@ static const struct dpu_dspp_cfg sm8350_dspp[] = {
{
.name = "dspp_0", .id = DSPP_0,
.base = 0x54000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &sdm845_dspp_sblk,
}, {
.name = "dspp_1", .id = DSPP_1,
.base = 0x56000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &sdm845_dspp_sblk,
}, {
.name = "dspp_2", .id = DSPP_2,
.base = 0x58000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &sdm845_dspp_sblk,
}, {
.name = "dspp_3", .id = DSPP_3,
.base = 0x5a000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &sdm845_dspp_sblk,
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
index 1edec0644b078ac1fff129354d4d02eec015a331..281826170da082fc90a05c641060901ece0fbed3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
@@ -117,7 +117,6 @@ static const struct dpu_dspp_cfg sc7280_dspp[] = {
{
.name = "dspp_0", .id = DSPP_0,
.base = 0x54000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &sdm845_dspp_sblk,
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
index 9d60208745138bf29a7bdbd14ef28a2102f36f9f..1dd0a1aa222d65f03013d634a87371dc552b5bd8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
@@ -191,22 +191,18 @@ static const struct dpu_dspp_cfg sc8280xp_dspp[] = {
{
.name = "dspp_0", .id = DSPP_0,
.base = 0x54000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &sdm845_dspp_sblk,
}, {
.name = "dspp_1", .id = DSPP_1,
.base = 0x56000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &sdm845_dspp_sblk,
}, {
.name = "dspp_2", .id = DSPP_2,
.base = 0x58000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &sdm845_dspp_sblk,
}, {
.name = "dspp_3", .id = DSPP_3,
.base = 0x5a000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &sdm845_dspp_sblk,
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
index 631154059c31e8ce1b9e3631552ce49aa589d4cf..50142b14e24eb875e72e5cff3b28ff8aba89fc9c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
@@ -192,22 +192,18 @@ static const struct dpu_dspp_cfg sm8450_dspp[] = {
{
.name = "dspp_0", .id = DSPP_0,
.base = 0x54000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &sdm845_dspp_sblk,
}, {
.name = "dspp_1", .id = DSPP_1,
.base = 0x56000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &sdm845_dspp_sblk,
}, {
.name = "dspp_2", .id = DSPP_2,
.base = 0x58000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &sdm845_dspp_sblk,
}, {
.name = "dspp_3", .id = DSPP_3,
.base = 0x5a000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &sdm845_dspp_sblk,
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
index 3547fdfb28cae6cd8d1909b268b88676afad0be7..264cd6d3640be1bf321fda429748ecdafbeed214 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
@@ -191,22 +191,18 @@ static const struct dpu_dspp_cfg sa8775p_dspp[] = {
{
.name = "dspp_0", .id = DSPP_0,
.base = 0x54000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &sdm845_dspp_sblk,
}, {
.name = "dspp_1", .id = DSPP_1,
.base = 0x56000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &sdm845_dspp_sblk,
}, {
.name = "dspp_2", .id = DSPP_2,
.base = 0x58000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &sdm845_dspp_sblk,
}, {
.name = "dspp_3", .id = DSPP_3,
.base = 0x5a000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &sdm845_dspp_sblk,
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
index e16e47a6f426359548434569ad632aa68f32908d..4c5785332b5240109af36a1256d4ea29c348bced 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
@@ -189,22 +189,18 @@ static const struct dpu_dspp_cfg sm8550_dspp[] = {
{
.name = "dspp_0", .id = DSPP_0,
.base = 0x54000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &sdm845_dspp_sblk,
}, {
.name = "dspp_1", .id = DSPP_1,
.base = 0x56000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &sdm845_dspp_sblk,
}, {
.name = "dspp_2", .id = DSPP_2,
.base = 0x58000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &sdm845_dspp_sblk,
}, {
.name = "dspp_3", .id = DSPP_3,
.base = 0x5a000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &sdm845_dspp_sblk,
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
index f85d5d7ae51d64203647a8bcec91f524c6e33528..960c68f33074e0cec0f33aa7d4f8f3b4cc69bac5 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
@@ -189,22 +189,18 @@ static const struct dpu_dspp_cfg sar2130p_dspp[] = {
{
.name = "dspp_0", .id = DSPP_0,
.base = 0x54000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &sdm845_dspp_sblk,
}, {
.name = "dspp_1", .id = DSPP_1,
.base = 0x56000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &sdm845_dspp_sblk,
}, {
.name = "dspp_2", .id = DSPP_2,
.base = 0x58000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &sdm845_dspp_sblk,
}, {
.name = "dspp_3", .id = DSPP_3,
.base = 0x5a000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &sdm845_dspp_sblk,
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
index 0d6511f90975508b36b0fa00a92349a82eff4d52..85dcf577b844995fe11322ec506885bc4a85e33c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
@@ -188,22 +188,18 @@ static const struct dpu_dspp_cfg x1e80100_dspp[] = {
{
.name = "dspp_0", .id = DSPP_0,
.base = 0x54000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &sdm845_dspp_sblk,
}, {
.name = "dspp_1", .id = DSPP_1,
.base = 0x56000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &sdm845_dspp_sblk,
}, {
.name = "dspp_2", .id = DSPP_2,
.base = 0x58000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &sdm845_dspp_sblk,
}, {
.name = "dspp_3", .id = DSPP_3,
.base = 0x5a000, .len = 0x1800,
- .features = DSPP_SC7180_MASK,
.sblk = &sdm845_dspp_sblk,
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index d383368c743b202d7256f6759deecaf9d756bb02..00e6f3e56ed1f9af581bad9845971fad315ef83c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -113,8 +113,6 @@
#define CTL_SM8550_MASK \
(CTL_SC7280_MASK | BIT(DPU_CTL_HAS_LAYER_EXT4))
-#define DSPP_SC7180_MASK BIT(DPU_DSPP_PCC)
-
#define INTF_SC7180_MASK \
(BIT(DPU_INTF_INPUT_CTRL) | \
BIT(DPU_INTF_STATUS_SUPPORTED) | \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
index 0f5a74398e66642fba48c112db41ffc75ae2a79f..11fb1bc54fa92a5d9926addb437bc4b8f283723b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
@@ -90,7 +90,7 @@ struct dpu_hw_dspp *dpu_hw_dspp_init(struct drm_device *dev,
/* Assign ops */
c->idx = cfg->id;
c->cap = cfg;
- if (test_bit(DPU_DSPP_PCC, &c->cap->features))
+ if (c->cap->sblk->pcc.base)
c->ops.setup_pcc = dpu_setup_dspp_pcc;
return c;
--
2.39.5
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH v4 07/30] drm/msm/dpu: remove DSPP_SC7180_MASK
2025-05-19 16:04 ` [PATCH v4 07/30] drm/msm/dpu: remove DSPP_SC7180_MASK Dmitry Baryshkov
@ 2025-05-20 7:58 ` neil.armstrong
0 siblings, 0 replies; 64+ messages in thread
From: neil.armstrong @ 2025-05-20 7:58 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Abhinav Kumar, Sean Paul,
Marijn Suijten, David Airlie, Simona Vetter, Vinod Koul,
Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel,
Dmitry Baryshkov
On 19/05/2025 18:04, Dmitry Baryshkov wrote:
> From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>
> Stop declaring DPU_DSPP_PCC as a part of the DSPP features, use the
> presence of the PCC sblk to check whether PCC is present in the hardware
> or not.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 4 ----
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h | 1 -
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h | 1 -
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h | 1 -
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h | 2 --
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 2 --
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h | 2 --
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h | 1 -
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 4 ----
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h | 2 --
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 4 ----
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 4 ----
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h | 2 --
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h | 1 -
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 1 -
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 4 ----
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 1 -
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 1 -
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 1 -
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 1 -
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 1 -
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 4 ----
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 1 -
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 4 ----
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 4 ----
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 4 ----
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 4 ----
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h | 4 ----
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 4 ----
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 --
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c | 2 +-
> 31 files changed, 1 insertion(+), 73 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
> index 61420821a5f2dd5e56b8336c898290a2552c77fa..b14d0d6886f019c8fa06047baf734e38696f14ce 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
> @@ -189,22 +189,18 @@ static const struct dpu_dspp_cfg sm8650_dspp[] = {
> {
> .name = "dspp_0", .id = DSPP_0,
> .base = 0x54000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &sdm845_dspp_sblk,
> }, {
> .name = "dspp_1", .id = DSPP_1,
> .base = 0x56000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &sdm845_dspp_sblk,
> }, {
> .name = "dspp_2", .id = DSPP_2,
> .base = 0x58000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &sdm845_dspp_sblk,
> }, {
> .name = "dspp_3", .id = DSPP_3,
> .base = 0x5a000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &sdm845_dspp_sblk,
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h
> index 39027a21c6feecfba2d164799d9d982fc282d06b..c0b4db94777c42efd941fdd52993b854ab54c694 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h
> @@ -116,7 +116,6 @@ static const struct dpu_dspp_cfg msm8937_dspp[] = {
> {
> .name = "dspp_0", .id = DSPP_0,
> .base = 0x54000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &msm8998_dspp_sblk,
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h
> index 8d1b43ea1663cfbf35bed7b913d5d0bd16757162..d3e4c48be306a04b457cc002910eb018a3f13154 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h
> @@ -103,7 +103,6 @@ static const struct dpu_dspp_cfg msm8917_dspp[] = {
> {
> .name = "dspp_0", .id = DSPP_0,
> .base = 0x54000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &msm8998_dspp_sblk,
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h
> index 16c12499b24bb4cb4a7f126dd6580d9d366142d8..c488b88332d0e69cfb23bcf4e41a2e4f4be6844d 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h
> @@ -116,7 +116,6 @@ static const struct dpu_dspp_cfg msm8953_dspp[] = {
> {
> .name = "dspp_0", .id = DSPP_0,
> .base = 0x54000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &msm8998_dspp_sblk,
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
> index 91f514d28ac62deeafa843b5fbd0c8eb856fa49e..8fe07a5683f734a058e7e7250f0811e3b7b7cf07 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
> @@ -223,12 +223,10 @@ static const struct dpu_dspp_cfg msm8996_dspp[] = {
> {
> .name = "dspp_0", .id = DSPP_0,
> .base = 0x54000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &msm8998_dspp_sblk,
> }, {
> .name = "dspp_1", .id = DSPP_1,
> .base = 0x56000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &msm8998_dspp_sblk,
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> index 413cd59dc0c4270973b34fc3a19405feff5b47e3..91285519c540025abce5c51f2f28442ed9d479b0 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> @@ -212,12 +212,10 @@ static const struct dpu_dspp_cfg msm8998_dspp[] = {
> {
> .name = "dspp_0", .id = DSPP_0,
> .base = 0x54000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &msm8998_dspp_sblk,
> }, {
> .name = "dspp_1", .id = DSPP_1,
> .base = 0x56000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &msm8998_dspp_sblk,
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h
> index b2eb7ca699e3ddacee441216be647784c9bbfcb5..50e0e3aec23c02acc1ce2d2a8a5658d6d49a62ac 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h
> @@ -183,12 +183,10 @@ static const struct dpu_dspp_cfg sdm660_dspp[] = {
> {
> .name = "dspp_0", .id = DSPP_0,
> .base = 0x54000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &msm8998_dspp_sblk,
> }, {
> .name = "dspp_1", .id = DSPP_1,
> .base = 0x56000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &msm8998_dspp_sblk,
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h
> index 85e121ad84a0f35fe2ba45cb76856ad83effdf44..1c299491e61f0465a164be74b7a754435f347cb6 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h
> @@ -133,7 +133,6 @@ static const struct dpu_dspp_cfg sdm630_dspp[] = {
> {
> .name = "dspp_0", .id = DSPP_0,
> .base = 0x54000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &msm8998_dspp_sblk,
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> index 49363d7d5b9384dd66ed02ee9ada05b24355f1bf..50e40405a5271ea6b12caa7a931ff7fe3f2478a8 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> @@ -170,22 +170,18 @@ static const struct dpu_dspp_cfg sdm845_dspp[] = {
> {
> .name = "dspp_0", .id = DSPP_0,
> .base = 0x54000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &sdm845_dspp_sblk,
> }, {
> .name = "dspp_1", .id = DSPP_1,
> .base = 0x56000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &sdm845_dspp_sblk,
> }, {
> .name = "dspp_2", .id = DSPP_2,
> .base = 0x58000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &sdm845_dspp_sblk,
> }, {
> .name = "dspp_3", .id = DSPP_3,
> .base = 0x5a000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &sdm845_dspp_sblk,
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h
> index c2fde980fb521d9259a9f1e3bf88cc81f46fdfe8..3a60432a758a942eb1541f143018bd466b2bdf20 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h
> @@ -103,12 +103,10 @@ static const struct dpu_dspp_cfg sdm670_dspp[] = {
> {
> .name = "dspp_0", .id = DSPP_0,
> .base = 0x54000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &sdm845_dspp_sblk,
> }, {
> .name = "dspp_1", .id = DSPP_1,
> .base = 0x56000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &sdm845_dspp_sblk,
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> index 08d38e1d420c1ceb9cc527b260c08edcddb139f4..b2ee5ee01870507d9f01020443c30dc573414c72 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> @@ -193,22 +193,18 @@ static const struct dpu_dspp_cfg sm8150_dspp[] = {
> {
> .name = "dspp_0", .id = DSPP_0,
> .base = 0x54000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &sdm845_dspp_sblk,
> }, {
> .name = "dspp_1", .id = DSPP_1,
> .base = 0x56000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &sdm845_dspp_sblk,
> }, {
> .name = "dspp_2", .id = DSPP_2,
> .base = 0x58000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &sdm845_dspp_sblk,
> }, {
> .name = "dspp_3", .id = DSPP_3,
> .base = 0x5a000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &sdm845_dspp_sblk,
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> index d6f8b1030c68a428a144428b422b63b960c2fdba..6db04c668a87a9f7baea01a9ea2a0f1bbb1212bf 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> @@ -193,22 +193,18 @@ static const struct dpu_dspp_cfg sc8180x_dspp[] = {
> {
> .name = "dspp_0", .id = DSPP_0,
> .base = 0x54000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &sdm845_dspp_sblk,
> }, {
> .name = "dspp_1", .id = DSPP_1,
> .base = 0x56000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &sdm845_dspp_sblk,
> }, {
> .name = "dspp_2", .id = DSPP_2,
> .base = 0x58000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &sdm845_dspp_sblk,
> }, {
> .name = "dspp_3", .id = DSPP_3,
> .base = 0x5a000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &sdm845_dspp_sblk,
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
> index 71ba48b0565648a02044d444d0242fe04cb34478..6f61ce85c536e36b65b98ba4740711cb495a7c9a 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
> @@ -150,12 +150,10 @@ static const struct dpu_dspp_cfg sm7150_dspp[] = {
> {
> .name = "dspp_0", .id = DSPP_0,
> .base = 0x54000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &sdm845_dspp_sblk,
> }, {
> .name = "dspp_1", .id = DSPP_1,
> .base = 0x56000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &sdm845_dspp_sblk,
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
> index da11830d44072666e47b0505e2edc3ae7717eb23..dc6d8fd05c2e3afbe5182b1ae8dd9fea8b6543e5 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
> @@ -136,7 +136,6 @@ static const struct dpu_dspp_cfg sm6150_dspp[] = {
> {
> .name = "dspp_0", .id = DSPP_0,
> .base = 0x54000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &sdm845_dspp_sblk,
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
> index fcfb3774f7a18d8e01546a3ac72aa29f7b750443..192e90b570dbf8f5c3c24f572443e111f6cf3db2 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
> @@ -117,7 +117,6 @@ static const struct dpu_dspp_cfg sm6125_dspp[] = {
> {
> .name = "dspp_0", .id = DSPP_0,
> .base = 0x54000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &sdm845_dspp_sblk,
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> index a86fdb33ebddc7f2a9914ef04899397e3271b79e..bdd92b5a61eabc6a1d5e0bfe740ed6d9f1e8e94f 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> @@ -191,22 +191,18 @@ static const struct dpu_dspp_cfg sm8250_dspp[] = {
> {
> .name = "dspp_0", .id = DSPP_0,
> .base = 0x54000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &sdm845_dspp_sblk,
> }, {
> .name = "dspp_1", .id = DSPP_1,
> .base = 0x56000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &sdm845_dspp_sblk,
> }, {
> .name = "dspp_2", .id = DSPP_2,
> .base = 0x58000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &sdm845_dspp_sblk,
> }, {
> .name = "dspp_3", .id = DSPP_3,
> .base = 0x5a000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &sdm845_dspp_sblk,
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> index 842fcc5887fef15789fbc686fe2156b6b509b45c..ce2ec6af5f53e2177009ca8826ca510fa08c03c7 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> @@ -106,7 +106,6 @@ static const struct dpu_dspp_cfg sc7180_dspp[] = {
> {
> .name = "dspp_0", .id = DSPP_0,
> .base = 0x54000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &sdm845_dspp_sblk,
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> index c5fd89dd7c89046bdbf1b1bf223aac2e3c4c0b26..986179b53f8b59200d10f5159cac630732dc7196 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> @@ -69,7 +69,6 @@ static const struct dpu_dspp_cfg sm6115_dspp[] = {
> {
> .name = "dspp_0", .id = DSPP_0,
> .base = 0x54000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &sdm845_dspp_sblk,
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> index a234bb289d247d065b336564faea8dc35b00def9..c2321a4a7d3894d85062d083b45402950122007b 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> @@ -115,7 +115,6 @@ static const struct dpu_dspp_cfg sm6350_dspp[] = {
> {
> .name = "dspp_0", .id = DSPP_0,
> .base = 0x54000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &sdm845_dspp_sblk,
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> index 53f3be28f6f61bb7e3f519b0efa4cb2f68d38810..c3dd2383bd5f32926b50d98c937da25ed59d7cb3 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> @@ -69,7 +69,6 @@ static const struct dpu_dspp_cfg qcm2290_dspp[] = {
> {
> .name = "dspp_0", .id = DSPP_0,
> .base = 0x54000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &sdm845_dspp_sblk,
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
> index 3a3bc8e429be0ba86185741b6b27d8a62489779f..abeaa2b8e06fdf6ce5cec2c1a4fd025a342f5a2f 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
> @@ -71,7 +71,6 @@ static const struct dpu_dspp_cfg sm6375_dspp[] = {
> {
> .name = "dspp_0", .id = DSPP_0,
> .base = 0x54000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &sdm845_dspp_sblk,
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> index e887e78059a81569fac8a4246ad63856dc48cfcb..bbef0e1c597299d24a923e1f0d977c99afedb8fb 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> @@ -191,22 +191,18 @@ static const struct dpu_dspp_cfg sm8350_dspp[] = {
> {
> .name = "dspp_0", .id = DSPP_0,
> .base = 0x54000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &sdm845_dspp_sblk,
> }, {
> .name = "dspp_1", .id = DSPP_1,
> .base = 0x56000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &sdm845_dspp_sblk,
> }, {
> .name = "dspp_2", .id = DSPP_2,
> .base = 0x58000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &sdm845_dspp_sblk,
> }, {
> .name = "dspp_3", .id = DSPP_3,
> .base = 0x5a000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &sdm845_dspp_sblk,
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> index 1edec0644b078ac1fff129354d4d02eec015a331..281826170da082fc90a05c641060901ece0fbed3 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> @@ -117,7 +117,6 @@ static const struct dpu_dspp_cfg sc7280_dspp[] = {
> {
> .name = "dspp_0", .id = DSPP_0,
> .base = 0x54000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &sdm845_dspp_sblk,
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> index 9d60208745138bf29a7bdbd14ef28a2102f36f9f..1dd0a1aa222d65f03013d634a87371dc552b5bd8 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> @@ -191,22 +191,18 @@ static const struct dpu_dspp_cfg sc8280xp_dspp[] = {
> {
> .name = "dspp_0", .id = DSPP_0,
> .base = 0x54000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &sdm845_dspp_sblk,
> }, {
> .name = "dspp_1", .id = DSPP_1,
> .base = 0x56000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &sdm845_dspp_sblk,
> }, {
> .name = "dspp_2", .id = DSPP_2,
> .base = 0x58000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &sdm845_dspp_sblk,
> }, {
> .name = "dspp_3", .id = DSPP_3,
> .base = 0x5a000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &sdm845_dspp_sblk,
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> index 631154059c31e8ce1b9e3631552ce49aa589d4cf..50142b14e24eb875e72e5cff3b28ff8aba89fc9c 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> @@ -192,22 +192,18 @@ static const struct dpu_dspp_cfg sm8450_dspp[] = {
> {
> .name = "dspp_0", .id = DSPP_0,
> .base = 0x54000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &sdm845_dspp_sblk,
> }, {
> .name = "dspp_1", .id = DSPP_1,
> .base = 0x56000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &sdm845_dspp_sblk,
> }, {
> .name = "dspp_2", .id = DSPP_2,
> .base = 0x58000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &sdm845_dspp_sblk,
> }, {
> .name = "dspp_3", .id = DSPP_3,
> .base = 0x5a000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &sdm845_dspp_sblk,
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
> index 3547fdfb28cae6cd8d1909b268b88676afad0be7..264cd6d3640be1bf321fda429748ecdafbeed214 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
> @@ -191,22 +191,18 @@ static const struct dpu_dspp_cfg sa8775p_dspp[] = {
> {
> .name = "dspp_0", .id = DSPP_0,
> .base = 0x54000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &sdm845_dspp_sblk,
> }, {
> .name = "dspp_1", .id = DSPP_1,
> .base = 0x56000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &sdm845_dspp_sblk,
> }, {
> .name = "dspp_2", .id = DSPP_2,
> .base = 0x58000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &sdm845_dspp_sblk,
> }, {
> .name = "dspp_3", .id = DSPP_3,
> .base = 0x5a000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &sdm845_dspp_sblk,
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> index e16e47a6f426359548434569ad632aa68f32908d..4c5785332b5240109af36a1256d4ea29c348bced 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> @@ -189,22 +189,18 @@ static const struct dpu_dspp_cfg sm8550_dspp[] = {
> {
> .name = "dspp_0", .id = DSPP_0,
> .base = 0x54000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &sdm845_dspp_sblk,
> }, {
> .name = "dspp_1", .id = DSPP_1,
> .base = 0x56000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &sdm845_dspp_sblk,
> }, {
> .name = "dspp_2", .id = DSPP_2,
> .base = 0x58000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &sdm845_dspp_sblk,
> }, {
> .name = "dspp_3", .id = DSPP_3,
> .base = 0x5a000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &sdm845_dspp_sblk,
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
> index f85d5d7ae51d64203647a8bcec91f524c6e33528..960c68f33074e0cec0f33aa7d4f8f3b4cc69bac5 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
> @@ -189,22 +189,18 @@ static const struct dpu_dspp_cfg sar2130p_dspp[] = {
> {
> .name = "dspp_0", .id = DSPP_0,
> .base = 0x54000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &sdm845_dspp_sblk,
> }, {
> .name = "dspp_1", .id = DSPP_1,
> .base = 0x56000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &sdm845_dspp_sblk,
> }, {
> .name = "dspp_2", .id = DSPP_2,
> .base = 0x58000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &sdm845_dspp_sblk,
> }, {
> .name = "dspp_3", .id = DSPP_3,
> .base = 0x5a000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &sdm845_dspp_sblk,
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
> index 0d6511f90975508b36b0fa00a92349a82eff4d52..85dcf577b844995fe11322ec506885bc4a85e33c 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
> @@ -188,22 +188,18 @@ static const struct dpu_dspp_cfg x1e80100_dspp[] = {
> {
> .name = "dspp_0", .id = DSPP_0,
> .base = 0x54000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &sdm845_dspp_sblk,
> }, {
> .name = "dspp_1", .id = DSPP_1,
> .base = 0x56000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &sdm845_dspp_sblk,
> }, {
> .name = "dspp_2", .id = DSPP_2,
> .base = 0x58000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &sdm845_dspp_sblk,
> }, {
> .name = "dspp_3", .id = DSPP_3,
> .base = 0x5a000, .len = 0x1800,
> - .features = DSPP_SC7180_MASK,
> .sblk = &sdm845_dspp_sblk,
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index d383368c743b202d7256f6759deecaf9d756bb02..00e6f3e56ed1f9af581bad9845971fad315ef83c 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -113,8 +113,6 @@
> #define CTL_SM8550_MASK \
> (CTL_SC7280_MASK | BIT(DPU_CTL_HAS_LAYER_EXT4))
>
> -#define DSPP_SC7180_MASK BIT(DPU_DSPP_PCC)
> -
> #define INTF_SC7180_MASK \
> (BIT(DPU_INTF_INPUT_CTRL) | \
> BIT(DPU_INTF_STATUS_SUPPORTED) | \
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
> index 0f5a74398e66642fba48c112db41ffc75ae2a79f..11fb1bc54fa92a5d9926addb437bc4b8f283723b 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
> @@ -90,7 +90,7 @@ struct dpu_hw_dspp *dpu_hw_dspp_init(struct drm_device *dev,
> /* Assign ops */
> c->idx = cfg->id;
> c->cap = cfg;
> - if (test_bit(DPU_DSPP_PCC, &c->cap->features))
> + if (c->cap->sblk->pcc.base)
> c->ops.setup_pcc = dpu_setup_dspp_pcc;
>
> return c;
>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH v4 08/30] drm/msm/dpu: get rid of DPU_CTL_HAS_LAYER_EXT4
2025-05-19 16:04 [PATCH v4 00/30] drm/msm/dpu: rework HW block feature handling Dmitry Baryshkov
` (6 preceding siblings ...)
2025-05-19 16:04 ` [PATCH v4 07/30] drm/msm/dpu: remove DSPP_SC7180_MASK Dmitry Baryshkov
@ 2025-05-19 16:04 ` Dmitry Baryshkov
2025-05-20 7:58 ` neil.armstrong
2025-05-19 16:04 ` [PATCH v4 09/30] drm/msm/dpu: get rid of DPU_CTL_ACTIVE_CFG Dmitry Baryshkov
` (21 subsequent siblings)
29 siblings, 1 reply; 64+ messages in thread
From: Dmitry Baryshkov @ 2025-05-19 16:04 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Sean Paul, Marijn Suijten, David Airlie,
Simona Vetter, Vinod Koul, Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel,
Dmitry Baryshkov
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Continue migration to the MDSS-revision based checks and replace
DPU_CTL_HAS_LAYER_EXT4 feature bit with the core_major_ver >= 9 check.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 12 ++++++------
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 12 ++++++------
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h | 12 ++++++------
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 12 ++++++------
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 ---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 --
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 5 ++++-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 4 ++++
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 2 +-
9 files changed, 33 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
index b14d0d6886f019c8fa06047baf734e38696f14ce..52ad7e2af0148c9ea81a2c95b270be7058fbaec1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
@@ -31,32 +31,32 @@ static const struct dpu_ctl_cfg sm8650_ctl[] = {
{
.name = "ctl_0", .id = CTL_0,
.base = 0x15000, .len = 0x1000,
- .features = CTL_SM8550_MASK,
+ .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
}, {
.name = "ctl_1", .id = CTL_1,
.base = 0x16000, .len = 0x1000,
- .features = CTL_SM8550_MASK,
+ .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
}, {
.name = "ctl_2", .id = CTL_2,
.base = 0x17000, .len = 0x1000,
- .features = CTL_SM8550_MASK,
+ .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
}, {
.name = "ctl_3", .id = CTL_3,
.base = 0x18000, .len = 0x1000,
- .features = CTL_SM8550_MASK,
+ .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
}, {
.name = "ctl_4", .id = CTL_4,
.base = 0x19000, .len = 0x1000,
- .features = CTL_SM8550_MASK,
+ .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
}, {
.name = "ctl_5", .id = CTL_5,
.base = 0x1a000, .len = 0x1000,
- .features = CTL_SM8550_MASK,
+ .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
index 4c5785332b5240109af36a1256d4ea29c348bced..83f73c7cdcc3a280285fa32230796fac57167ed6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
@@ -31,32 +31,32 @@ static const struct dpu_ctl_cfg sm8550_ctl[] = {
{
.name = "ctl_0", .id = CTL_0,
.base = 0x15000, .len = 0x290,
- .features = CTL_SM8550_MASK,
+ .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
}, {
.name = "ctl_1", .id = CTL_1,
.base = 0x16000, .len = 0x290,
- .features = CTL_SM8550_MASK,
+ .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
}, {
.name = "ctl_2", .id = CTL_2,
.base = 0x17000, .len = 0x290,
- .features = CTL_SM8550_MASK,
+ .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
}, {
.name = "ctl_3", .id = CTL_3,
.base = 0x18000, .len = 0x290,
- .features = CTL_SM8550_MASK,
+ .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
}, {
.name = "ctl_4", .id = CTL_4,
.base = 0x19000, .len = 0x290,
- .features = CTL_SM8550_MASK,
+ .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
}, {
.name = "ctl_5", .id = CTL_5,
.base = 0x1a000, .len = 0x290,
- .features = CTL_SM8550_MASK,
+ .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
index 960c68f33074e0cec0f33aa7d4f8f3b4cc69bac5..b21aab274703ac1f38698bee82d5d28b0fb6a0d0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
@@ -31,32 +31,32 @@ static const struct dpu_ctl_cfg sar2130p_ctl[] = {
{
.name = "ctl_0", .id = CTL_0,
.base = 0x15000, .len = 0x290,
- .features = CTL_SM8550_MASK,
+ .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
}, {
.name = "ctl_1", .id = CTL_1,
.base = 0x16000, .len = 0x290,
- .features = CTL_SM8550_MASK,
+ .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
}, {
.name = "ctl_2", .id = CTL_2,
.base = 0x17000, .len = 0x290,
- .features = CTL_SM8550_MASK,
+ .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
}, {
.name = "ctl_3", .id = CTL_3,
.base = 0x18000, .len = 0x290,
- .features = CTL_SM8550_MASK,
+ .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
}, {
.name = "ctl_4", .id = CTL_4,
.base = 0x19000, .len = 0x290,
- .features = CTL_SM8550_MASK,
+ .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
}, {
.name = "ctl_5", .id = CTL_5,
.base = 0x1a000, .len = 0x290,
- .features = CTL_SM8550_MASK,
+ .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
index 85dcf577b844995fe11322ec506885bc4a85e33c..d7e5f4dd3bccab125b0a42f67eddf194359dc761 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
@@ -30,32 +30,32 @@ static const struct dpu_ctl_cfg x1e80100_ctl[] = {
{
.name = "ctl_0", .id = CTL_0,
.base = 0x15000, .len = 0x290,
- .features = CTL_SM8550_MASK,
+ .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
}, {
.name = "ctl_1", .id = CTL_1,
.base = 0x16000, .len = 0x290,
- .features = CTL_SM8550_MASK,
+ .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
}, {
.name = "ctl_2", .id = CTL_2,
.base = 0x17000, .len = 0x290,
- .features = CTL_SM8550_MASK,
+ .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
}, {
.name = "ctl_3", .id = CTL_3,
.base = 0x18000, .len = 0x290,
- .features = CTL_SM8550_MASK,
+ .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
}, {
.name = "ctl_4", .id = CTL_4,
.base = 0x19000, .len = 0x290,
- .features = CTL_SM8550_MASK,
+ .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
}, {
.name = "ctl_5", .id = CTL_5,
.base = 0x1a000, .len = 0x290,
- .features = CTL_SM8550_MASK,
+ .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 00e6f3e56ed1f9af581bad9845971fad315ef83c..a162c4f9ebd79d3ba16b50117ee7462afdbbf3d4 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -110,9 +110,6 @@
BIT(DPU_CTL_VM_CFG) | \
BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH))
-#define CTL_SM8550_MASK \
- (CTL_SC7280_MASK | BIT(DPU_CTL_HAS_LAYER_EXT4))
-
#define INTF_SC7180_MASK \
(BIT(DPU_INTF_INPUT_CTRL) | \
BIT(DPU_INTF_STATUS_SUPPORTED) | \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 01dd6e65f777f3b92f41e2ccb08f279650d50425..3d6c2db395b65b89845cb7281195ca5ca16c22e6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -134,7 +134,6 @@ enum {
* @DPU_CTL_SPLIT_DISPLAY: CTL supports video mode split display
* @DPU_CTL_FETCH_ACTIVE: Active CTL for fetch HW (SSPPs)
* @DPU_CTL_VM_CFG: CTL config to support multiple VMs
- * @DPU_CTL_HAS_LAYER_EXT4: CTL has the CTL_LAYER_EXT4 register
* @DPU_CTL_DSPP_BLOCK_FLUSH: CTL config to support dspp sub-block flush
* @DPU_CTL_MAX
*/
@@ -143,7 +142,6 @@ enum {
DPU_CTL_ACTIVE_CFG,
DPU_CTL_FETCH_ACTIVE,
DPU_CTL_VM_CFG,
- DPU_CTL_HAS_LAYER_EXT4,
DPU_CTL_DSPP_SUB_BLOCK_FLUSH,
DPU_CTL_MAX
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index d58a0f1e8edb524ff3f21ff8c96688dd2ae49541..58bdd4d33b37d83f30931f09fdf80bef41e1f0fe 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -555,7 +555,7 @@ static void dpu_hw_ctl_setup_blendstage(struct dpu_hw_ctl *ctx,
DPU_REG_WRITE(c, CTL_LAYER_EXT(lm), mixercfg[1]);
DPU_REG_WRITE(c, CTL_LAYER_EXT2(lm), mixercfg[2]);
DPU_REG_WRITE(c, CTL_LAYER_EXT3(lm), mixercfg[3]);
- if ((test_bit(DPU_CTL_HAS_LAYER_EXT4, &ctx->caps->features)))
+ if (ctx->mdss_ver->core_major_ver >= 9)
DPU_REG_WRITE(c, CTL_LAYER_EXT4(lm), mixercfg[4]);
}
@@ -743,12 +743,14 @@ static void dpu_hw_ctl_set_active_fetch_pipes(struct dpu_hw_ctl *ctx,
* @dev: Corresponding device for devres management
* @cfg: ctl_path catalog entry for which driver object is required
* @addr: mapped register io address of MDP
+ * @mdss_ver: dpu core's major and minor versions
* @mixer_count: Number of mixers in @mixer
* @mixer: Pointer to an array of Layer Mixers defined in the catalog
*/
struct dpu_hw_ctl *dpu_hw_ctl_init(struct drm_device *dev,
const struct dpu_ctl_cfg *cfg,
void __iomem *addr,
+ const struct dpu_mdss_version *mdss_ver,
u32 mixer_count,
const struct dpu_lm_cfg *mixer)
{
@@ -762,6 +764,7 @@ struct dpu_hw_ctl *dpu_hw_ctl_init(struct drm_device *dev,
c->hw.log_mask = DPU_DBG_MASK_CTL;
c->caps = cfg;
+ c->mdss_ver = mdss_ver;
if (c->caps->features & BIT(DPU_CTL_ACTIVE_CFG)) {
c->ops.trigger_flush = dpu_hw_ctl_trigger_flush_v1;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
index feb09590bc8fc5c77c2c673fd888c28281a98b5a..9cd9959682c21cc1c6d8d14b8fb377deb33cc10d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
@@ -274,6 +274,7 @@ struct dpu_hw_ctl_ops {
* @pending_cwb_flush_mask: pending CWB flush
* @pending_dsc_flush_mask: pending DSC flush
* @pending_cdm_flush_mask: pending CDM flush
+ * @mdss_ver: MDSS revision information
* @ops: operation list
*/
struct dpu_hw_ctl {
@@ -295,6 +296,8 @@ struct dpu_hw_ctl {
u32 pending_dsc_flush_mask;
u32 pending_cdm_flush_mask;
+ const struct dpu_mdss_version *mdss_ver;
+
/* ops */
struct dpu_hw_ctl_ops ops;
};
@@ -312,6 +315,7 @@ static inline struct dpu_hw_ctl *to_dpu_hw_ctl(struct dpu_hw_blk *hw)
struct dpu_hw_ctl *dpu_hw_ctl_init(struct drm_device *dev,
const struct dpu_ctl_cfg *cfg,
void __iomem *addr,
+ const struct dpu_mdss_version *mdss_ver,
u32 mixer_count,
const struct dpu_lm_cfg *mixer);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index 2e296f79cba1437470eeb30900a650f6f4e334b6..d728e275ac427f7849dad4f4a055c56840ca2d23 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -142,7 +142,7 @@ int dpu_rm_init(struct drm_device *dev,
struct dpu_hw_ctl *hw;
const struct dpu_ctl_cfg *ctl = &cat->ctl[i];
- hw = dpu_hw_ctl_init(dev, ctl, mmio, cat->mixer_count, cat->mixer);
+ hw = dpu_hw_ctl_init(dev, ctl, mmio, cat->mdss_ver, cat->mixer_count, cat->mixer);
if (IS_ERR(hw)) {
rc = PTR_ERR(hw);
DPU_ERROR("failed ctl object creation: err %d\n", rc);
--
2.39.5
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH v4 08/30] drm/msm/dpu: get rid of DPU_CTL_HAS_LAYER_EXT4
2025-05-19 16:04 ` [PATCH v4 08/30] drm/msm/dpu: get rid of DPU_CTL_HAS_LAYER_EXT4 Dmitry Baryshkov
@ 2025-05-20 7:58 ` neil.armstrong
0 siblings, 0 replies; 64+ messages in thread
From: neil.armstrong @ 2025-05-20 7:58 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Abhinav Kumar, Sean Paul,
Marijn Suijten, David Airlie, Simona Vetter, Vinod Koul,
Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel,
Dmitry Baryshkov
On 19/05/2025 18:04, Dmitry Baryshkov wrote:
> From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>
> Continue migration to the MDSS-revision based checks and replace
> DPU_CTL_HAS_LAYER_EXT4 feature bit with the core_major_ver >= 9 check.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 12 ++++++------
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 12 ++++++------
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h | 12 ++++++------
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 12 ++++++------
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 --
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 5 ++++-
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 4 ++++
> drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 2 +-
> 9 files changed, 33 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
> index b14d0d6886f019c8fa06047baf734e38696f14ce..52ad7e2af0148c9ea81a2c95b270be7058fbaec1 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
> @@ -31,32 +31,32 @@ static const struct dpu_ctl_cfg sm8650_ctl[] = {
> {
> .name = "ctl_0", .id = CTL_0,
> .base = 0x15000, .len = 0x1000,
> - .features = CTL_SM8550_MASK,
> + .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> }, {
> .name = "ctl_1", .id = CTL_1,
> .base = 0x16000, .len = 0x1000,
> - .features = CTL_SM8550_MASK,
> + .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> }, {
> .name = "ctl_2", .id = CTL_2,
> .base = 0x17000, .len = 0x1000,
> - .features = CTL_SM8550_MASK,
> + .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> }, {
> .name = "ctl_3", .id = CTL_3,
> .base = 0x18000, .len = 0x1000,
> - .features = CTL_SM8550_MASK,
> + .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> }, {
> .name = "ctl_4", .id = CTL_4,
> .base = 0x19000, .len = 0x1000,
> - .features = CTL_SM8550_MASK,
> + .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
> }, {
> .name = "ctl_5", .id = CTL_5,
> .base = 0x1a000, .len = 0x1000,
> - .features = CTL_SM8550_MASK,
> + .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> index 4c5785332b5240109af36a1256d4ea29c348bced..83f73c7cdcc3a280285fa32230796fac57167ed6 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> @@ -31,32 +31,32 @@ static const struct dpu_ctl_cfg sm8550_ctl[] = {
> {
> .name = "ctl_0", .id = CTL_0,
> .base = 0x15000, .len = 0x290,
> - .features = CTL_SM8550_MASK,
> + .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> }, {
> .name = "ctl_1", .id = CTL_1,
> .base = 0x16000, .len = 0x290,
> - .features = CTL_SM8550_MASK,
> + .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> }, {
> .name = "ctl_2", .id = CTL_2,
> .base = 0x17000, .len = 0x290,
> - .features = CTL_SM8550_MASK,
> + .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> }, {
> .name = "ctl_3", .id = CTL_3,
> .base = 0x18000, .len = 0x290,
> - .features = CTL_SM8550_MASK,
> + .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> }, {
> .name = "ctl_4", .id = CTL_4,
> .base = 0x19000, .len = 0x290,
> - .features = CTL_SM8550_MASK,
> + .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
> }, {
> .name = "ctl_5", .id = CTL_5,
> .base = 0x1a000, .len = 0x290,
> - .features = CTL_SM8550_MASK,
> + .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
> index 960c68f33074e0cec0f33aa7d4f8f3b4cc69bac5..b21aab274703ac1f38698bee82d5d28b0fb6a0d0 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
> @@ -31,32 +31,32 @@ static const struct dpu_ctl_cfg sar2130p_ctl[] = {
> {
> .name = "ctl_0", .id = CTL_0,
> .base = 0x15000, .len = 0x290,
> - .features = CTL_SM8550_MASK,
> + .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> }, {
> .name = "ctl_1", .id = CTL_1,
> .base = 0x16000, .len = 0x290,
> - .features = CTL_SM8550_MASK,
> + .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> }, {
> .name = "ctl_2", .id = CTL_2,
> .base = 0x17000, .len = 0x290,
> - .features = CTL_SM8550_MASK,
> + .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> }, {
> .name = "ctl_3", .id = CTL_3,
> .base = 0x18000, .len = 0x290,
> - .features = CTL_SM8550_MASK,
> + .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> }, {
> .name = "ctl_4", .id = CTL_4,
> .base = 0x19000, .len = 0x290,
> - .features = CTL_SM8550_MASK,
> + .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
> }, {
> .name = "ctl_5", .id = CTL_5,
> .base = 0x1a000, .len = 0x290,
> - .features = CTL_SM8550_MASK,
> + .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
> index 85dcf577b844995fe11322ec506885bc4a85e33c..d7e5f4dd3bccab125b0a42f67eddf194359dc761 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
> @@ -30,32 +30,32 @@ static const struct dpu_ctl_cfg x1e80100_ctl[] = {
> {
> .name = "ctl_0", .id = CTL_0,
> .base = 0x15000, .len = 0x290,
> - .features = CTL_SM8550_MASK,
> + .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> }, {
> .name = "ctl_1", .id = CTL_1,
> .base = 0x16000, .len = 0x290,
> - .features = CTL_SM8550_MASK,
> + .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> }, {
> .name = "ctl_2", .id = CTL_2,
> .base = 0x17000, .len = 0x290,
> - .features = CTL_SM8550_MASK,
> + .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> }, {
> .name = "ctl_3", .id = CTL_3,
> .base = 0x18000, .len = 0x290,
> - .features = CTL_SM8550_MASK,
> + .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> }, {
> .name = "ctl_4", .id = CTL_4,
> .base = 0x19000, .len = 0x290,
> - .features = CTL_SM8550_MASK,
> + .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
> }, {
> .name = "ctl_5", .id = CTL_5,
> .base = 0x1a000, .len = 0x290,
> - .features = CTL_SM8550_MASK,
> + .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index 00e6f3e56ed1f9af581bad9845971fad315ef83c..a162c4f9ebd79d3ba16b50117ee7462afdbbf3d4 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -110,9 +110,6 @@
> BIT(DPU_CTL_VM_CFG) | \
> BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH))
>
> -#define CTL_SM8550_MASK \
> - (CTL_SC7280_MASK | BIT(DPU_CTL_HAS_LAYER_EXT4))
> -
> #define INTF_SC7180_MASK \
> (BIT(DPU_INTF_INPUT_CTRL) | \
> BIT(DPU_INTF_STATUS_SUPPORTED) | \
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index 01dd6e65f777f3b92f41e2ccb08f279650d50425..3d6c2db395b65b89845cb7281195ca5ca16c22e6 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -134,7 +134,6 @@ enum {
> * @DPU_CTL_SPLIT_DISPLAY: CTL supports video mode split display
> * @DPU_CTL_FETCH_ACTIVE: Active CTL for fetch HW (SSPPs)
> * @DPU_CTL_VM_CFG: CTL config to support multiple VMs
> - * @DPU_CTL_HAS_LAYER_EXT4: CTL has the CTL_LAYER_EXT4 register
> * @DPU_CTL_DSPP_BLOCK_FLUSH: CTL config to support dspp sub-block flush
> * @DPU_CTL_MAX
> */
> @@ -143,7 +142,6 @@ enum {
> DPU_CTL_ACTIVE_CFG,
> DPU_CTL_FETCH_ACTIVE,
> DPU_CTL_VM_CFG,
> - DPU_CTL_HAS_LAYER_EXT4,
> DPU_CTL_DSPP_SUB_BLOCK_FLUSH,
> DPU_CTL_MAX
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> index d58a0f1e8edb524ff3f21ff8c96688dd2ae49541..58bdd4d33b37d83f30931f09fdf80bef41e1f0fe 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> @@ -555,7 +555,7 @@ static void dpu_hw_ctl_setup_blendstage(struct dpu_hw_ctl *ctx,
> DPU_REG_WRITE(c, CTL_LAYER_EXT(lm), mixercfg[1]);
> DPU_REG_WRITE(c, CTL_LAYER_EXT2(lm), mixercfg[2]);
> DPU_REG_WRITE(c, CTL_LAYER_EXT3(lm), mixercfg[3]);
> - if ((test_bit(DPU_CTL_HAS_LAYER_EXT4, &ctx->caps->features)))
> + if (ctx->mdss_ver->core_major_ver >= 9)
> DPU_REG_WRITE(c, CTL_LAYER_EXT4(lm), mixercfg[4]);
> }
>
> @@ -743,12 +743,14 @@ static void dpu_hw_ctl_set_active_fetch_pipes(struct dpu_hw_ctl *ctx,
> * @dev: Corresponding device for devres management
> * @cfg: ctl_path catalog entry for which driver object is required
> * @addr: mapped register io address of MDP
> + * @mdss_ver: dpu core's major and minor versions
> * @mixer_count: Number of mixers in @mixer
> * @mixer: Pointer to an array of Layer Mixers defined in the catalog
> */
> struct dpu_hw_ctl *dpu_hw_ctl_init(struct drm_device *dev,
> const struct dpu_ctl_cfg *cfg,
> void __iomem *addr,
> + const struct dpu_mdss_version *mdss_ver,
> u32 mixer_count,
> const struct dpu_lm_cfg *mixer)
> {
> @@ -762,6 +764,7 @@ struct dpu_hw_ctl *dpu_hw_ctl_init(struct drm_device *dev,
> c->hw.log_mask = DPU_DBG_MASK_CTL;
>
> c->caps = cfg;
> + c->mdss_ver = mdss_ver;
>
> if (c->caps->features & BIT(DPU_CTL_ACTIVE_CFG)) {
> c->ops.trigger_flush = dpu_hw_ctl_trigger_flush_v1;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
> index feb09590bc8fc5c77c2c673fd888c28281a98b5a..9cd9959682c21cc1c6d8d14b8fb377deb33cc10d 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
> @@ -274,6 +274,7 @@ struct dpu_hw_ctl_ops {
> * @pending_cwb_flush_mask: pending CWB flush
> * @pending_dsc_flush_mask: pending DSC flush
> * @pending_cdm_flush_mask: pending CDM flush
> + * @mdss_ver: MDSS revision information
> * @ops: operation list
> */
> struct dpu_hw_ctl {
> @@ -295,6 +296,8 @@ struct dpu_hw_ctl {
> u32 pending_dsc_flush_mask;
> u32 pending_cdm_flush_mask;
>
> + const struct dpu_mdss_version *mdss_ver;
> +
> /* ops */
> struct dpu_hw_ctl_ops ops;
> };
> @@ -312,6 +315,7 @@ static inline struct dpu_hw_ctl *to_dpu_hw_ctl(struct dpu_hw_blk *hw)
> struct dpu_hw_ctl *dpu_hw_ctl_init(struct drm_device *dev,
> const struct dpu_ctl_cfg *cfg,
> void __iomem *addr,
> + const struct dpu_mdss_version *mdss_ver,
> u32 mixer_count,
> const struct dpu_lm_cfg *mixer);
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> index 2e296f79cba1437470eeb30900a650f6f4e334b6..d728e275ac427f7849dad4f4a055c56840ca2d23 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> @@ -142,7 +142,7 @@ int dpu_rm_init(struct drm_device *dev,
> struct dpu_hw_ctl *hw;
> const struct dpu_ctl_cfg *ctl = &cat->ctl[i];
>
> - hw = dpu_hw_ctl_init(dev, ctl, mmio, cat->mixer_count, cat->mixer);
> + hw = dpu_hw_ctl_init(dev, ctl, mmio, cat->mdss_ver, cat->mixer_count, cat->mixer);
> if (IS_ERR(hw)) {
> rc = PTR_ERR(hw);
> DPU_ERROR("failed ctl object creation: err %d\n", rc);
>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH v4 09/30] drm/msm/dpu: get rid of DPU_CTL_ACTIVE_CFG
2025-05-19 16:04 [PATCH v4 00/30] drm/msm/dpu: rework HW block feature handling Dmitry Baryshkov
` (7 preceding siblings ...)
2025-05-19 16:04 ` [PATCH v4 08/30] drm/msm/dpu: get rid of DPU_CTL_HAS_LAYER_EXT4 Dmitry Baryshkov
@ 2025-05-19 16:04 ` Dmitry Baryshkov
2025-05-20 7:57 ` neil.armstrong
2025-05-19 16:04 ` [PATCH v4 10/30] drm/msm/dpu: get rid of DPU_CTL_FETCH_ACTIVE Dmitry Baryshkov
` (20 subsequent siblings)
29 siblings, 1 reply; 64+ messages in thread
From: Dmitry Baryshkov @ 2025-05-19 16:04 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Sean Paul, Marijn Suijten, David Airlie,
Simona Vetter, Vinod Koul, Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel,
Dmitry Baryshkov
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Continue migration to the MDSS-revision based checks and replace
DPU_CTL_ACTIVE_CFG feature bit with the core_major_ver >= 5 check.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 6 ------
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 6 ------
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h | 6 ------
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h | 6 ------
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 6 ------
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 6 ------
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 3 ---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 4 ----
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 7 ++-----
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 2 +-
17 files changed, 6 insertions(+), 57 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
index b2ee5ee01870507d9f01020443c30dc573414c72..6c8ef23099a8212f33780d27a76991e9955a9bc3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
@@ -41,32 +41,26 @@ static const struct dpu_ctl_cfg sm8150_ctl[] = {
{
.name = "ctl_0", .id = CTL_0,
.base = 0x1000, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
}, {
.name = "ctl_1", .id = CTL_1,
.base = 0x1200, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
}, {
.name = "ctl_2", .id = CTL_2,
.base = 0x1400, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
}, {
.name = "ctl_3", .id = CTL_3,
.base = 0x1600, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
}, {
.name = "ctl_4", .id = CTL_4,
.base = 0x1800, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
}, {
.name = "ctl_5", .id = CTL_5,
.base = 0x1a00, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
index 6db04c668a87a9f7baea01a9ea2a0f1bbb1212bf..37d18803af4b850c40ab855b1f13db96f3ee96ea 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
@@ -41,32 +41,26 @@ static const struct dpu_ctl_cfg sc8180x_ctl[] = {
{
.name = "ctl_0", .id = CTL_0,
.base = 0x1000, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
}, {
.name = "ctl_1", .id = CTL_1,
.base = 0x1200, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
}, {
.name = "ctl_2", .id = CTL_2,
.base = 0x1400, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
}, {
.name = "ctl_3", .id = CTL_3,
.base = 0x1600, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
}, {
.name = "ctl_4", .id = CTL_4,
.base = 0x1800, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
}, {
.name = "ctl_5", .id = CTL_5,
.base = 0x1a00, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
index 6f61ce85c536e36b65b98ba4740711cb495a7c9a..41b43fb258508f1a5f285c88a3c1dc2f5f271cd0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
@@ -38,32 +38,26 @@ static const struct dpu_ctl_cfg sm7150_ctl[] = {
{
.name = "ctl_0", .id = CTL_0,
.base = 0x1000, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
}, {
.name = "ctl_1", .id = CTL_1,
.base = 0x1200, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
}, {
.name = "ctl_2", .id = CTL_2,
.base = 0x1400, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
}, {
.name = "ctl_3", .id = CTL_3,
.base = 0x1600, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
}, {
.name = "ctl_4", .id = CTL_4,
.base = 0x1800, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
}, {
.name = "ctl_5", .id = CTL_5,
.base = 0x1a00, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
index dc6d8fd05c2e3afbe5182b1ae8dd9fea8b6543e5..d44db988a6e2f443803a422846f817779d382b2a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
@@ -35,32 +35,26 @@ static const struct dpu_ctl_cfg sm6150_ctl[] = {
{
.name = "ctl_0", .id = CTL_0,
.base = 0x1000, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
}, {
.name = "ctl_1", .id = CTL_1,
.base = 0x1200, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
}, {
.name = "ctl_2", .id = CTL_2,
.base = 0x1400, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
}, {
.name = "ctl_3", .id = CTL_3,
.base = 0x1600, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
}, {
.name = "ctl_4", .id = CTL_4,
.base = 0x1800, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
}, {
.name = "ctl_5", .id = CTL_5,
.base = 0x1a00, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
index 192e90b570dbf8f5c3c24f572443e111f6cf3db2..6e571480c4a44b4f4663574c31270657b9a06a7a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
@@ -35,32 +35,26 @@ static const struct dpu_ctl_cfg sm6125_ctl[] = {
{
.name = "ctl_0", .id = CTL_0,
.base = 0x1000, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
}, {
.name = "ctl_1", .id = CTL_1,
.base = 0x1200, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
}, {
.name = "ctl_2", .id = CTL_2,
.base = 0x1400, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
}, {
.name = "ctl_3", .id = CTL_3,
.base = 0x1600, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
}, {
.name = "ctl_4", .id = CTL_4,
.base = 0x1800, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
}, {
.name = "ctl_5", .id = CTL_5,
.base = 0x1a00, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
index bdd92b5a61eabc6a1d5e0bfe740ed6d9f1e8e94f..6f9dc261e667fca3e94ec24e00d45f9af46e401e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
@@ -39,32 +39,26 @@ static const struct dpu_ctl_cfg sm8250_ctl[] = {
{
.name = "ctl_0", .id = CTL_0,
.base = 0x1000, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
}, {
.name = "ctl_1", .id = CTL_1,
.base = 0x1200, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
}, {
.name = "ctl_2", .id = CTL_2,
.base = 0x1400, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
}, {
.name = "ctl_3", .id = CTL_3,
.base = 0x1600, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
}, {
.name = "ctl_4", .id = CTL_4,
.base = 0x1800, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
}, {
.name = "ctl_5", .id = CTL_5,
.base = 0x1a00, .len = 0x1e0,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
index ce2ec6af5f53e2177009ca8826ca510fa08c03c7..373c7d605a04a1fc72f45e993ec176e8f5e015fe 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
@@ -32,17 +32,14 @@ static const struct dpu_ctl_cfg sc7180_ctl[] = {
{
.name = "ctl_0", .id = CTL_0,
.base = 0x1000, .len = 0x1dc,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
}, {
.name = "ctl_1", .id = CTL_1,
.base = 0x1200, .len = 0x1dc,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
}, {
.name = "ctl_2", .id = CTL_2,
.base = 0x1400, .len = 0x1dc,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
index 986179b53f8b59200d10f5159cac630732dc7196..1cf9f99d0542cf7037d2a9672d51ca7c437c364e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
@@ -29,7 +29,6 @@ static const struct dpu_ctl_cfg sm6115_ctl[] = {
{
.name = "ctl_0", .id = CTL_0,
.base = 0x1000, .len = 0x1dc,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
index c2321a4a7d3894d85062d083b45402950122007b..a3db71676f468526ea129c4b8465fb2c47885162 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
@@ -35,22 +35,18 @@ static const struct dpu_ctl_cfg sm6350_ctl[] = {
{
.name = "ctl_0", .id = CTL_0,
.base = 0x1000, .len = 0x1dc,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
}, {
.name = "ctl_1", .id = CTL_1,
.base = 0x1200, .len = 0x1dc,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
}, {
.name = "ctl_2", .id = CTL_2,
.base = 0x1400, .len = 0x1dc,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
}, {
.name = "ctl_3", .id = CTL_3,
.base = 0x1600, .len = 0x1dc,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
index c3dd2383bd5f32926b50d98c937da25ed59d7cb3..719cfaa98ab9e735d9255d9a5f1a4275739b4b1d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
@@ -29,7 +29,6 @@ static const struct dpu_ctl_cfg qcm2290_ctl[] = {
{
.name = "ctl_0", .id = CTL_0,
.base = 0x1000, .len = 0x1dc,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
index abeaa2b8e06fdf6ce5cec2c1a4fd025a342f5a2f..04cdda85e6828a83e99d146ee9d9f809f1acc007 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
@@ -30,7 +30,6 @@ static const struct dpu_ctl_cfg sm6375_ctl[] = {
{
.name = "ctl_0", .id = CTL_0,
.base = 0x1000, .len = 0x1dc,
- .features = BIT(DPU_CTL_ACTIVE_CFG),
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
index a0ba55ab3c894c200225fe48ec6214ae4135d059..25ba5d9bfff2b3f7a5054ae26511d05917f72d8b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
@@ -69,7 +69,7 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg(
ctl->ops.setup_intf_cfg(ctl, &intf_cfg);
/* setup which pp blk will connect to this intf */
- if (test_bit(DPU_CTL_ACTIVE_CFG, &ctl->caps->features) && phys_enc->hw_intf->ops.bind_pingpong_blk)
+ if (phys_enc->hw_intf->ops.bind_pingpong_blk)
phys_enc->hw_intf->ops.bind_pingpong_blk(
phys_enc->hw_intf,
phys_enc->hw_pp->idx);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index d35d15b60260037c5c0c369cb061e7759243b6fd..e12bca8a26ec98565a96919b1c43f7fa2ea8a0df 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -373,7 +373,7 @@ static void dpu_encoder_phys_vid_underrun_irq(void *arg)
static bool dpu_encoder_phys_vid_needs_single_flush(
struct dpu_encoder_phys *phys_enc)
{
- return !(phys_enc->hw_ctl->caps->features & BIT(DPU_CTL_ACTIVE_CFG)) &&
+ return !(phys_enc->dpu_kms->catalog->mdss_ver->core_major_ver >= 5) &&
phys_enc->split_role != ENC_ROLE_SOLO;
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
index 849fea580a4ca55fc4a742c6b6dee7dfcdd788e4..c8f3516ae4faa709e3eda4c0efb050ca18b675e4 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
@@ -218,7 +218,6 @@ static void dpu_encoder_phys_wb_setup_fb(struct dpu_encoder_phys *phys_enc,
static void dpu_encoder_phys_wb_setup_ctl(struct dpu_encoder_phys *phys_enc)
{
struct dpu_hw_wb *hw_wb;
- struct dpu_hw_ctl *ctl;
struct dpu_hw_cdm *hw_cdm;
if (!phys_enc) {
@@ -227,10 +226,9 @@ static void dpu_encoder_phys_wb_setup_ctl(struct dpu_encoder_phys *phys_enc)
}
hw_wb = phys_enc->hw_wb;
- ctl = phys_enc->hw_ctl;
hw_cdm = phys_enc->hw_cdm;
- if (test_bit(DPU_CTL_ACTIVE_CFG, &ctl->caps->features) &&
+ if (phys_enc->dpu_kms->catalog->mdss_ver->core_major_ver >= 5 &&
(phys_enc->hw_ctl &&
phys_enc->hw_ctl->ops.setup_intf_cfg)) {
struct dpu_hw_intf_cfg intf_cfg = {0};
@@ -534,7 +532,6 @@ static void dpu_encoder_phys_wb_enable(struct dpu_encoder_phys *phys_enc)
static void dpu_encoder_phys_wb_disable(struct dpu_encoder_phys *phys_enc)
{
struct dpu_hw_wb *hw_wb = phys_enc->hw_wb;
- struct dpu_hw_ctl *hw_ctl = phys_enc->hw_ctl;
DPU_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0);
@@ -556,7 +553,7 @@ static void dpu_encoder_phys_wb_disable(struct dpu_encoder_phys *phys_enc)
* WB support is added to those targets will need to add
* the legacy teardown sequence as well.
*/
- if (hw_ctl->caps->features & BIT(DPU_CTL_ACTIVE_CFG))
+ if (phys_enc->dpu_kms->catalog->mdss_ver->core_major_ver >= 5)
dpu_encoder_helper_phys_cleanup(phys_enc);
phys_enc->enable_state = DPU_ENC_DISABLED;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index a162c4f9ebd79d3ba16b50117ee7462afdbbf3d4..0863e5cfb3283ed32f61ddd4483220742df8633d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -105,8 +105,7 @@
(BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_DSC))
#define CTL_SC7280_MASK \
- (BIT(DPU_CTL_ACTIVE_CFG) | \
- BIT(DPU_CTL_FETCH_ACTIVE) | \
+ (BIT(DPU_CTL_FETCH_ACTIVE) | \
BIT(DPU_CTL_VM_CFG) | \
BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH))
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 3d6c2db395b65b89845cb7281195ca5ca16c22e6..9981d090b689b46bbc378d1965b0efd1df0efa8b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -139,7 +139,6 @@ enum {
*/
enum {
DPU_CTL_SPLIT_DISPLAY = 0x1,
- DPU_CTL_ACTIVE_CFG,
DPU_CTL_FETCH_ACTIVE,
DPU_CTL_VM_CFG,
DPU_CTL_DSPP_SUB_BLOCK_FLUSH,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index 58bdd4d33b37d83f30931f09fdf80bef41e1f0fe..2dfb7db371a3915f663cf134e4dd62f92224185b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -766,7 +766,7 @@ struct dpu_hw_ctl *dpu_hw_ctl_init(struct drm_device *dev,
c->caps = cfg;
c->mdss_ver = mdss_ver;
- if (c->caps->features & BIT(DPU_CTL_ACTIVE_CFG)) {
+ if (mdss_ver->core_major_ver >= 5) {
c->ops.trigger_flush = dpu_hw_ctl_trigger_flush_v1;
c->ops.setup_intf_cfg = dpu_hw_ctl_intf_cfg_v1;
c->ops.reset_intf_cfg = dpu_hw_ctl_reset_intf_cfg_v1;
--
2.39.5
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH v4 09/30] drm/msm/dpu: get rid of DPU_CTL_ACTIVE_CFG
2025-05-19 16:04 ` [PATCH v4 09/30] drm/msm/dpu: get rid of DPU_CTL_ACTIVE_CFG Dmitry Baryshkov
@ 2025-05-20 7:57 ` neil.armstrong
2025-05-20 21:29 ` Dmitry Baryshkov
0 siblings, 1 reply; 64+ messages in thread
From: neil.armstrong @ 2025-05-20 7:57 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Abhinav Kumar, Sean Paul,
Marijn Suijten, David Airlie, Simona Vetter, Vinod Koul,
Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel,
Dmitry Baryshkov
On 19/05/2025 18:04, Dmitry Baryshkov wrote:
> From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>
> Continue migration to the MDSS-revision based checks and replace
> DPU_CTL_ACTIVE_CFG feature bit with the core_major_ver >= 5 check.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 6 ------
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 6 ------
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h | 6 ------
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h | 6 ------
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 6 ------
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 6 ------
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 3 ---
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 1 -
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 4 ----
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 1 -
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 1 -
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 7 ++-----
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +--
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 -
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 2 +-
> 17 files changed, 6 insertions(+), 57 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> index b2ee5ee01870507d9f01020443c30dc573414c72..6c8ef23099a8212f33780d27a76991e9955a9bc3 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> @@ -41,32 +41,26 @@ static const struct dpu_ctl_cfg sm8150_ctl[] = {
> {
> .name = "ctl_0", .id = CTL_0,
> .base = 0x1000, .len = 0x1e0,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> }, {
> .name = "ctl_1", .id = CTL_1,
> .base = 0x1200, .len = 0x1e0,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> }, {
> .name = "ctl_2", .id = CTL_2,
> .base = 0x1400, .len = 0x1e0,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> }, {
> .name = "ctl_3", .id = CTL_3,
> .base = 0x1600, .len = 0x1e0,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> }, {
> .name = "ctl_4", .id = CTL_4,
> .base = 0x1800, .len = 0x1e0,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
> }, {
> .name = "ctl_5", .id = CTL_5,
> .base = 0x1a00, .len = 0x1e0,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> index 6db04c668a87a9f7baea01a9ea2a0f1bbb1212bf..37d18803af4b850c40ab855b1f13db96f3ee96ea 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> @@ -41,32 +41,26 @@ static const struct dpu_ctl_cfg sc8180x_ctl[] = {
> {
> .name = "ctl_0", .id = CTL_0,
> .base = 0x1000, .len = 0x1e0,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> }, {
> .name = "ctl_1", .id = CTL_1,
> .base = 0x1200, .len = 0x1e0,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> }, {
> .name = "ctl_2", .id = CTL_2,
> .base = 0x1400, .len = 0x1e0,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> }, {
> .name = "ctl_3", .id = CTL_3,
> .base = 0x1600, .len = 0x1e0,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> }, {
> .name = "ctl_4", .id = CTL_4,
> .base = 0x1800, .len = 0x1e0,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
> }, {
> .name = "ctl_5", .id = CTL_5,
> .base = 0x1a00, .len = 0x1e0,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
> index 6f61ce85c536e36b65b98ba4740711cb495a7c9a..41b43fb258508f1a5f285c88a3c1dc2f5f271cd0 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
> @@ -38,32 +38,26 @@ static const struct dpu_ctl_cfg sm7150_ctl[] = {
> {
> .name = "ctl_0", .id = CTL_0,
> .base = 0x1000, .len = 0x1e0,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> }, {
> .name = "ctl_1", .id = CTL_1,
> .base = 0x1200, .len = 0x1e0,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> }, {
> .name = "ctl_2", .id = CTL_2,
> .base = 0x1400, .len = 0x1e0,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> }, {
> .name = "ctl_3", .id = CTL_3,
> .base = 0x1600, .len = 0x1e0,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> }, {
> .name = "ctl_4", .id = CTL_4,
> .base = 0x1800, .len = 0x1e0,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
> }, {
> .name = "ctl_5", .id = CTL_5,
> .base = 0x1a00, .len = 0x1e0,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
> index dc6d8fd05c2e3afbe5182b1ae8dd9fea8b6543e5..d44db988a6e2f443803a422846f817779d382b2a 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
> @@ -35,32 +35,26 @@ static const struct dpu_ctl_cfg sm6150_ctl[] = {
> {
> .name = "ctl_0", .id = CTL_0,
> .base = 0x1000, .len = 0x1e0,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> }, {
> .name = "ctl_1", .id = CTL_1,
> .base = 0x1200, .len = 0x1e0,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> }, {
> .name = "ctl_2", .id = CTL_2,
> .base = 0x1400, .len = 0x1e0,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> }, {
> .name = "ctl_3", .id = CTL_3,
> .base = 0x1600, .len = 0x1e0,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> }, {
> .name = "ctl_4", .id = CTL_4,
> .base = 0x1800, .len = 0x1e0,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
> }, {
> .name = "ctl_5", .id = CTL_5,
> .base = 0x1a00, .len = 0x1e0,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
> index 192e90b570dbf8f5c3c24f572443e111f6cf3db2..6e571480c4a44b4f4663574c31270657b9a06a7a 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
> @@ -35,32 +35,26 @@ static const struct dpu_ctl_cfg sm6125_ctl[] = {
> {
> .name = "ctl_0", .id = CTL_0,
> .base = 0x1000, .len = 0x1e0,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> }, {
> .name = "ctl_1", .id = CTL_1,
> .base = 0x1200, .len = 0x1e0,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> }, {
> .name = "ctl_2", .id = CTL_2,
> .base = 0x1400, .len = 0x1e0,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> }, {
> .name = "ctl_3", .id = CTL_3,
> .base = 0x1600, .len = 0x1e0,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> }, {
> .name = "ctl_4", .id = CTL_4,
> .base = 0x1800, .len = 0x1e0,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
> }, {
> .name = "ctl_5", .id = CTL_5,
> .base = 0x1a00, .len = 0x1e0,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> index bdd92b5a61eabc6a1d5e0bfe740ed6d9f1e8e94f..6f9dc261e667fca3e94ec24e00d45f9af46e401e 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> @@ -39,32 +39,26 @@ static const struct dpu_ctl_cfg sm8250_ctl[] = {
> {
> .name = "ctl_0", .id = CTL_0,
> .base = 0x1000, .len = 0x1e0,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> }, {
> .name = "ctl_1", .id = CTL_1,
> .base = 0x1200, .len = 0x1e0,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> }, {
> .name = "ctl_2", .id = CTL_2,
> .base = 0x1400, .len = 0x1e0,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> }, {
> .name = "ctl_3", .id = CTL_3,
> .base = 0x1600, .len = 0x1e0,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> }, {
> .name = "ctl_4", .id = CTL_4,
> .base = 0x1800, .len = 0x1e0,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
> }, {
> .name = "ctl_5", .id = CTL_5,
> .base = 0x1a00, .len = 0x1e0,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> index ce2ec6af5f53e2177009ca8826ca510fa08c03c7..373c7d605a04a1fc72f45e993ec176e8f5e015fe 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> @@ -32,17 +32,14 @@ static const struct dpu_ctl_cfg sc7180_ctl[] = {
> {
> .name = "ctl_0", .id = CTL_0,
> .base = 0x1000, .len = 0x1dc,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> }, {
> .name = "ctl_1", .id = CTL_1,
> .base = 0x1200, .len = 0x1dc,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> }, {
> .name = "ctl_2", .id = CTL_2,
> .base = 0x1400, .len = 0x1dc,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> index 986179b53f8b59200d10f5159cac630732dc7196..1cf9f99d0542cf7037d2a9672d51ca7c437c364e 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> @@ -29,7 +29,6 @@ static const struct dpu_ctl_cfg sm6115_ctl[] = {
> {
> .name = "ctl_0", .id = CTL_0,
> .base = 0x1000, .len = 0x1dc,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> index c2321a4a7d3894d85062d083b45402950122007b..a3db71676f468526ea129c4b8465fb2c47885162 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> @@ -35,22 +35,18 @@ static const struct dpu_ctl_cfg sm6350_ctl[] = {
> {
> .name = "ctl_0", .id = CTL_0,
> .base = 0x1000, .len = 0x1dc,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> }, {
> .name = "ctl_1", .id = CTL_1,
> .base = 0x1200, .len = 0x1dc,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> }, {
> .name = "ctl_2", .id = CTL_2,
> .base = 0x1400, .len = 0x1dc,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> }, {
> .name = "ctl_3", .id = CTL_3,
> .base = 0x1600, .len = 0x1dc,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> index c3dd2383bd5f32926b50d98c937da25ed59d7cb3..719cfaa98ab9e735d9255d9a5f1a4275739b4b1d 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> @@ -29,7 +29,6 @@ static const struct dpu_ctl_cfg qcm2290_ctl[] = {
> {
> .name = "ctl_0", .id = CTL_0,
> .base = 0x1000, .len = 0x1dc,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
> index abeaa2b8e06fdf6ce5cec2c1a4fd025a342f5a2f..04cdda85e6828a83e99d146ee9d9f809f1acc007 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
> @@ -30,7 +30,6 @@ static const struct dpu_ctl_cfg sm6375_ctl[] = {
> {
> .name = "ctl_0", .id = CTL_0,
> .base = 0x1000, .len = 0x1dc,
> - .features = BIT(DPU_CTL_ACTIVE_CFG),
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
> index a0ba55ab3c894c200225fe48ec6214ae4135d059..25ba5d9bfff2b3f7a5054ae26511d05917f72d8b 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
> @@ -69,7 +69,7 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg(
> ctl->ops.setup_intf_cfg(ctl, &intf_cfg);
>
> /* setup which pp blk will connect to this intf */
> - if (test_bit(DPU_CTL_ACTIVE_CFG, &ctl->caps->features) && phys_enc->hw_intf->ops.bind_pingpong_blk)
> + if (phys_enc->hw_intf->ops.bind_pingpong_blk)
Why did you drop the version test here ?
Neil
> phys_enc->hw_intf->ops.bind_pingpong_blk(
> phys_enc->hw_intf,
> phys_enc->hw_pp->idx);
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> index d35d15b60260037c5c0c369cb061e7759243b6fd..e12bca8a26ec98565a96919b1c43f7fa2ea8a0df 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> @@ -373,7 +373,7 @@ static void dpu_encoder_phys_vid_underrun_irq(void *arg)
> static bool dpu_encoder_phys_vid_needs_single_flush(
> struct dpu_encoder_phys *phys_enc)
> {
> - return !(phys_enc->hw_ctl->caps->features & BIT(DPU_CTL_ACTIVE_CFG)) &&
> + return !(phys_enc->dpu_kms->catalog->mdss_ver->core_major_ver >= 5) &&
> phys_enc->split_role != ENC_ROLE_SOLO;
> }
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
> index 849fea580a4ca55fc4a742c6b6dee7dfcdd788e4..c8f3516ae4faa709e3eda4c0efb050ca18b675e4 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
> @@ -218,7 +218,6 @@ static void dpu_encoder_phys_wb_setup_fb(struct dpu_encoder_phys *phys_enc,
> static void dpu_encoder_phys_wb_setup_ctl(struct dpu_encoder_phys *phys_enc)
> {
> struct dpu_hw_wb *hw_wb;
> - struct dpu_hw_ctl *ctl;
> struct dpu_hw_cdm *hw_cdm;
>
> if (!phys_enc) {
> @@ -227,10 +226,9 @@ static void dpu_encoder_phys_wb_setup_ctl(struct dpu_encoder_phys *phys_enc)
> }
>
> hw_wb = phys_enc->hw_wb;
> - ctl = phys_enc->hw_ctl;
> hw_cdm = phys_enc->hw_cdm;
>
> - if (test_bit(DPU_CTL_ACTIVE_CFG, &ctl->caps->features) &&
> + if (phys_enc->dpu_kms->catalog->mdss_ver->core_major_ver >= 5 &&
> (phys_enc->hw_ctl &&
> phys_enc->hw_ctl->ops.setup_intf_cfg)) {
> struct dpu_hw_intf_cfg intf_cfg = {0};
> @@ -534,7 +532,6 @@ static void dpu_encoder_phys_wb_enable(struct dpu_encoder_phys *phys_enc)
> static void dpu_encoder_phys_wb_disable(struct dpu_encoder_phys *phys_enc)
> {
> struct dpu_hw_wb *hw_wb = phys_enc->hw_wb;
> - struct dpu_hw_ctl *hw_ctl = phys_enc->hw_ctl;
>
> DPU_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0);
>
> @@ -556,7 +553,7 @@ static void dpu_encoder_phys_wb_disable(struct dpu_encoder_phys *phys_enc)
> * WB support is added to those targets will need to add
> * the legacy teardown sequence as well.
> */
> - if (hw_ctl->caps->features & BIT(DPU_CTL_ACTIVE_CFG))
> + if (phys_enc->dpu_kms->catalog->mdss_ver->core_major_ver >= 5)
> dpu_encoder_helper_phys_cleanup(phys_enc);
>
> phys_enc->enable_state = DPU_ENC_DISABLED;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index a162c4f9ebd79d3ba16b50117ee7462afdbbf3d4..0863e5cfb3283ed32f61ddd4483220742df8633d 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -105,8 +105,7 @@
> (BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_DSC))
>
> #define CTL_SC7280_MASK \
> - (BIT(DPU_CTL_ACTIVE_CFG) | \
> - BIT(DPU_CTL_FETCH_ACTIVE) | \
> + (BIT(DPU_CTL_FETCH_ACTIVE) | \
> BIT(DPU_CTL_VM_CFG) | \
> BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH))
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index 3d6c2db395b65b89845cb7281195ca5ca16c22e6..9981d090b689b46bbc378d1965b0efd1df0efa8b 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -139,7 +139,6 @@ enum {
> */
> enum {
> DPU_CTL_SPLIT_DISPLAY = 0x1,
> - DPU_CTL_ACTIVE_CFG,
> DPU_CTL_FETCH_ACTIVE,
> DPU_CTL_VM_CFG,
> DPU_CTL_DSPP_SUB_BLOCK_FLUSH,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> index 58bdd4d33b37d83f30931f09fdf80bef41e1f0fe..2dfb7db371a3915f663cf134e4dd62f92224185b 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> @@ -766,7 +766,7 @@ struct dpu_hw_ctl *dpu_hw_ctl_init(struct drm_device *dev,
> c->caps = cfg;
> c->mdss_ver = mdss_ver;
>
> - if (c->caps->features & BIT(DPU_CTL_ACTIVE_CFG)) {
> + if (mdss_ver->core_major_ver >= 5) {
> c->ops.trigger_flush = dpu_hw_ctl_trigger_flush_v1;
> c->ops.setup_intf_cfg = dpu_hw_ctl_intf_cfg_v1;
> c->ops.reset_intf_cfg = dpu_hw_ctl_reset_intf_cfg_v1;
>
^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [PATCH v4 09/30] drm/msm/dpu: get rid of DPU_CTL_ACTIVE_CFG
2025-05-20 7:57 ` neil.armstrong
@ 2025-05-20 21:29 ` Dmitry Baryshkov
2025-05-21 12:51 ` Neil Armstrong
0 siblings, 1 reply; 64+ messages in thread
From: Dmitry Baryshkov @ 2025-05-20 21:29 UTC (permalink / raw)
To: Neil Armstrong
Cc: Rob Clark, Abhinav Kumar, Sean Paul, Marijn Suijten, David Airlie,
Simona Vetter, Vinod Koul, Konrad Dybcio, linux-arm-msm,
dri-devel, freedreno, linux-kernel
On Tue, May 20, 2025 at 09:57:38AM +0200, neil.armstrong@linaro.org wrote:
> On 19/05/2025 18:04, Dmitry Baryshkov wrote:
> > From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> >
> > Continue migration to the MDSS-revision based checks and replace
> > DPU_CTL_ACTIVE_CFG feature bit with the core_major_ver >= 5 check.
> >
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> > ---
> > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 6 ------
> > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 6 ------
> > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h | 6 ------
> > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h | 6 ------
> > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 6 ------
> > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 6 ------
> > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 3 ---
> > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 1 -
> > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 4 ----
> > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 1 -
> > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 1 -
> > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 2 +-
> > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 2 +-
> > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 7 ++-----
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +--
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 -
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 2 +-
> > 17 files changed, 6 insertions(+), 57 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
> > index a0ba55ab3c894c200225fe48ec6214ae4135d059..25ba5d9bfff2b3f7a5054ae26511d05917f72d8b 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
> > @@ -69,7 +69,7 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg(
> > ctl->ops.setup_intf_cfg(ctl, &intf_cfg);
> > /* setup which pp blk will connect to this intf */
> > - if (test_bit(DPU_CTL_ACTIVE_CFG, &ctl->caps->features) && phys_enc->hw_intf->ops.bind_pingpong_blk)
> > + if (phys_enc->hw_intf->ops.bind_pingpong_blk)
>
> Why did you drop the version test here ?
bind_pingpong_blk is only available since DPU 5.x, the same set of
hardware as the DPU having DPU_CTL_ACTIVE_CFG.
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v4 09/30] drm/msm/dpu: get rid of DPU_CTL_ACTIVE_CFG
2025-05-20 21:29 ` Dmitry Baryshkov
@ 2025-05-21 12:51 ` Neil Armstrong
2025-05-22 18:53 ` Dmitry Baryshkov
0 siblings, 1 reply; 64+ messages in thread
From: Neil Armstrong @ 2025-05-21 12:51 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Rob Clark, Abhinav Kumar, Sean Paul, Marijn Suijten, David Airlie,
Simona Vetter, Vinod Koul, Konrad Dybcio, linux-arm-msm,
dri-devel, freedreno, linux-kernel
On 20/05/2025 23:29, Dmitry Baryshkov wrote:
> On Tue, May 20, 2025 at 09:57:38AM +0200, neil.armstrong@linaro.org wrote:
>> On 19/05/2025 18:04, Dmitry Baryshkov wrote:
>>> From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>>
>>> Continue migration to the MDSS-revision based checks and replace
>>> DPU_CTL_ACTIVE_CFG feature bit with the core_major_ver >= 5 check.
>>>
>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
>>> ---
>>> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 6 ------
>>> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 6 ------
>>> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h | 6 ------
>>> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h | 6 ------
>>> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 6 ------
>>> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 6 ------
>>> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 3 ---
>>> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 1 -
>>> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 4 ----
>>> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 1 -
>>> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 1 -
>>> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 2 +-
>>> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 2 +-
>>> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 7 ++-----
>>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +--
>>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 -
>>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 2 +-
>>> 17 files changed, 6 insertions(+), 57 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
>>> index a0ba55ab3c894c200225fe48ec6214ae4135d059..25ba5d9bfff2b3f7a5054ae26511d05917f72d8b 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
>>> @@ -69,7 +69,7 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg(
>>> ctl->ops.setup_intf_cfg(ctl, &intf_cfg);
>>> /* setup which pp blk will connect to this intf */
>>> - if (test_bit(DPU_CTL_ACTIVE_CFG, &ctl->caps->features) && phys_enc->hw_intf->ops.bind_pingpong_blk)
>>> + if (phys_enc->hw_intf->ops.bind_pingpong_blk)
>>
>> Why did you drop the version test here ?
>
> bind_pingpong_blk is only available since DPU 5.x, the same set of
> hardware as the DPU having DPU_CTL_ACTIVE_CFG.
>
I think it deserves a comment in the code or the commit msg.
Neil
^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v4 09/30] drm/msm/dpu: get rid of DPU_CTL_ACTIVE_CFG
2025-05-21 12:51 ` Neil Armstrong
@ 2025-05-22 18:53 ` Dmitry Baryshkov
0 siblings, 0 replies; 64+ messages in thread
From: Dmitry Baryshkov @ 2025-05-22 18:53 UTC (permalink / raw)
To: Neil Armstrong
Cc: Rob Clark, Abhinav Kumar, Sean Paul, Marijn Suijten, David Airlie,
Simona Vetter, Vinod Koul, Konrad Dybcio, linux-arm-msm,
dri-devel, freedreno, linux-kernel
On Wed, May 21, 2025 at 02:51:22PM +0200, Neil Armstrong wrote:
> On 20/05/2025 23:29, Dmitry Baryshkov wrote:
> > On Tue, May 20, 2025 at 09:57:38AM +0200, neil.armstrong@linaro.org wrote:
> > > On 19/05/2025 18:04, Dmitry Baryshkov wrote:
> > > > From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > > >
> > > > Continue migration to the MDSS-revision based checks and replace
> > > > DPU_CTL_ACTIVE_CFG feature bit with the core_major_ver >= 5 check.
> > > >
> > > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > > > Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
> > > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> > > > ---
> > > > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 6 ------
> > > > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 6 ------
> > > > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h | 6 ------
> > > > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h | 6 ------
> > > > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 6 ------
> > > > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 6 ------
> > > > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 3 ---
> > > > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 1 -
> > > > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 4 ----
> > > > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 1 -
> > > > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 1 -
> > > > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 2 +-
> > > > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 2 +-
> > > > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 7 ++-----
> > > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +--
> > > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 -
> > > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 2 +-
> > > > 17 files changed, 6 insertions(+), 57 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
> > > > index a0ba55ab3c894c200225fe48ec6214ae4135d059..25ba5d9bfff2b3f7a5054ae26511d05917f72d8b 100644
> > > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
> > > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
> > > > @@ -69,7 +69,7 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg(
> > > > ctl->ops.setup_intf_cfg(ctl, &intf_cfg);
> > > > /* setup which pp blk will connect to this intf */
> > > > - if (test_bit(DPU_CTL_ACTIVE_CFG, &ctl->caps->features) && phys_enc->hw_intf->ops.bind_pingpong_blk)
> > > > + if (phys_enc->hw_intf->ops.bind_pingpong_blk)
> > >
> > > Why did you drop the version test here ?
> >
> > bind_pingpong_blk is only available since DPU 5.x, the same set of
> > hardware as the DPU having DPU_CTL_ACTIVE_CFG.
> >
>
> I think it deserves a comment in the code or the commit msg.
Ack
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH v4 10/30] drm/msm/dpu: get rid of DPU_CTL_FETCH_ACTIVE
2025-05-19 16:04 [PATCH v4 00/30] drm/msm/dpu: rework HW block feature handling Dmitry Baryshkov
` (8 preceding siblings ...)
2025-05-19 16:04 ` [PATCH v4 09/30] drm/msm/dpu: get rid of DPU_CTL_ACTIVE_CFG Dmitry Baryshkov
@ 2025-05-19 16:04 ` Dmitry Baryshkov
2025-05-20 7:56 ` neil.armstrong
2025-05-19 16:04 ` [PATCH v4 11/30] drm/msm/dpu: get rid of DPU_CTL_DSPP_SUB_BLOCK_FLUSH Dmitry Baryshkov
` (19 subsequent siblings)
29 siblings, 1 reply; 64+ messages in thread
From: Dmitry Baryshkov @ 2025-05-19 16:04 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Sean Paul, Marijn Suijten, David Airlie,
Simona Vetter, Vinod Koul, Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel,
Dmitry Baryshkov
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Continue migration to the MDSS-revision based checks and replace
DPU_CTL_FETCH_ACTIVE feature bit with the core_major_ver >= 7 check.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 --
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 2 +-
3 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 0863e5cfb3283ed32f61ddd4483220742df8633d..6fed2cce082c476c1f7f8ee683f2a6f3eeaa5231 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -105,8 +105,7 @@
(BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_DSC))
#define CTL_SC7280_MASK \
- (BIT(DPU_CTL_FETCH_ACTIVE) | \
- BIT(DPU_CTL_VM_CFG) | \
+ (BIT(DPU_CTL_VM_CFG) | \
BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH))
#define INTF_SC7180_MASK \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 9981d090b689b46bbc378d1965b0efd1df0efa8b..82f04de6300eca7d05ece3ac880c26f3a56505b9 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -132,14 +132,12 @@ enum {
/**
* CTL sub-blocks
* @DPU_CTL_SPLIT_DISPLAY: CTL supports video mode split display
- * @DPU_CTL_FETCH_ACTIVE: Active CTL for fetch HW (SSPPs)
* @DPU_CTL_VM_CFG: CTL config to support multiple VMs
* @DPU_CTL_DSPP_BLOCK_FLUSH: CTL config to support dspp sub-block flush
* @DPU_CTL_MAX
*/
enum {
DPU_CTL_SPLIT_DISPLAY = 0x1,
- DPU_CTL_FETCH_ACTIVE,
DPU_CTL_VM_CFG,
DPU_CTL_DSPP_SUB_BLOCK_FLUSH,
DPU_CTL_MAX
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index 2dfb7db371a3915f663cf134e4dd62f92224185b..772df53bfc4fcc2ff976f66ef7339be1ae3da8f4 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -809,7 +809,7 @@ struct dpu_hw_ctl *dpu_hw_ctl_init(struct drm_device *dev,
else
c->ops.update_pending_flush_dspp = dpu_hw_ctl_update_pending_flush_dspp;
- if (c->caps->features & BIT(DPU_CTL_FETCH_ACTIVE))
+ if (mdss_ver->core_major_ver >= 7)
c->ops.set_active_fetch_pipes = dpu_hw_ctl_set_active_fetch_pipes;
c->idx = cfg->id;
--
2.39.5
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH v4 10/30] drm/msm/dpu: get rid of DPU_CTL_FETCH_ACTIVE
2025-05-19 16:04 ` [PATCH v4 10/30] drm/msm/dpu: get rid of DPU_CTL_FETCH_ACTIVE Dmitry Baryshkov
@ 2025-05-20 7:56 ` neil.armstrong
0 siblings, 0 replies; 64+ messages in thread
From: neil.armstrong @ 2025-05-20 7:56 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Abhinav Kumar, Sean Paul,
Marijn Suijten, David Airlie, Simona Vetter, Vinod Koul,
Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel,
Dmitry Baryshkov
On 19/05/2025 18:04, Dmitry Baryshkov wrote:
> From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>
> Continue migration to the MDSS-revision based checks and replace
> DPU_CTL_FETCH_ACTIVE feature bit with the core_major_ver >= 7 check.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +--
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 --
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 2 +-
> 3 files changed, 2 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index 0863e5cfb3283ed32f61ddd4483220742df8633d..6fed2cce082c476c1f7f8ee683f2a6f3eeaa5231 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -105,8 +105,7 @@
> (BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_DSC))
>
> #define CTL_SC7280_MASK \
> - (BIT(DPU_CTL_FETCH_ACTIVE) | \
> - BIT(DPU_CTL_VM_CFG) | \
> + (BIT(DPU_CTL_VM_CFG) | \
> BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH))
>
> #define INTF_SC7180_MASK \
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index 9981d090b689b46bbc378d1965b0efd1df0efa8b..82f04de6300eca7d05ece3ac880c26f3a56505b9 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -132,14 +132,12 @@ enum {
> /**
> * CTL sub-blocks
> * @DPU_CTL_SPLIT_DISPLAY: CTL supports video mode split display
> - * @DPU_CTL_FETCH_ACTIVE: Active CTL for fetch HW (SSPPs)
> * @DPU_CTL_VM_CFG: CTL config to support multiple VMs
> * @DPU_CTL_DSPP_BLOCK_FLUSH: CTL config to support dspp sub-block flush
> * @DPU_CTL_MAX
> */
> enum {
> DPU_CTL_SPLIT_DISPLAY = 0x1,
> - DPU_CTL_FETCH_ACTIVE,
> DPU_CTL_VM_CFG,
> DPU_CTL_DSPP_SUB_BLOCK_FLUSH,
> DPU_CTL_MAX
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> index 2dfb7db371a3915f663cf134e4dd62f92224185b..772df53bfc4fcc2ff976f66ef7339be1ae3da8f4 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> @@ -809,7 +809,7 @@ struct dpu_hw_ctl *dpu_hw_ctl_init(struct drm_device *dev,
> else
> c->ops.update_pending_flush_dspp = dpu_hw_ctl_update_pending_flush_dspp;
>
> - if (c->caps->features & BIT(DPU_CTL_FETCH_ACTIVE))
> + if (mdss_ver->core_major_ver >= 7)
> c->ops.set_active_fetch_pipes = dpu_hw_ctl_set_active_fetch_pipes;
>
> c->idx = cfg->id;
>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH v4 11/30] drm/msm/dpu: get rid of DPU_CTL_DSPP_SUB_BLOCK_FLUSH
2025-05-19 16:04 [PATCH v4 00/30] drm/msm/dpu: rework HW block feature handling Dmitry Baryshkov
` (9 preceding siblings ...)
2025-05-19 16:04 ` [PATCH v4 10/30] drm/msm/dpu: get rid of DPU_CTL_FETCH_ACTIVE Dmitry Baryshkov
@ 2025-05-19 16:04 ` Dmitry Baryshkov
2025-05-20 7:55 ` neil.armstrong
2025-05-19 16:04 ` [PATCH v4 12/30] drm/msm/dpu: get rid of DPU_CTL_VM_CFG Dmitry Baryshkov
` (18 subsequent siblings)
29 siblings, 1 reply; 64+ messages in thread
From: Dmitry Baryshkov @ 2025-05-19 16:04 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Sean Paul, Marijn Suijten, David Airlie,
Simona Vetter, Vinod Koul, Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel,
Dmitry Baryshkov
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Continue migration to the MDSS-revision based checks and replace
DPU_CTL_DSPP_SUB_BLOCK_FLUSH feature bit with the core_major_ver >= 7
check.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 --
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 2 +-
3 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 6fed2cce082c476c1f7f8ee683f2a6f3eeaa5231..19a859e2a1f80c2321789af4ec7c5e299f0fb873 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -105,8 +105,7 @@
(BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_DSC))
#define CTL_SC7280_MASK \
- (BIT(DPU_CTL_VM_CFG) | \
- BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH))
+ (BIT(DPU_CTL_VM_CFG))
#define INTF_SC7180_MASK \
(BIT(DPU_INTF_INPUT_CTRL) | \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 82f04de6300eca7d05ece3ac880c26f3a56505b9..1e5fc1d5873975189a1759212b8a6c6078de22f9 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -133,13 +133,11 @@ enum {
* CTL sub-blocks
* @DPU_CTL_SPLIT_DISPLAY: CTL supports video mode split display
* @DPU_CTL_VM_CFG: CTL config to support multiple VMs
- * @DPU_CTL_DSPP_BLOCK_FLUSH: CTL config to support dspp sub-block flush
* @DPU_CTL_MAX
*/
enum {
DPU_CTL_SPLIT_DISPLAY = 0x1,
DPU_CTL_VM_CFG,
- DPU_CTL_DSPP_SUB_BLOCK_FLUSH,
DPU_CTL_MAX
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index 772df53bfc4fcc2ff976f66ef7339be1ae3da8f4..edb82c81b0a449b1a7273fc258961b9447be8d9d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -804,7 +804,7 @@ struct dpu_hw_ctl *dpu_hw_ctl_init(struct drm_device *dev,
c->ops.setup_blendstage = dpu_hw_ctl_setup_blendstage;
c->ops.update_pending_flush_sspp = dpu_hw_ctl_update_pending_flush_sspp;
c->ops.update_pending_flush_mixer = dpu_hw_ctl_update_pending_flush_mixer;
- if (c->caps->features & BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH))
+ if (mdss_ver->core_major_ver >= 7)
c->ops.update_pending_flush_dspp = dpu_hw_ctl_update_pending_flush_dspp_sub_blocks;
else
c->ops.update_pending_flush_dspp = dpu_hw_ctl_update_pending_flush_dspp;
--
2.39.5
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH v4 11/30] drm/msm/dpu: get rid of DPU_CTL_DSPP_SUB_BLOCK_FLUSH
2025-05-19 16:04 ` [PATCH v4 11/30] drm/msm/dpu: get rid of DPU_CTL_DSPP_SUB_BLOCK_FLUSH Dmitry Baryshkov
@ 2025-05-20 7:55 ` neil.armstrong
0 siblings, 0 replies; 64+ messages in thread
From: neil.armstrong @ 2025-05-20 7:55 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Abhinav Kumar, Sean Paul,
Marijn Suijten, David Airlie, Simona Vetter, Vinod Koul,
Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel,
Dmitry Baryshkov
On 19/05/2025 18:04, Dmitry Baryshkov wrote:
> From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>
> Continue migration to the MDSS-revision based checks and replace
> DPU_CTL_DSPP_SUB_BLOCK_FLUSH feature bit with the core_major_ver >= 7
> check.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +--
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 --
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 2 +-
> 3 files changed, 2 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index 6fed2cce082c476c1f7f8ee683f2a6f3eeaa5231..19a859e2a1f80c2321789af4ec7c5e299f0fb873 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -105,8 +105,7 @@
> (BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_DSC))
>
> #define CTL_SC7280_MASK \
> - (BIT(DPU_CTL_VM_CFG) | \
> - BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH))
> + (BIT(DPU_CTL_VM_CFG))
>
> #define INTF_SC7180_MASK \
> (BIT(DPU_INTF_INPUT_CTRL) | \
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index 82f04de6300eca7d05ece3ac880c26f3a56505b9..1e5fc1d5873975189a1759212b8a6c6078de22f9 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -133,13 +133,11 @@ enum {
> * CTL sub-blocks
> * @DPU_CTL_SPLIT_DISPLAY: CTL supports video mode split display
> * @DPU_CTL_VM_CFG: CTL config to support multiple VMs
> - * @DPU_CTL_DSPP_BLOCK_FLUSH: CTL config to support dspp sub-block flush
> * @DPU_CTL_MAX
> */
> enum {
> DPU_CTL_SPLIT_DISPLAY = 0x1,
> DPU_CTL_VM_CFG,
> - DPU_CTL_DSPP_SUB_BLOCK_FLUSH,
> DPU_CTL_MAX
> };
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> index 772df53bfc4fcc2ff976f66ef7339be1ae3da8f4..edb82c81b0a449b1a7273fc258961b9447be8d9d 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> @@ -804,7 +804,7 @@ struct dpu_hw_ctl *dpu_hw_ctl_init(struct drm_device *dev,
> c->ops.setup_blendstage = dpu_hw_ctl_setup_blendstage;
> c->ops.update_pending_flush_sspp = dpu_hw_ctl_update_pending_flush_sspp;
> c->ops.update_pending_flush_mixer = dpu_hw_ctl_update_pending_flush_mixer;
> - if (c->caps->features & BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH))
> + if (mdss_ver->core_major_ver >= 7)
> c->ops.update_pending_flush_dspp = dpu_hw_ctl_update_pending_flush_dspp_sub_blocks;
> else
> c->ops.update_pending_flush_dspp = dpu_hw_ctl_update_pending_flush_dspp;
>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH v4 12/30] drm/msm/dpu: get rid of DPU_CTL_VM_CFG
2025-05-19 16:04 [PATCH v4 00/30] drm/msm/dpu: rework HW block feature handling Dmitry Baryshkov
` (10 preceding siblings ...)
2025-05-19 16:04 ` [PATCH v4 11/30] drm/msm/dpu: get rid of DPU_CTL_DSPP_SUB_BLOCK_FLUSH Dmitry Baryshkov
@ 2025-05-19 16:04 ` Dmitry Baryshkov
2025-05-20 7:55 ` neil.armstrong
2025-05-19 16:04 ` [PATCH v4 13/30] drm/msm/dpu: get rid of DPU_DATA_HCTL_EN Dmitry Baryshkov
` (17 subsequent siblings)
29 siblings, 1 reply; 64+ messages in thread
From: Dmitry Baryshkov @ 2025-05-19 16:04 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Sean Paul, Marijn Suijten, David Airlie,
Simona Vetter, Vinod Koul, Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel,
Dmitry Baryshkov
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Continue migration to the MDSS-revision based checks and replace
DPU_CTL_VM_CFG feature bit with the core_major_ver >= 7 check.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 6 ------
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 6 ------
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 4 ----
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 6 ------
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 6 ------
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 6 ------
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 6 ------
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h | 6 ------
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 6 ------
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 ---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 --
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 2 +-
12 files changed, 1 insertion(+), 58 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
index 52ad7e2af0148c9ea81a2c95b270be7058fbaec1..bbdb7e1668fee33cb7d99a7cb8ab001e58f079be 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
@@ -31,32 +31,26 @@ static const struct dpu_ctl_cfg sm8650_ctl[] = {
{
.name = "ctl_0", .id = CTL_0,
.base = 0x15000, .len = 0x1000,
- .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
}, {
.name = "ctl_1", .id = CTL_1,
.base = 0x16000, .len = 0x1000,
- .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
}, {
.name = "ctl_2", .id = CTL_2,
.base = 0x17000, .len = 0x1000,
- .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
}, {
.name = "ctl_3", .id = CTL_3,
.base = 0x18000, .len = 0x1000,
- .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
}, {
.name = "ctl_4", .id = CTL_4,
.base = 0x19000, .len = 0x1000,
- .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
}, {
.name = "ctl_5", .id = CTL_5,
.base = 0x1a000, .len = 0x1000,
- .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
index bbef0e1c597299d24a923e1f0d977c99afedb8fb..3c6da0acdc3b81db65e2544f16d90322fe7e92a6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
@@ -39,32 +39,26 @@ static const struct dpu_ctl_cfg sm8350_ctl[] = {
{
.name = "ctl_0", .id = CTL_0,
.base = 0x15000, .len = 0x1e8,
- .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
}, {
.name = "ctl_1", .id = CTL_1,
.base = 0x16000, .len = 0x1e8,
- .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
}, {
.name = "ctl_2", .id = CTL_2,
.base = 0x17000, .len = 0x1e8,
- .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
}, {
.name = "ctl_3", .id = CTL_3,
.base = 0x18000, .len = 0x1e8,
- .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
}, {
.name = "ctl_4", .id = CTL_4,
.base = 0x19000, .len = 0x1e8,
- .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
}, {
.name = "ctl_5", .id = CTL_5,
.base = 0x1a000, .len = 0x1e8,
- .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
index 281826170da082fc90a05c641060901ece0fbed3..2ee29c56224596b3786104090290b88cecf7b223 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
@@ -32,22 +32,18 @@ static const struct dpu_ctl_cfg sc7280_ctl[] = {
{
.name = "ctl_0", .id = CTL_0,
.base = 0x15000, .len = 0x1e8,
- .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
}, {
.name = "ctl_1", .id = CTL_1,
.base = 0x16000, .len = 0x1e8,
- .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
}, {
.name = "ctl_2", .id = CTL_2,
.base = 0x17000, .len = 0x1e8,
- .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
}, {
.name = "ctl_3", .id = CTL_3,
.base = 0x18000, .len = 0x1e8,
- .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
index 1dd0a1aa222d65f03013d634a87371dc552b5bd8..2f20d0014a94e707a5f0548fc1c6bf0983b0cad0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
@@ -39,32 +39,26 @@ static const struct dpu_ctl_cfg sc8280xp_ctl[] = {
{
.name = "ctl_0", .id = CTL_0,
.base = 0x15000, .len = 0x204,
- .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
}, {
.name = "ctl_1", .id = CTL_1,
.base = 0x16000, .len = 0x204,
- .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
}, {
.name = "ctl_2", .id = CTL_2,
.base = 0x17000, .len = 0x204,
- .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
}, {
.name = "ctl_3", .id = CTL_3,
.base = 0x18000, .len = 0x204,
- .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
}, {
.name = "ctl_4", .id = CTL_4,
.base = 0x19000, .len = 0x204,
- .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
}, {
.name = "ctl_5", .id = CTL_5,
.base = 0x1a000, .len = 0x204,
- .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
index 50142b14e24eb875e72e5cff3b28ff8aba89fc9c..314875e2dca96b3b5c40aae0d15fb80da8ebd42c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
@@ -40,32 +40,26 @@ static const struct dpu_ctl_cfg sm8450_ctl[] = {
{
.name = "ctl_0", .id = CTL_0,
.base = 0x15000, .len = 0x204,
- .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
}, {
.name = "ctl_1", .id = CTL_1,
.base = 0x16000, .len = 0x204,
- .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
}, {
.name = "ctl_2", .id = CTL_2,
.base = 0x17000, .len = 0x204,
- .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
}, {
.name = "ctl_3", .id = CTL_3,
.base = 0x18000, .len = 0x204,
- .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
}, {
.name = "ctl_4", .id = CTL_4,
.base = 0x19000, .len = 0x204,
- .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
}, {
.name = "ctl_5", .id = CTL_5,
.base = 0x1a000, .len = 0x204,
- .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
index 264cd6d3640be1bf321fda429748ecdafbeed214..36775f444af4b2654231cd9456ac4eea1f0f18e6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
@@ -39,32 +39,26 @@ static const struct dpu_ctl_cfg sa8775p_ctl[] = {
{
.name = "ctl_0", .id = CTL_0,
.base = 0x15000, .len = 0x204,
- .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
}, {
.name = "ctl_1", .id = CTL_1,
.base = 0x16000, .len = 0x204,
- .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
}, {
.name = "ctl_2", .id = CTL_2,
.base = 0x17000, .len = 0x204,
- .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
}, {
.name = "ctl_3", .id = CTL_3,
.base = 0x18000, .len = 0x204,
- .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
}, {
.name = "ctl_4", .id = CTL_4,
.base = 0x19000, .len = 0x204,
- .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
}, {
.name = "ctl_5", .id = CTL_5,
.base = 0x1a000, .len = 0x204,
- .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
index 83f73c7cdcc3a280285fa32230796fac57167ed6..624f24c8a33a182634d49058014fc3175f5ac9d3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
@@ -31,32 +31,26 @@ static const struct dpu_ctl_cfg sm8550_ctl[] = {
{
.name = "ctl_0", .id = CTL_0,
.base = 0x15000, .len = 0x290,
- .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
}, {
.name = "ctl_1", .id = CTL_1,
.base = 0x16000, .len = 0x290,
- .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
}, {
.name = "ctl_2", .id = CTL_2,
.base = 0x17000, .len = 0x290,
- .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
}, {
.name = "ctl_3", .id = CTL_3,
.base = 0x18000, .len = 0x290,
- .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
}, {
.name = "ctl_4", .id = CTL_4,
.base = 0x19000, .len = 0x290,
- .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
}, {
.name = "ctl_5", .id = CTL_5,
.base = 0x1a000, .len = 0x290,
- .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
index b21aab274703ac1f38698bee82d5d28b0fb6a0d0..857dc8465bf5571cd08cf3115fb96002873c004b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
@@ -31,32 +31,26 @@ static const struct dpu_ctl_cfg sar2130p_ctl[] = {
{
.name = "ctl_0", .id = CTL_0,
.base = 0x15000, .len = 0x290,
- .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
}, {
.name = "ctl_1", .id = CTL_1,
.base = 0x16000, .len = 0x290,
- .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
}, {
.name = "ctl_2", .id = CTL_2,
.base = 0x17000, .len = 0x290,
- .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
}, {
.name = "ctl_3", .id = CTL_3,
.base = 0x18000, .len = 0x290,
- .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
}, {
.name = "ctl_4", .id = CTL_4,
.base = 0x19000, .len = 0x290,
- .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
}, {
.name = "ctl_5", .id = CTL_5,
.base = 0x1a000, .len = 0x290,
- .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
index d7e5f4dd3bccab125b0a42f67eddf194359dc761..05b0962c2d937f077d0b42fa8af6e2da40c7dcae 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
@@ -30,32 +30,26 @@ static const struct dpu_ctl_cfg x1e80100_ctl[] = {
{
.name = "ctl_0", .id = CTL_0,
.base = 0x15000, .len = 0x290,
- .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
}, {
.name = "ctl_1", .id = CTL_1,
.base = 0x16000, .len = 0x290,
- .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
}, {
.name = "ctl_2", .id = CTL_2,
.base = 0x17000, .len = 0x290,
- .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
}, {
.name = "ctl_3", .id = CTL_3,
.base = 0x18000, .len = 0x290,
- .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
}, {
.name = "ctl_4", .id = CTL_4,
.base = 0x19000, .len = 0x290,
- .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
}, {
.name = "ctl_5", .id = CTL_5,
.base = 0x1a000, .len = 0x290,
- .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 19a859e2a1f80c2321789af4ec7c5e299f0fb873..5cd87b13e839e7ad60356cde162405fdfb6f9498 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -104,9 +104,6 @@
#define PINGPONG_SM8150_MASK \
(BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_DSC))
-#define CTL_SC7280_MASK \
- (BIT(DPU_CTL_VM_CFG))
-
#define INTF_SC7180_MASK \
(BIT(DPU_INTF_INPUT_CTRL) | \
BIT(DPU_INTF_STATUS_SUPPORTED) | \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 1e5fc1d5873975189a1759212b8a6c6078de22f9..3b6133e1bb581741fe87b049ad0c89bf30b76019 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -132,12 +132,10 @@ enum {
/**
* CTL sub-blocks
* @DPU_CTL_SPLIT_DISPLAY: CTL supports video mode split display
- * @DPU_CTL_VM_CFG: CTL config to support multiple VMs
* @DPU_CTL_MAX
*/
enum {
DPU_CTL_SPLIT_DISPLAY = 0x1,
- DPU_CTL_VM_CFG,
DPU_CTL_MAX
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index edb82c81b0a449b1a7273fc258961b9447be8d9d..fe4fdfb8774b176fb024d76dc0bd269d9736d226 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -575,7 +575,7 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,
* per VM. Explicitly disable it until VM support is
* added in SW. Power on reset value is not disable.
*/
- if ((test_bit(DPU_CTL_VM_CFG, &ctx->caps->features)))
+ if (ctx->mdss_ver->core_major_ver >= 7)
mode_sel = CTL_DEFAULT_GROUP_ID << 28;
if (cfg->intf_mode_sel == DPU_CTL_MODE_SEL_CMD)
--
2.39.5
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH v4 12/30] drm/msm/dpu: get rid of DPU_CTL_VM_CFG
2025-05-19 16:04 ` [PATCH v4 12/30] drm/msm/dpu: get rid of DPU_CTL_VM_CFG Dmitry Baryshkov
@ 2025-05-20 7:55 ` neil.armstrong
0 siblings, 0 replies; 64+ messages in thread
From: neil.armstrong @ 2025-05-20 7:55 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Abhinav Kumar, Sean Paul,
Marijn Suijten, David Airlie, Simona Vetter, Vinod Koul,
Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel,
Dmitry Baryshkov
On 19/05/2025 18:04, Dmitry Baryshkov wrote:
> From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>
> Continue migration to the MDSS-revision based checks and replace
> DPU_CTL_VM_CFG feature bit with the core_major_ver >= 7 check.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 6 ------
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 6 ------
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 4 ----
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 6 ------
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 6 ------
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 6 ------
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 6 ------
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h | 6 ------
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 6 ------
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 --
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 2 +-
> 12 files changed, 1 insertion(+), 58 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
> index 52ad7e2af0148c9ea81a2c95b270be7058fbaec1..bbdb7e1668fee33cb7d99a7cb8ab001e58f079be 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
> @@ -31,32 +31,26 @@ static const struct dpu_ctl_cfg sm8650_ctl[] = {
> {
> .name = "ctl_0", .id = CTL_0,
> .base = 0x15000, .len = 0x1000,
> - .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> }, {
> .name = "ctl_1", .id = CTL_1,
> .base = 0x16000, .len = 0x1000,
> - .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> }, {
> .name = "ctl_2", .id = CTL_2,
> .base = 0x17000, .len = 0x1000,
> - .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> }, {
> .name = "ctl_3", .id = CTL_3,
> .base = 0x18000, .len = 0x1000,
> - .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> }, {
> .name = "ctl_4", .id = CTL_4,
> .base = 0x19000, .len = 0x1000,
> - .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
> }, {
> .name = "ctl_5", .id = CTL_5,
> .base = 0x1a000, .len = 0x1000,
> - .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> index bbef0e1c597299d24a923e1f0d977c99afedb8fb..3c6da0acdc3b81db65e2544f16d90322fe7e92a6 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> @@ -39,32 +39,26 @@ static const struct dpu_ctl_cfg sm8350_ctl[] = {
> {
> .name = "ctl_0", .id = CTL_0,
> .base = 0x15000, .len = 0x1e8,
> - .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> }, {
> .name = "ctl_1", .id = CTL_1,
> .base = 0x16000, .len = 0x1e8,
> - .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> }, {
> .name = "ctl_2", .id = CTL_2,
> .base = 0x17000, .len = 0x1e8,
> - .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> }, {
> .name = "ctl_3", .id = CTL_3,
> .base = 0x18000, .len = 0x1e8,
> - .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> }, {
> .name = "ctl_4", .id = CTL_4,
> .base = 0x19000, .len = 0x1e8,
> - .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
> }, {
> .name = "ctl_5", .id = CTL_5,
> .base = 0x1a000, .len = 0x1e8,
> - .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> index 281826170da082fc90a05c641060901ece0fbed3..2ee29c56224596b3786104090290b88cecf7b223 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> @@ -32,22 +32,18 @@ static const struct dpu_ctl_cfg sc7280_ctl[] = {
> {
> .name = "ctl_0", .id = CTL_0,
> .base = 0x15000, .len = 0x1e8,
> - .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> }, {
> .name = "ctl_1", .id = CTL_1,
> .base = 0x16000, .len = 0x1e8,
> - .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> }, {
> .name = "ctl_2", .id = CTL_2,
> .base = 0x17000, .len = 0x1e8,
> - .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> }, {
> .name = "ctl_3", .id = CTL_3,
> .base = 0x18000, .len = 0x1e8,
> - .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> index 1dd0a1aa222d65f03013d634a87371dc552b5bd8..2f20d0014a94e707a5f0548fc1c6bf0983b0cad0 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> @@ -39,32 +39,26 @@ static const struct dpu_ctl_cfg sc8280xp_ctl[] = {
> {
> .name = "ctl_0", .id = CTL_0,
> .base = 0x15000, .len = 0x204,
> - .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> }, {
> .name = "ctl_1", .id = CTL_1,
> .base = 0x16000, .len = 0x204,
> - .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> }, {
> .name = "ctl_2", .id = CTL_2,
> .base = 0x17000, .len = 0x204,
> - .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> }, {
> .name = "ctl_3", .id = CTL_3,
> .base = 0x18000, .len = 0x204,
> - .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> }, {
> .name = "ctl_4", .id = CTL_4,
> .base = 0x19000, .len = 0x204,
> - .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
> }, {
> .name = "ctl_5", .id = CTL_5,
> .base = 0x1a000, .len = 0x204,
> - .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> index 50142b14e24eb875e72e5cff3b28ff8aba89fc9c..314875e2dca96b3b5c40aae0d15fb80da8ebd42c 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> @@ -40,32 +40,26 @@ static const struct dpu_ctl_cfg sm8450_ctl[] = {
> {
> .name = "ctl_0", .id = CTL_0,
> .base = 0x15000, .len = 0x204,
> - .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> }, {
> .name = "ctl_1", .id = CTL_1,
> .base = 0x16000, .len = 0x204,
> - .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> }, {
> .name = "ctl_2", .id = CTL_2,
> .base = 0x17000, .len = 0x204,
> - .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> }, {
> .name = "ctl_3", .id = CTL_3,
> .base = 0x18000, .len = 0x204,
> - .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> }, {
> .name = "ctl_4", .id = CTL_4,
> .base = 0x19000, .len = 0x204,
> - .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
> }, {
> .name = "ctl_5", .id = CTL_5,
> .base = 0x1a000, .len = 0x204,
> - .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
> index 264cd6d3640be1bf321fda429748ecdafbeed214..36775f444af4b2654231cd9456ac4eea1f0f18e6 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
> @@ -39,32 +39,26 @@ static const struct dpu_ctl_cfg sa8775p_ctl[] = {
> {
> .name = "ctl_0", .id = CTL_0,
> .base = 0x15000, .len = 0x204,
> - .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> }, {
> .name = "ctl_1", .id = CTL_1,
> .base = 0x16000, .len = 0x204,
> - .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> }, {
> .name = "ctl_2", .id = CTL_2,
> .base = 0x17000, .len = 0x204,
> - .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> }, {
> .name = "ctl_3", .id = CTL_3,
> .base = 0x18000, .len = 0x204,
> - .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> }, {
> .name = "ctl_4", .id = CTL_4,
> .base = 0x19000, .len = 0x204,
> - .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
> }, {
> .name = "ctl_5", .id = CTL_5,
> .base = 0x1a000, .len = 0x204,
> - .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> index 83f73c7cdcc3a280285fa32230796fac57167ed6..624f24c8a33a182634d49058014fc3175f5ac9d3 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> @@ -31,32 +31,26 @@ static const struct dpu_ctl_cfg sm8550_ctl[] = {
> {
> .name = "ctl_0", .id = CTL_0,
> .base = 0x15000, .len = 0x290,
> - .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> }, {
> .name = "ctl_1", .id = CTL_1,
> .base = 0x16000, .len = 0x290,
> - .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> }, {
> .name = "ctl_2", .id = CTL_2,
> .base = 0x17000, .len = 0x290,
> - .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> }, {
> .name = "ctl_3", .id = CTL_3,
> .base = 0x18000, .len = 0x290,
> - .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> }, {
> .name = "ctl_4", .id = CTL_4,
> .base = 0x19000, .len = 0x290,
> - .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
> }, {
> .name = "ctl_5", .id = CTL_5,
> .base = 0x1a000, .len = 0x290,
> - .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
> index b21aab274703ac1f38698bee82d5d28b0fb6a0d0..857dc8465bf5571cd08cf3115fb96002873c004b 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
> @@ -31,32 +31,26 @@ static const struct dpu_ctl_cfg sar2130p_ctl[] = {
> {
> .name = "ctl_0", .id = CTL_0,
> .base = 0x15000, .len = 0x290,
> - .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> }, {
> .name = "ctl_1", .id = CTL_1,
> .base = 0x16000, .len = 0x290,
> - .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> }, {
> .name = "ctl_2", .id = CTL_2,
> .base = 0x17000, .len = 0x290,
> - .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> }, {
> .name = "ctl_3", .id = CTL_3,
> .base = 0x18000, .len = 0x290,
> - .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> }, {
> .name = "ctl_4", .id = CTL_4,
> .base = 0x19000, .len = 0x290,
> - .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
> }, {
> .name = "ctl_5", .id = CTL_5,
> .base = 0x1a000, .len = 0x290,
> - .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
> index d7e5f4dd3bccab125b0a42f67eddf194359dc761..05b0962c2d937f077d0b42fa8af6e2da40c7dcae 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
> @@ -30,32 +30,26 @@ static const struct dpu_ctl_cfg x1e80100_ctl[] = {
> {
> .name = "ctl_0", .id = CTL_0,
> .base = 0x15000, .len = 0x290,
> - .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> }, {
> .name = "ctl_1", .id = CTL_1,
> .base = 0x16000, .len = 0x290,
> - .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> }, {
> .name = "ctl_2", .id = CTL_2,
> .base = 0x17000, .len = 0x290,
> - .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> }, {
> .name = "ctl_3", .id = CTL_3,
> .base = 0x18000, .len = 0x290,
> - .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> }, {
> .name = "ctl_4", .id = CTL_4,
> .base = 0x19000, .len = 0x290,
> - .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
> }, {
> .name = "ctl_5", .id = CTL_5,
> .base = 0x1a000, .len = 0x290,
> - .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index 19a859e2a1f80c2321789af4ec7c5e299f0fb873..5cd87b13e839e7ad60356cde162405fdfb6f9498 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -104,9 +104,6 @@
> #define PINGPONG_SM8150_MASK \
> (BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_DSC))
>
> -#define CTL_SC7280_MASK \
> - (BIT(DPU_CTL_VM_CFG))
> -
> #define INTF_SC7180_MASK \
> (BIT(DPU_INTF_INPUT_CTRL) | \
> BIT(DPU_INTF_STATUS_SUPPORTED) | \
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index 1e5fc1d5873975189a1759212b8a6c6078de22f9..3b6133e1bb581741fe87b049ad0c89bf30b76019 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -132,12 +132,10 @@ enum {
> /**
> * CTL sub-blocks
> * @DPU_CTL_SPLIT_DISPLAY: CTL supports video mode split display
> - * @DPU_CTL_VM_CFG: CTL config to support multiple VMs
> * @DPU_CTL_MAX
> */
> enum {
> DPU_CTL_SPLIT_DISPLAY = 0x1,
> - DPU_CTL_VM_CFG,
> DPU_CTL_MAX
> };
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> index edb82c81b0a449b1a7273fc258961b9447be8d9d..fe4fdfb8774b176fb024d76dc0bd269d9736d226 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> @@ -575,7 +575,7 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,
> * per VM. Explicitly disable it until VM support is
> * added in SW. Power on reset value is not disable.
> */
> - if ((test_bit(DPU_CTL_VM_CFG, &ctx->caps->features)))
> + if (ctx->mdss_ver->core_major_ver >= 7)
> mode_sel = CTL_DEFAULT_GROUP_ID << 28;
>
> if (cfg->intf_mode_sel == DPU_CTL_MODE_SEL_CMD)
>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH v4 13/30] drm/msm/dpu: get rid of DPU_DATA_HCTL_EN
2025-05-19 16:04 [PATCH v4 00/30] drm/msm/dpu: rework HW block feature handling Dmitry Baryshkov
` (11 preceding siblings ...)
2025-05-19 16:04 ` [PATCH v4 12/30] drm/msm/dpu: get rid of DPU_CTL_VM_CFG Dmitry Baryshkov
@ 2025-05-19 16:04 ` Dmitry Baryshkov
2025-05-20 7:55 ` neil.armstrong
2025-05-19 16:04 ` [PATCH v4 14/30] drm/msm/dpu: get rid of DPU_INTF_STATUS_SUPPORTED Dmitry Baryshkov
` (16 subsequent siblings)
29 siblings, 1 reply; 64+ messages in thread
From: Dmitry Baryshkov @ 2025-05-19 16:04 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Sean Paul, Marijn Suijten, David Airlie,
Simona Vetter, Vinod Koul, Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel,
Dmitry Baryshkov
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Continue migration to the MDSS-revision based checks and replace
DPU_DATA_HCTL_EN feature bit with the core_major_ver >= 5 check.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 3 ---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 2 +-
3 files changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 5cd87b13e839e7ad60356cde162405fdfb6f9498..1244dd59648d11123c507a1369f28f952d047fd5 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -106,8 +106,7 @@
#define INTF_SC7180_MASK \
(BIT(DPU_INTF_INPUT_CTRL) | \
- BIT(DPU_INTF_STATUS_SUPPORTED) | \
- BIT(DPU_DATA_HCTL_EN))
+ BIT(DPU_INTF_STATUS_SUPPORTED))
#define WB_SDM845_MASK (BIT(DPU_WB_LINE_MODE) | \
BIT(DPU_WB_UBWC) | \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 3b6133e1bb581741fe87b049ad0c89bf30b76019..bf6b2392efb47fa8c3e3c5d17f1a72341872e18b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -143,14 +143,11 @@ enum {
* INTF sub-blocks
* @DPU_INTF_INPUT_CTRL Supports the setting of pp block from which
* pixel data arrives to this INTF
- * @DPU_DATA_HCTL_EN Allows data to be transferred at different rate
- * than video timing
* @DPU_INTF_STATUS_SUPPORTED INTF block has INTF_STATUS register
* @DPU_INTF_MAX
*/
enum {
DPU_INTF_INPUT_CTRL = 0x1,
- DPU_DATA_HCTL_EN,
DPU_INTF_STATUS_SUPPORTED,
DPU_INTF_MAX
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index 1d56c21ac79095ab515aeb485346e1eb5793c260..8f9733aad2dec3a9b5464d55b00f350348842911 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
@@ -237,7 +237,7 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *intf,
DPU_REG_WRITE(c, INTF_FRAME_LINE_COUNT_EN, 0x3);
DPU_REG_WRITE(c, INTF_CONFIG, intf_cfg);
DPU_REG_WRITE(c, INTF_PANEL_FORMAT, panel_format);
- if (intf->cap->features & BIT(DPU_DATA_HCTL_EN)) {
+ if (intf->mdss_ver->core_major_ver >= 5) {
/*
* DATA_HCTL_EN controls data timing which can be different from
* video timing. It is recommended to enable it for all cases, except
--
2.39.5
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH v4 13/30] drm/msm/dpu: get rid of DPU_DATA_HCTL_EN
2025-05-19 16:04 ` [PATCH v4 13/30] drm/msm/dpu: get rid of DPU_DATA_HCTL_EN Dmitry Baryshkov
@ 2025-05-20 7:55 ` neil.armstrong
0 siblings, 0 replies; 64+ messages in thread
From: neil.armstrong @ 2025-05-20 7:55 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Abhinav Kumar, Sean Paul,
Marijn Suijten, David Airlie, Simona Vetter, Vinod Koul,
Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel,
Dmitry Baryshkov
On 19/05/2025 18:04, Dmitry Baryshkov wrote:
> From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>
> Continue migration to the MDSS-revision based checks and replace
> DPU_DATA_HCTL_EN feature bit with the core_major_ver >= 5 check.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +--
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 3 ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 2 +-
> 3 files changed, 2 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index 5cd87b13e839e7ad60356cde162405fdfb6f9498..1244dd59648d11123c507a1369f28f952d047fd5 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -106,8 +106,7 @@
>
> #define INTF_SC7180_MASK \
> (BIT(DPU_INTF_INPUT_CTRL) | \
> - BIT(DPU_INTF_STATUS_SUPPORTED) | \
> - BIT(DPU_DATA_HCTL_EN))
> + BIT(DPU_INTF_STATUS_SUPPORTED))
>
> #define WB_SDM845_MASK (BIT(DPU_WB_LINE_MODE) | \
> BIT(DPU_WB_UBWC) | \
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index 3b6133e1bb581741fe87b049ad0c89bf30b76019..bf6b2392efb47fa8c3e3c5d17f1a72341872e18b 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -143,14 +143,11 @@ enum {
> * INTF sub-blocks
> * @DPU_INTF_INPUT_CTRL Supports the setting of pp block from which
> * pixel data arrives to this INTF
> - * @DPU_DATA_HCTL_EN Allows data to be transferred at different rate
> - * than video timing
> * @DPU_INTF_STATUS_SUPPORTED INTF block has INTF_STATUS register
> * @DPU_INTF_MAX
> */
> enum {
> DPU_INTF_INPUT_CTRL = 0x1,
> - DPU_DATA_HCTL_EN,
> DPU_INTF_STATUS_SUPPORTED,
> DPU_INTF_MAX
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> index 1d56c21ac79095ab515aeb485346e1eb5793c260..8f9733aad2dec3a9b5464d55b00f350348842911 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> @@ -237,7 +237,7 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *intf,
> DPU_REG_WRITE(c, INTF_FRAME_LINE_COUNT_EN, 0x3);
> DPU_REG_WRITE(c, INTF_CONFIG, intf_cfg);
> DPU_REG_WRITE(c, INTF_PANEL_FORMAT, panel_format);
> - if (intf->cap->features & BIT(DPU_DATA_HCTL_EN)) {
> + if (intf->mdss_ver->core_major_ver >= 5) {
> /*
> * DATA_HCTL_EN controls data timing which can be different from
> * video timing. It is recommended to enable it for all cases, except
>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH v4 14/30] drm/msm/dpu: get rid of DPU_INTF_STATUS_SUPPORTED
2025-05-19 16:04 [PATCH v4 00/30] drm/msm/dpu: rework HW block feature handling Dmitry Baryshkov
` (12 preceding siblings ...)
2025-05-19 16:04 ` [PATCH v4 13/30] drm/msm/dpu: get rid of DPU_DATA_HCTL_EN Dmitry Baryshkov
@ 2025-05-19 16:04 ` Dmitry Baryshkov
2025-05-20 7:55 ` neil.armstrong
2025-05-19 16:04 ` [PATCH v4 15/30] drm/msm/dpu: get rid of DPU_INTF_INPUT_CTRL Dmitry Baryshkov
` (15 subsequent siblings)
29 siblings, 1 reply; 64+ messages in thread
From: Dmitry Baryshkov @ 2025-05-19 16:04 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Sean Paul, Marijn Suijten, David Airlie,
Simona Vetter, Vinod Koul, Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel,
Dmitry Baryshkov
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Continue migration to the MDSS-revision based checks and replace
DPU_INTF_STATUS_SUPPORTED feature bit with the core_major_ver >= 5
check.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 --
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 3 +--
3 files changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 1244dd59648d11123c507a1369f28f952d047fd5..4482f2fe6f04e58408b55994d885ea1c717c6a07 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -105,8 +105,7 @@
(BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_DSC))
#define INTF_SC7180_MASK \
- (BIT(DPU_INTF_INPUT_CTRL) | \
- BIT(DPU_INTF_STATUS_SUPPORTED))
+ (BIT(DPU_INTF_INPUT_CTRL))
#define WB_SDM845_MASK (BIT(DPU_WB_LINE_MODE) | \
BIT(DPU_WB_UBWC) | \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index bf6b2392efb47fa8c3e3c5d17f1a72341872e18b..e1c6df3a3b72ffb5a816bd18266a35abe723fbd9 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -143,12 +143,10 @@ enum {
* INTF sub-blocks
* @DPU_INTF_INPUT_CTRL Supports the setting of pp block from which
* pixel data arrives to this INTF
- * @DPU_INTF_STATUS_SUPPORTED INTF block has INTF_STATUS register
* @DPU_INTF_MAX
*/
enum {
DPU_INTF_INPUT_CTRL = 0x1,
- DPU_INTF_STATUS_SUPPORTED,
DPU_INTF_MAX
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index 8f9733aad2dec3a9b5464d55b00f350348842911..54c2e984ef0ce604e3eda49595d2816ea41bd7fd 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
@@ -308,9 +308,8 @@ static void dpu_hw_intf_get_status(
struct dpu_hw_intf_status *s)
{
struct dpu_hw_blk_reg_map *c = &intf->hw;
- unsigned long cap = intf->cap->features;
- if (cap & BIT(DPU_INTF_STATUS_SUPPORTED))
+ if (intf->mdss_ver->core_major_ver >= 5)
s->is_en = DPU_REG_READ(c, INTF_STATUS) & BIT(0);
else
s->is_en = DPU_REG_READ(c, INTF_TIMING_ENGINE_EN);
--
2.39.5
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH v4 14/30] drm/msm/dpu: get rid of DPU_INTF_STATUS_SUPPORTED
2025-05-19 16:04 ` [PATCH v4 14/30] drm/msm/dpu: get rid of DPU_INTF_STATUS_SUPPORTED Dmitry Baryshkov
@ 2025-05-20 7:55 ` neil.armstrong
0 siblings, 0 replies; 64+ messages in thread
From: neil.armstrong @ 2025-05-20 7:55 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Abhinav Kumar, Sean Paul,
Marijn Suijten, David Airlie, Simona Vetter, Vinod Koul,
Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel,
Dmitry Baryshkov
On 19/05/2025 18:04, Dmitry Baryshkov wrote:
> From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>
> Continue migration to the MDSS-revision based checks and replace
> DPU_INTF_STATUS_SUPPORTED feature bit with the core_major_ver >= 5
> check.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +--
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 --
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 3 +--
> 3 files changed, 2 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index 1244dd59648d11123c507a1369f28f952d047fd5..4482f2fe6f04e58408b55994d885ea1c717c6a07 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -105,8 +105,7 @@
> (BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_DSC))
>
> #define INTF_SC7180_MASK \
> - (BIT(DPU_INTF_INPUT_CTRL) | \
> - BIT(DPU_INTF_STATUS_SUPPORTED))
> + (BIT(DPU_INTF_INPUT_CTRL))
>
> #define WB_SDM845_MASK (BIT(DPU_WB_LINE_MODE) | \
> BIT(DPU_WB_UBWC) | \
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index bf6b2392efb47fa8c3e3c5d17f1a72341872e18b..e1c6df3a3b72ffb5a816bd18266a35abe723fbd9 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -143,12 +143,10 @@ enum {
> * INTF sub-blocks
> * @DPU_INTF_INPUT_CTRL Supports the setting of pp block from which
> * pixel data arrives to this INTF
> - * @DPU_INTF_STATUS_SUPPORTED INTF block has INTF_STATUS register
> * @DPU_INTF_MAX
> */
> enum {
> DPU_INTF_INPUT_CTRL = 0x1,
> - DPU_INTF_STATUS_SUPPORTED,
> DPU_INTF_MAX
> };
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> index 8f9733aad2dec3a9b5464d55b00f350348842911..54c2e984ef0ce604e3eda49595d2816ea41bd7fd 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> @@ -308,9 +308,8 @@ static void dpu_hw_intf_get_status(
> struct dpu_hw_intf_status *s)
> {
> struct dpu_hw_blk_reg_map *c = &intf->hw;
> - unsigned long cap = intf->cap->features;
>
> - if (cap & BIT(DPU_INTF_STATUS_SUPPORTED))
> + if (intf->mdss_ver->core_major_ver >= 5)
> s->is_en = DPU_REG_READ(c, INTF_STATUS) & BIT(0);
> else
> s->is_en = DPU_REG_READ(c, INTF_TIMING_ENGINE_EN);
>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH v4 15/30] drm/msm/dpu: get rid of DPU_INTF_INPUT_CTRL
2025-05-19 16:04 [PATCH v4 00/30] drm/msm/dpu: rework HW block feature handling Dmitry Baryshkov
` (13 preceding siblings ...)
2025-05-19 16:04 ` [PATCH v4 14/30] drm/msm/dpu: get rid of DPU_INTF_STATUS_SUPPORTED Dmitry Baryshkov
@ 2025-05-19 16:04 ` Dmitry Baryshkov
2025-05-20 7:55 ` neil.armstrong
2025-05-19 16:04 ` [PATCH v4 16/30] drm/msm/dpu: get rid of DPU_PINGPONG_DSC Dmitry Baryshkov
` (14 subsequent siblings)
29 siblings, 1 reply; 64+ messages in thread
From: Dmitry Baryshkov @ 2025-05-19 16:04 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Sean Paul, Marijn Suijten, David Airlie,
Simona Vetter, Vinod Koul, Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel,
Dmitry Baryshkov
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Continue migration to the MDSS-revision based checks and replace
DPU_INTF_INPUT_CTRL feature bit with the core_major_ver >= 5 check.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 4 ----
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 4 ----
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 6 ------
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h | 4 ----
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h | 3 ---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 2 --
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 4 ----
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 2 --
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 2 --
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 4 ----
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 3 ---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 9 ---------
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 4 ----
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 8 --------
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 4 ----
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h | 4 ----
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 9 ---------
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 ---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 11 -----------
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 2 +-
23 files changed, 1 insertion(+), 94 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
index bbdb7e1668fee33cb7d99a7cb8ab001e58f079be..88582fc257dea342f05b93dae6afe986eb7f32d0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
@@ -364,7 +364,6 @@ static const struct dpu_intf_cfg sm8650_intf[] = {
{
.name = "intf_0", .id = INTF_0,
.base = 0x34000, .len = 0x280,
- .features = INTF_SC7180_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_0,
.prog_fetch_lines_worst_case = 24,
@@ -373,7 +372,6 @@ static const struct dpu_intf_cfg sm8650_intf[] = {
}, {
.name = "intf_1", .id = INTF_1,
.base = 0x35000, .len = 0x300,
- .features = INTF_SC7180_MASK,
.type = INTF_DSI,
.controller_id = MSM_DSI_CONTROLLER_0,
.prog_fetch_lines_worst_case = 24,
@@ -383,7 +381,6 @@ static const struct dpu_intf_cfg sm8650_intf[] = {
}, {
.name = "intf_2", .id = INTF_2,
.base = 0x36000, .len = 0x300,
- .features = INTF_SC7180_MASK,
.type = INTF_DSI,
.controller_id = MSM_DSI_CONTROLLER_1,
.prog_fetch_lines_worst_case = 24,
@@ -393,7 +390,6 @@ static const struct dpu_intf_cfg sm8650_intf[] = {
}, {
.name = "intf_3", .id = INTF_3,
.base = 0x37000, .len = 0x280,
- .features = INTF_SC7180_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_1,
.prog_fetch_lines_worst_case = 24,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
index 6c8ef23099a8212f33780d27a76991e9955a9bc3..bcab869aafbe1e23e0267bbad377fc10d8c6256d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
@@ -301,7 +301,6 @@ static const struct dpu_intf_cfg sm8150_intf[] = {
{
.name = "intf_0", .id = INTF_0,
.base = 0x6a000, .len = 0x280,
- .features = INTF_SC7180_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_0,
.prog_fetch_lines_worst_case = 24,
@@ -310,7 +309,6 @@ static const struct dpu_intf_cfg sm8150_intf[] = {
}, {
.name = "intf_1", .id = INTF_1,
.base = 0x6a800, .len = 0x2bc,
- .features = INTF_SC7180_MASK,
.type = INTF_DSI,
.controller_id = MSM_DSI_CONTROLLER_0,
.prog_fetch_lines_worst_case = 24,
@@ -320,7 +318,6 @@ static const struct dpu_intf_cfg sm8150_intf[] = {
}, {
.name = "intf_2", .id = INTF_2,
.base = 0x6b000, .len = 0x2bc,
- .features = INTF_SC7180_MASK,
.type = INTF_DSI,
.controller_id = MSM_DSI_CONTROLLER_1,
.prog_fetch_lines_worst_case = 24,
@@ -330,7 +327,6 @@ static const struct dpu_intf_cfg sm8150_intf[] = {
}, {
.name = "intf_3", .id = INTF_3,
.base = 0x6b800, .len = 0x280,
- .features = INTF_SC7180_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_1,
.prog_fetch_lines_worst_case = 24,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
index 37d18803af4b850c40ab855b1f13db96f3ee96ea..4b61bc7eb79f00a184c95b2319b737fcee6c4cbb 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
@@ -309,7 +309,6 @@ static const struct dpu_intf_cfg sc8180x_intf[] = {
{
.name = "intf_0", .id = INTF_0,
.base = 0x6a000, .len = 0x280,
- .features = INTF_SC7180_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_0,
.prog_fetch_lines_worst_case = 24,
@@ -318,7 +317,6 @@ static const struct dpu_intf_cfg sc8180x_intf[] = {
}, {
.name = "intf_1", .id = INTF_1,
.base = 0x6a800, .len = 0x2bc,
- .features = INTF_SC7180_MASK,
.type = INTF_DSI,
.controller_id = MSM_DSI_CONTROLLER_0,
.prog_fetch_lines_worst_case = 24,
@@ -328,7 +326,6 @@ static const struct dpu_intf_cfg sc8180x_intf[] = {
}, {
.name = "intf_2", .id = INTF_2,
.base = 0x6b000, .len = 0x2bc,
- .features = INTF_SC7180_MASK,
.type = INTF_DSI,
.controller_id = MSM_DSI_CONTROLLER_1,
.prog_fetch_lines_worst_case = 24,
@@ -340,7 +337,6 @@ static const struct dpu_intf_cfg sc8180x_intf[] = {
{
.name = "intf_3", .id = INTF_3,
.base = 0x6b800, .len = 0x280,
- .features = INTF_SC7180_MASK,
.type = INTF_DP,
.controller_id = 999,
.prog_fetch_lines_worst_case = 24,
@@ -349,7 +345,6 @@ static const struct dpu_intf_cfg sc8180x_intf[] = {
}, {
.name = "intf_4", .id = INTF_4,
.base = 0x6c000, .len = 0x280,
- .features = INTF_SC7180_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_1,
.prog_fetch_lines_worst_case = 24,
@@ -358,7 +353,6 @@ static const struct dpu_intf_cfg sc8180x_intf[] = {
}, {
.name = "intf_5", .id = INTF_5,
.base = 0x6c800, .len = 0x280,
- .features = INTF_SC7180_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_2,
.prog_fetch_lines_worst_case = 24,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
index 41b43fb258508f1a5f285c88a3c1dc2f5f271cd0..2e7ae68f7e922e9b71d79627806042f645cb4ad2 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
@@ -210,7 +210,6 @@ static const struct dpu_intf_cfg sm7150_intf[] = {
{
.name = "intf_0", .id = INTF_0,
.base = 0x6a000, .len = 0x280,
- .features = INTF_SC7180_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_0,
.prog_fetch_lines_worst_case = 24,
@@ -219,7 +218,6 @@ static const struct dpu_intf_cfg sm7150_intf[] = {
}, {
.name = "intf_1", .id = INTF_1,
.base = 0x6a800, .len = 0x2bc,
- .features = INTF_SC7180_MASK,
.type = INTF_DSI,
.controller_id = MSM_DSI_CONTROLLER_0,
.prog_fetch_lines_worst_case = 24,
@@ -229,7 +227,6 @@ static const struct dpu_intf_cfg sm7150_intf[] = {
}, {
.name = "intf_2", .id = INTF_2,
.base = 0x6b000, .len = 0x2bc,
- .features = INTF_SC7180_MASK,
.type = INTF_DSI,
.controller_id = MSM_DSI_CONTROLLER_1,
.prog_fetch_lines_worst_case = 24,
@@ -239,7 +236,6 @@ static const struct dpu_intf_cfg sm7150_intf[] = {
}, {
.name = "intf_3", .id = INTF_3,
.base = 0x6b800, .len = 0x280,
- .features = INTF_SC7180_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_1,
.prog_fetch_lines_worst_case = 24,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
index d44db988a6e2f443803a422846f817779d382b2a..a99c99ca37703cc3a7d4403d3f026f234b693319 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
@@ -175,7 +175,6 @@ static const struct dpu_intf_cfg sm6150_intf[] = {
{
.name = "intf_0", .id = INTF_0,
.base = 0x6a000, .len = 0x280,
- .features = INTF_SC7180_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_0,
.prog_fetch_lines_worst_case = 24,
@@ -184,7 +183,6 @@ static const struct dpu_intf_cfg sm6150_intf[] = {
}, {
.name = "intf_1", .id = INTF_1,
.base = 0x6a800, .len = 0x2c0,
- .features = INTF_SC7180_MASK,
.type = INTF_DSI,
.controller_id = MSM_DSI_CONTROLLER_0,
.prog_fetch_lines_worst_case = 24,
@@ -194,7 +192,6 @@ static const struct dpu_intf_cfg sm6150_intf[] = {
}, {
.name = "intf_3", .id = INTF_3,
.base = 0x6b800, .len = 0x280,
- .features = INTF_SC7180_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_1,
.prog_fetch_lines_worst_case = 24,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
index 6e571480c4a44b4f4663574c31270657b9a06a7a..72f1328deda87ccc0b97f3f03d5840a77426b2b7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
@@ -152,7 +152,6 @@ static const struct dpu_intf_cfg sm6125_intf[] = {
{
.name = "intf_0", .id = INTF_0,
.base = 0x6a000, .len = 0x280,
- .features = INTF_SC7180_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_0,
.prog_fetch_lines_worst_case = 24,
@@ -161,7 +160,6 @@ static const struct dpu_intf_cfg sm6125_intf[] = {
}, {
.name = "intf_1", .id = INTF_1,
.base = 0x6a800, .len = 0x2c0,
- .features = INTF_SC7180_MASK,
.type = INTF_DSI,
.controller_id = 0,
.prog_fetch_lines_worst_case = 24,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
index 6f9dc261e667fca3e94ec24e00d45f9af46e401e..aee4adb3b73d2efb074abc58dff7d213a73207d9 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
@@ -284,7 +284,6 @@ static const struct dpu_intf_cfg sm8250_intf[] = {
{
.name = "intf_0", .id = INTF_0,
.base = 0x6a000, .len = 0x280,
- .features = INTF_SC7180_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_0,
.prog_fetch_lines_worst_case = 24,
@@ -293,7 +292,6 @@ static const struct dpu_intf_cfg sm8250_intf[] = {
}, {
.name = "intf_1", .id = INTF_1,
.base = 0x6a800, .len = 0x2c0,
- .features = INTF_SC7180_MASK,
.type = INTF_DSI,
.controller_id = MSM_DSI_CONTROLLER_0,
.prog_fetch_lines_worst_case = 24,
@@ -303,7 +301,6 @@ static const struct dpu_intf_cfg sm8250_intf[] = {
}, {
.name = "intf_2", .id = INTF_2,
.base = 0x6b000, .len = 0x2c0,
- .features = INTF_SC7180_MASK,
.type = INTF_DSI,
.controller_id = MSM_DSI_CONTROLLER_1,
.prog_fetch_lines_worst_case = 24,
@@ -313,7 +310,6 @@ static const struct dpu_intf_cfg sm8250_intf[] = {
}, {
.name = "intf_3", .id = INTF_3,
.base = 0x6b800, .len = 0x280,
- .features = INTF_SC7180_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_1,
.prog_fetch_lines_worst_case = 24,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
index 373c7d605a04a1fc72f45e993ec176e8f5e015fe..05c0f81b263c4a9aab8adbfa487f6cd20ce94079 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
@@ -129,7 +129,6 @@ static const struct dpu_intf_cfg sc7180_intf[] = {
{
.name = "intf_0", .id = INTF_0,
.base = 0x6a000, .len = 0x280,
- .features = INTF_SC7180_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_0,
.prog_fetch_lines_worst_case = 24,
@@ -138,7 +137,6 @@ static const struct dpu_intf_cfg sc7180_intf[] = {
}, {
.name = "intf_1", .id = INTF_1,
.base = 0x6a800, .len = 0x2c0,
- .features = INTF_SC7180_MASK,
.type = INTF_DSI,
.controller_id = MSM_DSI_CONTROLLER_0,
.prog_fetch_lines_worst_case = 24,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
index 1cf9f99d0542cf7037d2a9672d51ca7c437c364e..b729a01e8ff8443721bf993726ae9ebe21e89440 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
@@ -87,7 +87,6 @@ static const struct dpu_intf_cfg sm6115_intf[] = {
{
.name = "intf_1", .id = INTF_1,
.base = 0x6a800, .len = 0x2c0,
- .features = INTF_SC7180_MASK,
.type = INTF_DSI,
.controller_id = MSM_DSI_CONTROLLER_0,
.prog_fetch_lines_worst_case = 24,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
index a3db71676f468526ea129c4b8465fb2c47885162..25f56c55f373ef5e57082448bc1a1d1d17968b06 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
@@ -160,7 +160,6 @@ static const struct dpu_intf_cfg sm6350_intf[] = {
{
.name = "intf_0", .id = INTF_0,
.base = 0x6a000, .len = 0x280,
- .features = INTF_SC7180_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_0,
.prog_fetch_lines_worst_case = 35,
@@ -169,7 +168,6 @@ static const struct dpu_intf_cfg sm6350_intf[] = {
}, {
.name = "intf_1", .id = INTF_1,
.base = 0x6a800, .len = 0x2c0,
- .features = INTF_SC7180_MASK,
.type = INTF_DSI,
.controller_id = MSM_DSI_CONTROLLER_0,
.prog_fetch_lines_worst_case = 35,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
index 719cfaa98ab9e735d9255d9a5f1a4275739b4b1d..20b12a68fb9dfe0291486ca827c6ca25a1711014 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
@@ -87,7 +87,6 @@ static const struct dpu_intf_cfg qcm2290_intf[] = {
{
.name = "intf_1", .id = INTF_1,
.base = 0x6a800, .len = 0x2c0,
- .features = INTF_SC7180_MASK,
.type = INTF_DSI,
.controller_id = MSM_DSI_CONTROLLER_0,
.prog_fetch_lines_worst_case = 24,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
index 04cdda85e6828a83e99d146ee9d9f809f1acc007..6935ff7da3162dd7b86f3786b0f604d113e51649 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
@@ -97,7 +97,6 @@ static const struct dpu_intf_cfg sm6375_intf[] = {
{
.name = "intf_1", .id = INTF_1,
.base = 0x6a800, .len = 0x2c0,
- .features = INTF_SC7180_MASK,
.type = INTF_DSI,
.controller_id = MSM_DSI_CONTROLLER_0,
.prog_fetch_lines_worst_case = 24,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
index 3c6da0acdc3b81db65e2544f16d90322fe7e92a6..b6b1a4383efa72fc0bc8a6feac1c3adb7773ba42 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
@@ -308,7 +308,6 @@ static const struct dpu_intf_cfg sm8350_intf[] = {
{
.name = "intf_0", .id = INTF_0,
.base = 0x34000, .len = 0x280,
- .features = INTF_SC7180_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_0,
.prog_fetch_lines_worst_case = 24,
@@ -317,7 +316,6 @@ static const struct dpu_intf_cfg sm8350_intf[] = {
}, {
.name = "intf_1", .id = INTF_1,
.base = 0x35000, .len = 0x2c4,
- .features = INTF_SC7180_MASK,
.type = INTF_DSI,
.controller_id = MSM_DSI_CONTROLLER_0,
.prog_fetch_lines_worst_case = 24,
@@ -327,7 +325,6 @@ static const struct dpu_intf_cfg sm8350_intf[] = {
}, {
.name = "intf_2", .id = INTF_2,
.base = 0x36000, .len = 0x2c4,
- .features = INTF_SC7180_MASK,
.type = INTF_DSI,
.controller_id = MSM_DSI_CONTROLLER_1,
.prog_fetch_lines_worst_case = 24,
@@ -337,7 +334,6 @@ static const struct dpu_intf_cfg sm8350_intf[] = {
}, {
.name = "intf_3", .id = INTF_3,
.base = 0x37000, .len = 0x280,
- .features = INTF_SC7180_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_1,
.prog_fetch_lines_worst_case = 24,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
index 2ee29c56224596b3786104090290b88cecf7b223..d1dd895acbf666ceab39f9c38ae11bda100b5953 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
@@ -178,7 +178,6 @@ static const struct dpu_intf_cfg sc7280_intf[] = {
{
.name = "intf_0", .id = INTF_0,
.base = 0x34000, .len = 0x280,
- .features = INTF_SC7180_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_0,
.prog_fetch_lines_worst_case = 24,
@@ -187,7 +186,6 @@ static const struct dpu_intf_cfg sc7280_intf[] = {
}, {
.name = "intf_1", .id = INTF_1,
.base = 0x35000, .len = 0x2c4,
- .features = INTF_SC7180_MASK,
.type = INTF_DSI,
.controller_id = MSM_DSI_CONTROLLER_0,
.prog_fetch_lines_worst_case = 24,
@@ -197,7 +195,6 @@ static const struct dpu_intf_cfg sc7280_intf[] = {
}, {
.name = "intf_5", .id = INTF_5,
.base = 0x39000, .len = 0x280,
- .features = INTF_SC7180_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_1,
.prog_fetch_lines_worst_case = 24,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
index 2f20d0014a94e707a5f0548fc1c6bf0983b0cad0..481d36b80c4eddda53d2f9963392d9499f966792 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
@@ -304,7 +304,6 @@ static const struct dpu_intf_cfg sc8280xp_intf[] = {
{
.name = "intf_0", .id = INTF_0,
.base = 0x34000, .len = 0x280,
- .features = INTF_SC7180_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_0,
.prog_fetch_lines_worst_case = 24,
@@ -313,7 +312,6 @@ static const struct dpu_intf_cfg sc8280xp_intf[] = {
}, {
.name = "intf_1", .id = INTF_1,
.base = 0x35000, .len = 0x300,
- .features = INTF_SC7180_MASK,
.type = INTF_DSI,
.controller_id = MSM_DSI_CONTROLLER_0,
.prog_fetch_lines_worst_case = 24,
@@ -323,7 +321,6 @@ static const struct dpu_intf_cfg sc8280xp_intf[] = {
}, {
.name = "intf_2", .id = INTF_2,
.base = 0x36000, .len = 0x300,
- .features = INTF_SC7180_MASK,
.type = INTF_DSI,
.controller_id = MSM_DSI_CONTROLLER_1,
.prog_fetch_lines_worst_case = 24,
@@ -333,7 +330,6 @@ static const struct dpu_intf_cfg sc8280xp_intf[] = {
}, {
.name = "intf_3", .id = INTF_3,
.base = 0x37000, .len = 0x280,
- .features = INTF_SC7180_MASK,
.type = INTF_NONE,
.controller_id = MSM_DP_CONTROLLER_0,
.prog_fetch_lines_worst_case = 24,
@@ -342,7 +338,6 @@ static const struct dpu_intf_cfg sc8280xp_intf[] = {
}, {
.name = "intf_4", .id = INTF_4,
.base = 0x38000, .len = 0x280,
- .features = INTF_SC7180_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_1,
.prog_fetch_lines_worst_case = 24,
@@ -351,7 +346,6 @@ static const struct dpu_intf_cfg sc8280xp_intf[] = {
}, {
.name = "intf_5", .id = INTF_5,
.base = 0x39000, .len = 0x280,
- .features = INTF_SC7180_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_3,
.prog_fetch_lines_worst_case = 24,
@@ -360,7 +354,6 @@ static const struct dpu_intf_cfg sc8280xp_intf[] = {
}, {
.name = "intf_6", .id = INTF_6,
.base = 0x3a000, .len = 0x280,
- .features = INTF_SC7180_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_2,
.prog_fetch_lines_worst_case = 24,
@@ -369,7 +362,6 @@ static const struct dpu_intf_cfg sc8280xp_intf[] = {
}, {
.name = "intf_7", .id = INTF_7,
.base = 0x3b000, .len = 0x280,
- .features = INTF_SC7180_MASK,
.type = INTF_NONE,
.controller_id = MSM_DP_CONTROLLER_2,
.prog_fetch_lines_worst_case = 24,
@@ -378,7 +370,6 @@ static const struct dpu_intf_cfg sc8280xp_intf[] = {
}, {
.name = "intf_8", .id = INTF_8,
.base = 0x3c000, .len = 0x280,
- .features = INTF_SC7180_MASK,
.type = INTF_NONE,
.controller_id = MSM_DP_CONTROLLER_1,
.prog_fetch_lines_worst_case = 24,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
index 314875e2dca96b3b5c40aae0d15fb80da8ebd42c..32649f25fdcbc1fe45d7028352dfd4c0daa11d84 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
@@ -324,7 +324,6 @@ static const struct dpu_intf_cfg sm8450_intf[] = {
{
.name = "intf_0", .id = INTF_0,
.base = 0x34000, .len = 0x280,
- .features = INTF_SC7180_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_0,
.prog_fetch_lines_worst_case = 24,
@@ -333,7 +332,6 @@ static const struct dpu_intf_cfg sm8450_intf[] = {
}, {
.name = "intf_1", .id = INTF_1,
.base = 0x35000, .len = 0x300,
- .features = INTF_SC7180_MASK,
.type = INTF_DSI,
.controller_id = MSM_DSI_CONTROLLER_0,
.prog_fetch_lines_worst_case = 24,
@@ -343,7 +341,6 @@ static const struct dpu_intf_cfg sm8450_intf[] = {
}, {
.name = "intf_2", .id = INTF_2,
.base = 0x36000, .len = 0x300,
- .features = INTF_SC7180_MASK,
.type = INTF_DSI,
.controller_id = MSM_DSI_CONTROLLER_1,
.prog_fetch_lines_worst_case = 24,
@@ -353,7 +350,6 @@ static const struct dpu_intf_cfg sm8450_intf[] = {
}, {
.name = "intf_3", .id = INTF_3,
.base = 0x37000, .len = 0x280,
- .features = INTF_SC7180_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_1,
.prog_fetch_lines_worst_case = 24,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
index 36775f444af4b2654231cd9456ac4eea1f0f18e6..4679b7e47d50e21d5b6df69fd0479b804ac69979 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
@@ -334,7 +334,6 @@ static const struct dpu_intf_cfg sa8775p_intf[] = {
{
.name = "intf_0", .id = INTF_0,
.base = 0x34000, .len = 0x280,
- .features = INTF_SC7180_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_0,
.prog_fetch_lines_worst_case = 24,
@@ -343,7 +342,6 @@ static const struct dpu_intf_cfg sa8775p_intf[] = {
}, {
.name = "intf_1", .id = INTF_1,
.base = 0x35000, .len = 0x300,
- .features = INTF_SC7180_MASK,
.type = INTF_DSI,
.controller_id = MSM_DSI_CONTROLLER_0,
.prog_fetch_lines_worst_case = 24,
@@ -353,7 +351,6 @@ static const struct dpu_intf_cfg sa8775p_intf[] = {
}, {
.name = "intf_2", .id = INTF_2,
.base = 0x36000, .len = 0x300,
- .features = INTF_SC7180_MASK,
.type = INTF_DSI,
.controller_id = MSM_DSI_CONTROLLER_1,
.prog_fetch_lines_worst_case = 24,
@@ -363,7 +360,6 @@ static const struct dpu_intf_cfg sa8775p_intf[] = {
}, {
.name = "intf_3", .id = INTF_3,
.base = 0x37000, .len = 0x280,
- .features = INTF_SC7180_MASK,
.type = INTF_NONE,
.controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
.prog_fetch_lines_worst_case = 24,
@@ -372,7 +368,6 @@ static const struct dpu_intf_cfg sa8775p_intf[] = {
}, {
.name = "intf_4", .id = INTF_4,
.base = 0x38000, .len = 0x280,
- .features = INTF_SC7180_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_1,
.prog_fetch_lines_worst_case = 24,
@@ -381,7 +376,6 @@ static const struct dpu_intf_cfg sa8775p_intf[] = {
}, {
.name = "intf_6", .id = INTF_6,
.base = 0x3A000, .len = 0x280,
- .features = INTF_SC7180_MASK,
.type = INTF_NONE,
.controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
.prog_fetch_lines_worst_case = 24,
@@ -390,7 +384,6 @@ static const struct dpu_intf_cfg sa8775p_intf[] = {
}, {
.name = "intf_7", .id = INTF_7,
.base = 0x3b000, .len = 0x280,
- .features = INTF_SC7180_MASK,
.type = INTF_NONE,
.controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
.prog_fetch_lines_worst_case = 24,
@@ -399,7 +392,6 @@ static const struct dpu_intf_cfg sa8775p_intf[] = {
}, {
.name = "intf_8", .id = INTF_8,
.base = 0x3c000, .len = 0x280,
- .features = INTF_SC7180_MASK,
.type = INTF_NONE,
.controller_id = MSM_DP_CONTROLLER_1, /* pair with intf_4 for DP MST */
.prog_fetch_lines_worst_case = 24,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
index 624f24c8a33a182634d49058014fc3175f5ac9d3..def7c161d787d9cecd219b4db0482158d3e5bc12 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
@@ -319,7 +319,6 @@ static const struct dpu_intf_cfg sm8550_intf[] = {
{
.name = "intf_0", .id = INTF_0,
.base = 0x34000, .len = 0x280,
- .features = INTF_SC7180_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_0,
.prog_fetch_lines_worst_case = 24,
@@ -328,7 +327,6 @@ static const struct dpu_intf_cfg sm8550_intf[] = {
}, {
.name = "intf_1", .id = INTF_1,
.base = 0x35000, .len = 0x300,
- .features = INTF_SC7180_MASK,
.type = INTF_DSI,
.controller_id = MSM_DSI_CONTROLLER_0,
.prog_fetch_lines_worst_case = 24,
@@ -338,7 +336,6 @@ static const struct dpu_intf_cfg sm8550_intf[] = {
}, {
.name = "intf_2", .id = INTF_2,
.base = 0x36000, .len = 0x300,
- .features = INTF_SC7180_MASK,
.type = INTF_DSI,
.controller_id = MSM_DSI_CONTROLLER_1,
.prog_fetch_lines_worst_case = 24,
@@ -348,7 +345,6 @@ static const struct dpu_intf_cfg sm8550_intf[] = {
}, {
.name = "intf_3", .id = INTF_3,
.base = 0x37000, .len = 0x280,
- .features = INTF_SC7180_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_1,
.prog_fetch_lines_worst_case = 24,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
index 857dc8465bf5571cd08cf3115fb96002873c004b..979a674517d8b270309a4ce92534face0f2ba855 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
@@ -319,7 +319,6 @@ static const struct dpu_intf_cfg sar2130p_intf[] = {
{
.name = "intf_0", .id = INTF_0,
.base = 0x34000, .len = 0x280,
- .features = INTF_SC7180_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_0,
.prog_fetch_lines_worst_case = 24,
@@ -328,7 +327,6 @@ static const struct dpu_intf_cfg sar2130p_intf[] = {
}, {
.name = "intf_1", .id = INTF_1,
.base = 0x35000, .len = 0x300,
- .features = INTF_SC7180_MASK,
.type = INTF_DSI,
.controller_id = MSM_DSI_CONTROLLER_0,
.prog_fetch_lines_worst_case = 24,
@@ -338,7 +336,6 @@ static const struct dpu_intf_cfg sar2130p_intf[] = {
}, {
.name = "intf_2", .id = INTF_2,
.base = 0x36000, .len = 0x300,
- .features = INTF_SC7180_MASK,
.type = INTF_DSI,
.controller_id = MSM_DSI_CONTROLLER_1,
.prog_fetch_lines_worst_case = 24,
@@ -348,7 +345,6 @@ static const struct dpu_intf_cfg sar2130p_intf[] = {
}, {
.name = "intf_3", .id = INTF_3,
.base = 0x37000, .len = 0x280,
- .features = INTF_SC7180_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_1,
.prog_fetch_lines_worst_case = 24,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
index 05b0962c2d937f077d0b42fa8af6e2da40c7dcae..ffee0740ddb5c13dbbd2ca0d70855cba27f73ca6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
@@ -320,7 +320,6 @@ static const struct dpu_intf_cfg x1e80100_intf[] = {
{
.name = "intf_0", .id = INTF_0,
.base = 0x34000, .len = 0x280,
- .features = INTF_SC7180_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_0,
.prog_fetch_lines_worst_case = 24,
@@ -329,7 +328,6 @@ static const struct dpu_intf_cfg x1e80100_intf[] = {
}, {
.name = "intf_1", .id = INTF_1,
.base = 0x35000, .len = 0x300,
- .features = INTF_SC7180_MASK,
.type = INTF_DSI,
.controller_id = MSM_DSI_CONTROLLER_0,
.prog_fetch_lines_worst_case = 24,
@@ -339,7 +337,6 @@ static const struct dpu_intf_cfg x1e80100_intf[] = {
}, {
.name = "intf_2", .id = INTF_2,
.base = 0x36000, .len = 0x300,
- .features = INTF_SC7180_MASK,
.type = INTF_DSI,
.controller_id = MSM_DSI_CONTROLLER_1,
.prog_fetch_lines_worst_case = 24,
@@ -349,7 +346,6 @@ static const struct dpu_intf_cfg x1e80100_intf[] = {
}, {
.name = "intf_3", .id = INTF_3,
.base = 0x37000, .len = 0x280,
- .features = INTF_SC7180_MASK,
.type = INTF_NONE,
.controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
.prog_fetch_lines_worst_case = 24,
@@ -358,7 +354,6 @@ static const struct dpu_intf_cfg x1e80100_intf[] = {
}, {
.name = "intf_4", .id = INTF_4,
.base = 0x38000, .len = 0x280,
- .features = INTF_SC7180_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_1,
.prog_fetch_lines_worst_case = 24,
@@ -367,7 +362,6 @@ static const struct dpu_intf_cfg x1e80100_intf[] = {
}, {
.name = "intf_5", .id = INTF_5,
.base = 0x39000, .len = 0x280,
- .features = INTF_SC7180_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_3,
.prog_fetch_lines_worst_case = 24,
@@ -376,7 +370,6 @@ static const struct dpu_intf_cfg x1e80100_intf[] = {
}, {
.name = "intf_6", .id = INTF_6,
.base = 0x3A000, .len = 0x280,
- .features = INTF_SC7180_MASK,
.type = INTF_DP,
.controller_id = MSM_DP_CONTROLLER_2,
.prog_fetch_lines_worst_case = 24,
@@ -385,7 +378,6 @@ static const struct dpu_intf_cfg x1e80100_intf[] = {
}, {
.name = "intf_7", .id = INTF_7,
.base = 0x3b000, .len = 0x280,
- .features = INTF_SC7180_MASK,
.type = INTF_NONE,
.controller_id = MSM_DP_CONTROLLER_2, /* pair with intf_6 for DP MST */
.prog_fetch_lines_worst_case = 24,
@@ -394,7 +386,6 @@ static const struct dpu_intf_cfg x1e80100_intf[] = {
}, {
.name = "intf_8", .id = INTF_8,
.base = 0x3c000, .len = 0x280,
- .features = INTF_SC7180_MASK,
.type = INTF_NONE,
.controller_id = MSM_DP_CONTROLLER_1, /* pair with intf_4 for DP MST */
.prog_fetch_lines_worst_case = 24,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 4482f2fe6f04e58408b55994d885ea1c717c6a07..df1eeb9082f74ab734c235f0cd0baf8c0eda14b5 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -104,9 +104,6 @@
#define PINGPONG_SM8150_MASK \
(BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_DSC))
-#define INTF_SC7180_MASK \
- (BIT(DPU_INTF_INPUT_CTRL))
-
#define WB_SDM845_MASK (BIT(DPU_WB_LINE_MODE) | \
BIT(DPU_WB_UBWC) | \
BIT(DPU_WB_YUV_CONFIG) | \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index e1c6df3a3b72ffb5a816bd18266a35abe723fbd9..bc71ec9a5bc8b6e15d7af13c42ba5d4197729822 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -139,17 +139,6 @@ enum {
DPU_CTL_MAX
};
-/**
- * INTF sub-blocks
- * @DPU_INTF_INPUT_CTRL Supports the setting of pp block from which
- * pixel data arrives to this INTF
- * @DPU_INTF_MAX
- */
-enum {
- DPU_INTF_INPUT_CTRL = 0x1,
- DPU_INTF_MAX
-};
-
/**
* WB sub-blocks and features
* @DPU_WB_LINE_MODE Writeback module supports line/linear mode
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index 54c2e984ef0ce604e3eda49595d2816ea41bd7fd..a80ac82a96255da1d52e1f2fa7fc39388fc3782b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
@@ -588,7 +588,7 @@ struct dpu_hw_intf *dpu_hw_intf_init(struct drm_device *dev,
c->ops.setup_misr = dpu_hw_intf_setup_misr;
c->ops.collect_misr = dpu_hw_intf_collect_misr;
- if (cfg->features & BIT(DPU_INTF_INPUT_CTRL))
+ if (mdss_rev->core_major_ver >= 5)
c->ops.bind_pingpong_blk = dpu_hw_intf_bind_pingpong_blk;
/* INTF TE is only for DSI interfaces */
--
2.39.5
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH v4 15/30] drm/msm/dpu: get rid of DPU_INTF_INPUT_CTRL
2025-05-19 16:04 ` [PATCH v4 15/30] drm/msm/dpu: get rid of DPU_INTF_INPUT_CTRL Dmitry Baryshkov
@ 2025-05-20 7:55 ` neil.armstrong
0 siblings, 0 replies; 64+ messages in thread
From: neil.armstrong @ 2025-05-20 7:55 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Abhinav Kumar, Sean Paul,
Marijn Suijten, David Airlie, Simona Vetter, Vinod Koul,
Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel,
Dmitry Baryshkov
On 19/05/2025 18:04, Dmitry Baryshkov wrote:
> From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>
> Continue migration to the MDSS-revision based checks and replace
> DPU_INTF_INPUT_CTRL feature bit with the core_major_ver >= 5 check.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 4 ----
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 4 ----
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 6 ------
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h | 4 ----
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h | 3 ---
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 2 --
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 4 ----
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 2 --
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 1 -
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 2 --
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 1 -
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 1 -
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 4 ----
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 3 ---
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 9 ---------
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 4 ----
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 8 --------
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 4 ----
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h | 4 ----
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 9 ---------
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 11 -----------
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 2 +-
> 23 files changed, 1 insertion(+), 94 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
> index bbdb7e1668fee33cb7d99a7cb8ab001e58f079be..88582fc257dea342f05b93dae6afe986eb7f32d0 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
> @@ -364,7 +364,6 @@ static const struct dpu_intf_cfg sm8650_intf[] = {
> {
> .name = "intf_0", .id = INTF_0,
> .base = 0x34000, .len = 0x280,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DP,
> .controller_id = MSM_DP_CONTROLLER_0,
> .prog_fetch_lines_worst_case = 24,
> @@ -373,7 +372,6 @@ static const struct dpu_intf_cfg sm8650_intf[] = {
> }, {
> .name = "intf_1", .id = INTF_1,
> .base = 0x35000, .len = 0x300,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DSI,
> .controller_id = MSM_DSI_CONTROLLER_0,
> .prog_fetch_lines_worst_case = 24,
> @@ -383,7 +381,6 @@ static const struct dpu_intf_cfg sm8650_intf[] = {
> }, {
> .name = "intf_2", .id = INTF_2,
> .base = 0x36000, .len = 0x300,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DSI,
> .controller_id = MSM_DSI_CONTROLLER_1,
> .prog_fetch_lines_worst_case = 24,
> @@ -393,7 +390,6 @@ static const struct dpu_intf_cfg sm8650_intf[] = {
> }, {
> .name = "intf_3", .id = INTF_3,
> .base = 0x37000, .len = 0x280,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DP,
> .controller_id = MSM_DP_CONTROLLER_1,
> .prog_fetch_lines_worst_case = 24,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> index 6c8ef23099a8212f33780d27a76991e9955a9bc3..bcab869aafbe1e23e0267bbad377fc10d8c6256d 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> @@ -301,7 +301,6 @@ static const struct dpu_intf_cfg sm8150_intf[] = {
> {
> .name = "intf_0", .id = INTF_0,
> .base = 0x6a000, .len = 0x280,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DP,
> .controller_id = MSM_DP_CONTROLLER_0,
> .prog_fetch_lines_worst_case = 24,
> @@ -310,7 +309,6 @@ static const struct dpu_intf_cfg sm8150_intf[] = {
> }, {
> .name = "intf_1", .id = INTF_1,
> .base = 0x6a800, .len = 0x2bc,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DSI,
> .controller_id = MSM_DSI_CONTROLLER_0,
> .prog_fetch_lines_worst_case = 24,
> @@ -320,7 +318,6 @@ static const struct dpu_intf_cfg sm8150_intf[] = {
> }, {
> .name = "intf_2", .id = INTF_2,
> .base = 0x6b000, .len = 0x2bc,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DSI,
> .controller_id = MSM_DSI_CONTROLLER_1,
> .prog_fetch_lines_worst_case = 24,
> @@ -330,7 +327,6 @@ static const struct dpu_intf_cfg sm8150_intf[] = {
> }, {
> .name = "intf_3", .id = INTF_3,
> .base = 0x6b800, .len = 0x280,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DP,
> .controller_id = MSM_DP_CONTROLLER_1,
> .prog_fetch_lines_worst_case = 24,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> index 37d18803af4b850c40ab855b1f13db96f3ee96ea..4b61bc7eb79f00a184c95b2319b737fcee6c4cbb 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> @@ -309,7 +309,6 @@ static const struct dpu_intf_cfg sc8180x_intf[] = {
> {
> .name = "intf_0", .id = INTF_0,
> .base = 0x6a000, .len = 0x280,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DP,
> .controller_id = MSM_DP_CONTROLLER_0,
> .prog_fetch_lines_worst_case = 24,
> @@ -318,7 +317,6 @@ static const struct dpu_intf_cfg sc8180x_intf[] = {
> }, {
> .name = "intf_1", .id = INTF_1,
> .base = 0x6a800, .len = 0x2bc,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DSI,
> .controller_id = MSM_DSI_CONTROLLER_0,
> .prog_fetch_lines_worst_case = 24,
> @@ -328,7 +326,6 @@ static const struct dpu_intf_cfg sc8180x_intf[] = {
> }, {
> .name = "intf_2", .id = INTF_2,
> .base = 0x6b000, .len = 0x2bc,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DSI,
> .controller_id = MSM_DSI_CONTROLLER_1,
> .prog_fetch_lines_worst_case = 24,
> @@ -340,7 +337,6 @@ static const struct dpu_intf_cfg sc8180x_intf[] = {
> {
> .name = "intf_3", .id = INTF_3,
> .base = 0x6b800, .len = 0x280,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DP,
> .controller_id = 999,
> .prog_fetch_lines_worst_case = 24,
> @@ -349,7 +345,6 @@ static const struct dpu_intf_cfg sc8180x_intf[] = {
> }, {
> .name = "intf_4", .id = INTF_4,
> .base = 0x6c000, .len = 0x280,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DP,
> .controller_id = MSM_DP_CONTROLLER_1,
> .prog_fetch_lines_worst_case = 24,
> @@ -358,7 +353,6 @@ static const struct dpu_intf_cfg sc8180x_intf[] = {
> }, {
> .name = "intf_5", .id = INTF_5,
> .base = 0x6c800, .len = 0x280,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DP,
> .controller_id = MSM_DP_CONTROLLER_2,
> .prog_fetch_lines_worst_case = 24,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
> index 41b43fb258508f1a5f285c88a3c1dc2f5f271cd0..2e7ae68f7e922e9b71d79627806042f645cb4ad2 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
> @@ -210,7 +210,6 @@ static const struct dpu_intf_cfg sm7150_intf[] = {
> {
> .name = "intf_0", .id = INTF_0,
> .base = 0x6a000, .len = 0x280,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DP,
> .controller_id = MSM_DP_CONTROLLER_0,
> .prog_fetch_lines_worst_case = 24,
> @@ -219,7 +218,6 @@ static const struct dpu_intf_cfg sm7150_intf[] = {
> }, {
> .name = "intf_1", .id = INTF_1,
> .base = 0x6a800, .len = 0x2bc,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DSI,
> .controller_id = MSM_DSI_CONTROLLER_0,
> .prog_fetch_lines_worst_case = 24,
> @@ -229,7 +227,6 @@ static const struct dpu_intf_cfg sm7150_intf[] = {
> }, {
> .name = "intf_2", .id = INTF_2,
> .base = 0x6b000, .len = 0x2bc,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DSI,
> .controller_id = MSM_DSI_CONTROLLER_1,
> .prog_fetch_lines_worst_case = 24,
> @@ -239,7 +236,6 @@ static const struct dpu_intf_cfg sm7150_intf[] = {
> }, {
> .name = "intf_3", .id = INTF_3,
> .base = 0x6b800, .len = 0x280,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DP,
> .controller_id = MSM_DP_CONTROLLER_1,
> .prog_fetch_lines_worst_case = 24,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
> index d44db988a6e2f443803a422846f817779d382b2a..a99c99ca37703cc3a7d4403d3f026f234b693319 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
> @@ -175,7 +175,6 @@ static const struct dpu_intf_cfg sm6150_intf[] = {
> {
> .name = "intf_0", .id = INTF_0,
> .base = 0x6a000, .len = 0x280,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DP,
> .controller_id = MSM_DP_CONTROLLER_0,
> .prog_fetch_lines_worst_case = 24,
> @@ -184,7 +183,6 @@ static const struct dpu_intf_cfg sm6150_intf[] = {
> }, {
> .name = "intf_1", .id = INTF_1,
> .base = 0x6a800, .len = 0x2c0,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DSI,
> .controller_id = MSM_DSI_CONTROLLER_0,
> .prog_fetch_lines_worst_case = 24,
> @@ -194,7 +192,6 @@ static const struct dpu_intf_cfg sm6150_intf[] = {
> }, {
> .name = "intf_3", .id = INTF_3,
> .base = 0x6b800, .len = 0x280,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DP,
> .controller_id = MSM_DP_CONTROLLER_1,
> .prog_fetch_lines_worst_case = 24,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
> index 6e571480c4a44b4f4663574c31270657b9a06a7a..72f1328deda87ccc0b97f3f03d5840a77426b2b7 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
> @@ -152,7 +152,6 @@ static const struct dpu_intf_cfg sm6125_intf[] = {
> {
> .name = "intf_0", .id = INTF_0,
> .base = 0x6a000, .len = 0x280,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DP,
> .controller_id = MSM_DP_CONTROLLER_0,
> .prog_fetch_lines_worst_case = 24,
> @@ -161,7 +160,6 @@ static const struct dpu_intf_cfg sm6125_intf[] = {
> }, {
> .name = "intf_1", .id = INTF_1,
> .base = 0x6a800, .len = 0x2c0,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DSI,
> .controller_id = 0,
> .prog_fetch_lines_worst_case = 24,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> index 6f9dc261e667fca3e94ec24e00d45f9af46e401e..aee4adb3b73d2efb074abc58dff7d213a73207d9 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> @@ -284,7 +284,6 @@ static const struct dpu_intf_cfg sm8250_intf[] = {
> {
> .name = "intf_0", .id = INTF_0,
> .base = 0x6a000, .len = 0x280,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DP,
> .controller_id = MSM_DP_CONTROLLER_0,
> .prog_fetch_lines_worst_case = 24,
> @@ -293,7 +292,6 @@ static const struct dpu_intf_cfg sm8250_intf[] = {
> }, {
> .name = "intf_1", .id = INTF_1,
> .base = 0x6a800, .len = 0x2c0,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DSI,
> .controller_id = MSM_DSI_CONTROLLER_0,
> .prog_fetch_lines_worst_case = 24,
> @@ -303,7 +301,6 @@ static const struct dpu_intf_cfg sm8250_intf[] = {
> }, {
> .name = "intf_2", .id = INTF_2,
> .base = 0x6b000, .len = 0x2c0,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DSI,
> .controller_id = MSM_DSI_CONTROLLER_1,
> .prog_fetch_lines_worst_case = 24,
> @@ -313,7 +310,6 @@ static const struct dpu_intf_cfg sm8250_intf[] = {
> }, {
> .name = "intf_3", .id = INTF_3,
> .base = 0x6b800, .len = 0x280,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DP,
> .controller_id = MSM_DP_CONTROLLER_1,
> .prog_fetch_lines_worst_case = 24,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> index 373c7d605a04a1fc72f45e993ec176e8f5e015fe..05c0f81b263c4a9aab8adbfa487f6cd20ce94079 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> @@ -129,7 +129,6 @@ static const struct dpu_intf_cfg sc7180_intf[] = {
> {
> .name = "intf_0", .id = INTF_0,
> .base = 0x6a000, .len = 0x280,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DP,
> .controller_id = MSM_DP_CONTROLLER_0,
> .prog_fetch_lines_worst_case = 24,
> @@ -138,7 +137,6 @@ static const struct dpu_intf_cfg sc7180_intf[] = {
> }, {
> .name = "intf_1", .id = INTF_1,
> .base = 0x6a800, .len = 0x2c0,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DSI,
> .controller_id = MSM_DSI_CONTROLLER_0,
> .prog_fetch_lines_worst_case = 24,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> index 1cf9f99d0542cf7037d2a9672d51ca7c437c364e..b729a01e8ff8443721bf993726ae9ebe21e89440 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> @@ -87,7 +87,6 @@ static const struct dpu_intf_cfg sm6115_intf[] = {
> {
> .name = "intf_1", .id = INTF_1,
> .base = 0x6a800, .len = 0x2c0,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DSI,
> .controller_id = MSM_DSI_CONTROLLER_0,
> .prog_fetch_lines_worst_case = 24,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> index a3db71676f468526ea129c4b8465fb2c47885162..25f56c55f373ef5e57082448bc1a1d1d17968b06 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> @@ -160,7 +160,6 @@ static const struct dpu_intf_cfg sm6350_intf[] = {
> {
> .name = "intf_0", .id = INTF_0,
> .base = 0x6a000, .len = 0x280,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DP,
> .controller_id = MSM_DP_CONTROLLER_0,
> .prog_fetch_lines_worst_case = 35,
> @@ -169,7 +168,6 @@ static const struct dpu_intf_cfg sm6350_intf[] = {
> }, {
> .name = "intf_1", .id = INTF_1,
> .base = 0x6a800, .len = 0x2c0,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DSI,
> .controller_id = MSM_DSI_CONTROLLER_0,
> .prog_fetch_lines_worst_case = 35,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> index 719cfaa98ab9e735d9255d9a5f1a4275739b4b1d..20b12a68fb9dfe0291486ca827c6ca25a1711014 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> @@ -87,7 +87,6 @@ static const struct dpu_intf_cfg qcm2290_intf[] = {
> {
> .name = "intf_1", .id = INTF_1,
> .base = 0x6a800, .len = 0x2c0,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DSI,
> .controller_id = MSM_DSI_CONTROLLER_0,
> .prog_fetch_lines_worst_case = 24,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
> index 04cdda85e6828a83e99d146ee9d9f809f1acc007..6935ff7da3162dd7b86f3786b0f604d113e51649 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
> @@ -97,7 +97,6 @@ static const struct dpu_intf_cfg sm6375_intf[] = {
> {
> .name = "intf_1", .id = INTF_1,
> .base = 0x6a800, .len = 0x2c0,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DSI,
> .controller_id = MSM_DSI_CONTROLLER_0,
> .prog_fetch_lines_worst_case = 24,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> index 3c6da0acdc3b81db65e2544f16d90322fe7e92a6..b6b1a4383efa72fc0bc8a6feac1c3adb7773ba42 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> @@ -308,7 +308,6 @@ static const struct dpu_intf_cfg sm8350_intf[] = {
> {
> .name = "intf_0", .id = INTF_0,
> .base = 0x34000, .len = 0x280,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DP,
> .controller_id = MSM_DP_CONTROLLER_0,
> .prog_fetch_lines_worst_case = 24,
> @@ -317,7 +316,6 @@ static const struct dpu_intf_cfg sm8350_intf[] = {
> }, {
> .name = "intf_1", .id = INTF_1,
> .base = 0x35000, .len = 0x2c4,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DSI,
> .controller_id = MSM_DSI_CONTROLLER_0,
> .prog_fetch_lines_worst_case = 24,
> @@ -327,7 +325,6 @@ static const struct dpu_intf_cfg sm8350_intf[] = {
> }, {
> .name = "intf_2", .id = INTF_2,
> .base = 0x36000, .len = 0x2c4,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DSI,
> .controller_id = MSM_DSI_CONTROLLER_1,
> .prog_fetch_lines_worst_case = 24,
> @@ -337,7 +334,6 @@ static const struct dpu_intf_cfg sm8350_intf[] = {
> }, {
> .name = "intf_3", .id = INTF_3,
> .base = 0x37000, .len = 0x280,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DP,
> .controller_id = MSM_DP_CONTROLLER_1,
> .prog_fetch_lines_worst_case = 24,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> index 2ee29c56224596b3786104090290b88cecf7b223..d1dd895acbf666ceab39f9c38ae11bda100b5953 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> @@ -178,7 +178,6 @@ static const struct dpu_intf_cfg sc7280_intf[] = {
> {
> .name = "intf_0", .id = INTF_0,
> .base = 0x34000, .len = 0x280,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DP,
> .controller_id = MSM_DP_CONTROLLER_0,
> .prog_fetch_lines_worst_case = 24,
> @@ -187,7 +186,6 @@ static const struct dpu_intf_cfg sc7280_intf[] = {
> }, {
> .name = "intf_1", .id = INTF_1,
> .base = 0x35000, .len = 0x2c4,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DSI,
> .controller_id = MSM_DSI_CONTROLLER_0,
> .prog_fetch_lines_worst_case = 24,
> @@ -197,7 +195,6 @@ static const struct dpu_intf_cfg sc7280_intf[] = {
> }, {
> .name = "intf_5", .id = INTF_5,
> .base = 0x39000, .len = 0x280,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DP,
> .controller_id = MSM_DP_CONTROLLER_1,
> .prog_fetch_lines_worst_case = 24,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> index 2f20d0014a94e707a5f0548fc1c6bf0983b0cad0..481d36b80c4eddda53d2f9963392d9499f966792 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> @@ -304,7 +304,6 @@ static const struct dpu_intf_cfg sc8280xp_intf[] = {
> {
> .name = "intf_0", .id = INTF_0,
> .base = 0x34000, .len = 0x280,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DP,
> .controller_id = MSM_DP_CONTROLLER_0,
> .prog_fetch_lines_worst_case = 24,
> @@ -313,7 +312,6 @@ static const struct dpu_intf_cfg sc8280xp_intf[] = {
> }, {
> .name = "intf_1", .id = INTF_1,
> .base = 0x35000, .len = 0x300,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DSI,
> .controller_id = MSM_DSI_CONTROLLER_0,
> .prog_fetch_lines_worst_case = 24,
> @@ -323,7 +321,6 @@ static const struct dpu_intf_cfg sc8280xp_intf[] = {
> }, {
> .name = "intf_2", .id = INTF_2,
> .base = 0x36000, .len = 0x300,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DSI,
> .controller_id = MSM_DSI_CONTROLLER_1,
> .prog_fetch_lines_worst_case = 24,
> @@ -333,7 +330,6 @@ static const struct dpu_intf_cfg sc8280xp_intf[] = {
> }, {
> .name = "intf_3", .id = INTF_3,
> .base = 0x37000, .len = 0x280,
> - .features = INTF_SC7180_MASK,
> .type = INTF_NONE,
> .controller_id = MSM_DP_CONTROLLER_0,
> .prog_fetch_lines_worst_case = 24,
> @@ -342,7 +338,6 @@ static const struct dpu_intf_cfg sc8280xp_intf[] = {
> }, {
> .name = "intf_4", .id = INTF_4,
> .base = 0x38000, .len = 0x280,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DP,
> .controller_id = MSM_DP_CONTROLLER_1,
> .prog_fetch_lines_worst_case = 24,
> @@ -351,7 +346,6 @@ static const struct dpu_intf_cfg sc8280xp_intf[] = {
> }, {
> .name = "intf_5", .id = INTF_5,
> .base = 0x39000, .len = 0x280,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DP,
> .controller_id = MSM_DP_CONTROLLER_3,
> .prog_fetch_lines_worst_case = 24,
> @@ -360,7 +354,6 @@ static const struct dpu_intf_cfg sc8280xp_intf[] = {
> }, {
> .name = "intf_6", .id = INTF_6,
> .base = 0x3a000, .len = 0x280,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DP,
> .controller_id = MSM_DP_CONTROLLER_2,
> .prog_fetch_lines_worst_case = 24,
> @@ -369,7 +362,6 @@ static const struct dpu_intf_cfg sc8280xp_intf[] = {
> }, {
> .name = "intf_7", .id = INTF_7,
> .base = 0x3b000, .len = 0x280,
> - .features = INTF_SC7180_MASK,
> .type = INTF_NONE,
> .controller_id = MSM_DP_CONTROLLER_2,
> .prog_fetch_lines_worst_case = 24,
> @@ -378,7 +370,6 @@ static const struct dpu_intf_cfg sc8280xp_intf[] = {
> }, {
> .name = "intf_8", .id = INTF_8,
> .base = 0x3c000, .len = 0x280,
> - .features = INTF_SC7180_MASK,
> .type = INTF_NONE,
> .controller_id = MSM_DP_CONTROLLER_1,
> .prog_fetch_lines_worst_case = 24,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> index 314875e2dca96b3b5c40aae0d15fb80da8ebd42c..32649f25fdcbc1fe45d7028352dfd4c0daa11d84 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> @@ -324,7 +324,6 @@ static const struct dpu_intf_cfg sm8450_intf[] = {
> {
> .name = "intf_0", .id = INTF_0,
> .base = 0x34000, .len = 0x280,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DP,
> .controller_id = MSM_DP_CONTROLLER_0,
> .prog_fetch_lines_worst_case = 24,
> @@ -333,7 +332,6 @@ static const struct dpu_intf_cfg sm8450_intf[] = {
> }, {
> .name = "intf_1", .id = INTF_1,
> .base = 0x35000, .len = 0x300,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DSI,
> .controller_id = MSM_DSI_CONTROLLER_0,
> .prog_fetch_lines_worst_case = 24,
> @@ -343,7 +341,6 @@ static const struct dpu_intf_cfg sm8450_intf[] = {
> }, {
> .name = "intf_2", .id = INTF_2,
> .base = 0x36000, .len = 0x300,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DSI,
> .controller_id = MSM_DSI_CONTROLLER_1,
> .prog_fetch_lines_worst_case = 24,
> @@ -353,7 +350,6 @@ static const struct dpu_intf_cfg sm8450_intf[] = {
> }, {
> .name = "intf_3", .id = INTF_3,
> .base = 0x37000, .len = 0x280,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DP,
> .controller_id = MSM_DP_CONTROLLER_1,
> .prog_fetch_lines_worst_case = 24,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
> index 36775f444af4b2654231cd9456ac4eea1f0f18e6..4679b7e47d50e21d5b6df69fd0479b804ac69979 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
> @@ -334,7 +334,6 @@ static const struct dpu_intf_cfg sa8775p_intf[] = {
> {
> .name = "intf_0", .id = INTF_0,
> .base = 0x34000, .len = 0x280,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DP,
> .controller_id = MSM_DP_CONTROLLER_0,
> .prog_fetch_lines_worst_case = 24,
> @@ -343,7 +342,6 @@ static const struct dpu_intf_cfg sa8775p_intf[] = {
> }, {
> .name = "intf_1", .id = INTF_1,
> .base = 0x35000, .len = 0x300,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DSI,
> .controller_id = MSM_DSI_CONTROLLER_0,
> .prog_fetch_lines_worst_case = 24,
> @@ -353,7 +351,6 @@ static const struct dpu_intf_cfg sa8775p_intf[] = {
> }, {
> .name = "intf_2", .id = INTF_2,
> .base = 0x36000, .len = 0x300,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DSI,
> .controller_id = MSM_DSI_CONTROLLER_1,
> .prog_fetch_lines_worst_case = 24,
> @@ -363,7 +360,6 @@ static const struct dpu_intf_cfg sa8775p_intf[] = {
> }, {
> .name = "intf_3", .id = INTF_3,
> .base = 0x37000, .len = 0x280,
> - .features = INTF_SC7180_MASK,
> .type = INTF_NONE,
> .controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
> .prog_fetch_lines_worst_case = 24,
> @@ -372,7 +368,6 @@ static const struct dpu_intf_cfg sa8775p_intf[] = {
> }, {
> .name = "intf_4", .id = INTF_4,
> .base = 0x38000, .len = 0x280,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DP,
> .controller_id = MSM_DP_CONTROLLER_1,
> .prog_fetch_lines_worst_case = 24,
> @@ -381,7 +376,6 @@ static const struct dpu_intf_cfg sa8775p_intf[] = {
> }, {
> .name = "intf_6", .id = INTF_6,
> .base = 0x3A000, .len = 0x280,
> - .features = INTF_SC7180_MASK,
> .type = INTF_NONE,
> .controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
> .prog_fetch_lines_worst_case = 24,
> @@ -390,7 +384,6 @@ static const struct dpu_intf_cfg sa8775p_intf[] = {
> }, {
> .name = "intf_7", .id = INTF_7,
> .base = 0x3b000, .len = 0x280,
> - .features = INTF_SC7180_MASK,
> .type = INTF_NONE,
> .controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
> .prog_fetch_lines_worst_case = 24,
> @@ -399,7 +392,6 @@ static const struct dpu_intf_cfg sa8775p_intf[] = {
> }, {
> .name = "intf_8", .id = INTF_8,
> .base = 0x3c000, .len = 0x280,
> - .features = INTF_SC7180_MASK,
> .type = INTF_NONE,
> .controller_id = MSM_DP_CONTROLLER_1, /* pair with intf_4 for DP MST */
> .prog_fetch_lines_worst_case = 24,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> index 624f24c8a33a182634d49058014fc3175f5ac9d3..def7c161d787d9cecd219b4db0482158d3e5bc12 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> @@ -319,7 +319,6 @@ static const struct dpu_intf_cfg sm8550_intf[] = {
> {
> .name = "intf_0", .id = INTF_0,
> .base = 0x34000, .len = 0x280,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DP,
> .controller_id = MSM_DP_CONTROLLER_0,
> .prog_fetch_lines_worst_case = 24,
> @@ -328,7 +327,6 @@ static const struct dpu_intf_cfg sm8550_intf[] = {
> }, {
> .name = "intf_1", .id = INTF_1,
> .base = 0x35000, .len = 0x300,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DSI,
> .controller_id = MSM_DSI_CONTROLLER_0,
> .prog_fetch_lines_worst_case = 24,
> @@ -338,7 +336,6 @@ static const struct dpu_intf_cfg sm8550_intf[] = {
> }, {
> .name = "intf_2", .id = INTF_2,
> .base = 0x36000, .len = 0x300,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DSI,
> .controller_id = MSM_DSI_CONTROLLER_1,
> .prog_fetch_lines_worst_case = 24,
> @@ -348,7 +345,6 @@ static const struct dpu_intf_cfg sm8550_intf[] = {
> }, {
> .name = "intf_3", .id = INTF_3,
> .base = 0x37000, .len = 0x280,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DP,
> .controller_id = MSM_DP_CONTROLLER_1,
> .prog_fetch_lines_worst_case = 24,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
> index 857dc8465bf5571cd08cf3115fb96002873c004b..979a674517d8b270309a4ce92534face0f2ba855 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
> @@ -319,7 +319,6 @@ static const struct dpu_intf_cfg sar2130p_intf[] = {
> {
> .name = "intf_0", .id = INTF_0,
> .base = 0x34000, .len = 0x280,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DP,
> .controller_id = MSM_DP_CONTROLLER_0,
> .prog_fetch_lines_worst_case = 24,
> @@ -328,7 +327,6 @@ static const struct dpu_intf_cfg sar2130p_intf[] = {
> }, {
> .name = "intf_1", .id = INTF_1,
> .base = 0x35000, .len = 0x300,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DSI,
> .controller_id = MSM_DSI_CONTROLLER_0,
> .prog_fetch_lines_worst_case = 24,
> @@ -338,7 +336,6 @@ static const struct dpu_intf_cfg sar2130p_intf[] = {
> }, {
> .name = "intf_2", .id = INTF_2,
> .base = 0x36000, .len = 0x300,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DSI,
> .controller_id = MSM_DSI_CONTROLLER_1,
> .prog_fetch_lines_worst_case = 24,
> @@ -348,7 +345,6 @@ static const struct dpu_intf_cfg sar2130p_intf[] = {
> }, {
> .name = "intf_3", .id = INTF_3,
> .base = 0x37000, .len = 0x280,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DP,
> .controller_id = MSM_DP_CONTROLLER_1,
> .prog_fetch_lines_worst_case = 24,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
> index 05b0962c2d937f077d0b42fa8af6e2da40c7dcae..ffee0740ddb5c13dbbd2ca0d70855cba27f73ca6 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
> @@ -320,7 +320,6 @@ static const struct dpu_intf_cfg x1e80100_intf[] = {
> {
> .name = "intf_0", .id = INTF_0,
> .base = 0x34000, .len = 0x280,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DP,
> .controller_id = MSM_DP_CONTROLLER_0,
> .prog_fetch_lines_worst_case = 24,
> @@ -329,7 +328,6 @@ static const struct dpu_intf_cfg x1e80100_intf[] = {
> }, {
> .name = "intf_1", .id = INTF_1,
> .base = 0x35000, .len = 0x300,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DSI,
> .controller_id = MSM_DSI_CONTROLLER_0,
> .prog_fetch_lines_worst_case = 24,
> @@ -339,7 +337,6 @@ static const struct dpu_intf_cfg x1e80100_intf[] = {
> }, {
> .name = "intf_2", .id = INTF_2,
> .base = 0x36000, .len = 0x300,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DSI,
> .controller_id = MSM_DSI_CONTROLLER_1,
> .prog_fetch_lines_worst_case = 24,
> @@ -349,7 +346,6 @@ static const struct dpu_intf_cfg x1e80100_intf[] = {
> }, {
> .name = "intf_3", .id = INTF_3,
> .base = 0x37000, .len = 0x280,
> - .features = INTF_SC7180_MASK,
> .type = INTF_NONE,
> .controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
> .prog_fetch_lines_worst_case = 24,
> @@ -358,7 +354,6 @@ static const struct dpu_intf_cfg x1e80100_intf[] = {
> }, {
> .name = "intf_4", .id = INTF_4,
> .base = 0x38000, .len = 0x280,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DP,
> .controller_id = MSM_DP_CONTROLLER_1,
> .prog_fetch_lines_worst_case = 24,
> @@ -367,7 +362,6 @@ static const struct dpu_intf_cfg x1e80100_intf[] = {
> }, {
> .name = "intf_5", .id = INTF_5,
> .base = 0x39000, .len = 0x280,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DP,
> .controller_id = MSM_DP_CONTROLLER_3,
> .prog_fetch_lines_worst_case = 24,
> @@ -376,7 +370,6 @@ static const struct dpu_intf_cfg x1e80100_intf[] = {
> }, {
> .name = "intf_6", .id = INTF_6,
> .base = 0x3A000, .len = 0x280,
> - .features = INTF_SC7180_MASK,
> .type = INTF_DP,
> .controller_id = MSM_DP_CONTROLLER_2,
> .prog_fetch_lines_worst_case = 24,
> @@ -385,7 +378,6 @@ static const struct dpu_intf_cfg x1e80100_intf[] = {
> }, {
> .name = "intf_7", .id = INTF_7,
> .base = 0x3b000, .len = 0x280,
> - .features = INTF_SC7180_MASK,
> .type = INTF_NONE,
> .controller_id = MSM_DP_CONTROLLER_2, /* pair with intf_6 for DP MST */
> .prog_fetch_lines_worst_case = 24,
> @@ -394,7 +386,6 @@ static const struct dpu_intf_cfg x1e80100_intf[] = {
> }, {
> .name = "intf_8", .id = INTF_8,
> .base = 0x3c000, .len = 0x280,
> - .features = INTF_SC7180_MASK,
> .type = INTF_NONE,
> .controller_id = MSM_DP_CONTROLLER_1, /* pair with intf_4 for DP MST */
> .prog_fetch_lines_worst_case = 24,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index 4482f2fe6f04e58408b55994d885ea1c717c6a07..df1eeb9082f74ab734c235f0cd0baf8c0eda14b5 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -104,9 +104,6 @@
> #define PINGPONG_SM8150_MASK \
> (BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_DSC))
>
> -#define INTF_SC7180_MASK \
> - (BIT(DPU_INTF_INPUT_CTRL))
> -
> #define WB_SDM845_MASK (BIT(DPU_WB_LINE_MODE) | \
> BIT(DPU_WB_UBWC) | \
> BIT(DPU_WB_YUV_CONFIG) | \
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index e1c6df3a3b72ffb5a816bd18266a35abe723fbd9..bc71ec9a5bc8b6e15d7af13c42ba5d4197729822 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -139,17 +139,6 @@ enum {
> DPU_CTL_MAX
> };
>
> -/**
> - * INTF sub-blocks
> - * @DPU_INTF_INPUT_CTRL Supports the setting of pp block from which
> - * pixel data arrives to this INTF
> - * @DPU_INTF_MAX
> - */
> -enum {
> - DPU_INTF_INPUT_CTRL = 0x1,
> - DPU_INTF_MAX
> -};
> -
> /**
> * WB sub-blocks and features
> * @DPU_WB_LINE_MODE Writeback module supports line/linear mode
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> index 54c2e984ef0ce604e3eda49595d2816ea41bd7fd..a80ac82a96255da1d52e1f2fa7fc39388fc3782b 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> @@ -588,7 +588,7 @@ struct dpu_hw_intf *dpu_hw_intf_init(struct drm_device *dev,
> c->ops.setup_misr = dpu_hw_intf_setup_misr;
> c->ops.collect_misr = dpu_hw_intf_collect_misr;
>
> - if (cfg->features & BIT(DPU_INTF_INPUT_CTRL))
> + if (mdss_rev->core_major_ver >= 5)
> c->ops.bind_pingpong_blk = dpu_hw_intf_bind_pingpong_blk;
>
> /* INTF TE is only for DSI interfaces */
>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH v4 16/30] drm/msm/dpu: get rid of DPU_PINGPONG_DSC
2025-05-19 16:04 [PATCH v4 00/30] drm/msm/dpu: rework HW block feature handling Dmitry Baryshkov
` (14 preceding siblings ...)
2025-05-19 16:04 ` [PATCH v4 15/30] drm/msm/dpu: get rid of DPU_INTF_INPUT_CTRL Dmitry Baryshkov
@ 2025-05-19 16:04 ` Dmitry Baryshkov
2025-05-20 7:54 ` neil.armstrong
2025-05-19 16:04 ` [PATCH v4 17/30] drm/msm/dpu: get rid of DPU_PINGPONG_DITHER Dmitry Baryshkov
` (13 subsequent siblings)
29 siblings, 1 reply; 64+ messages in thread
From: Dmitry Baryshkov @ 2025-05-19 16:04 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Sean Paul, Marijn Suijten, David Airlie,
Simona Vetter, Vinod Koul, Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel,
Dmitry Baryshkov
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Continue migration to the MDSS-revision based checks and replace
DPU_PINGPONG_DSC feature bit with the core_major_ver < 7 check.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h | 4 ----
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 7 ++-----
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 --
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 2 +-
4 files changed, 3 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
index 8fe07a5683f734a058e7e7250f0811e3b7b7cf07..0e8e71775f2c1c38af018353c85ffeb6ccddb42f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
@@ -181,28 +181,24 @@ static const struct dpu_pingpong_cfg msm8996_pp[] = {
{
.name = "pingpong_0", .id = PINGPONG_0,
.base = 0x70000, .len = 0xd4,
- .features = PINGPONG_MSM8996_MASK,
.sblk = &msm8996_pp_sblk,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
}, {
.name = "pingpong_1", .id = PINGPONG_1,
.base = 0x70800, .len = 0xd4,
- .features = PINGPONG_MSM8996_MASK,
.sblk = &msm8996_pp_sblk,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13),
}, {
.name = "pingpong_2", .id = PINGPONG_2,
.base = 0x71000, .len = 0xd4,
- .features = PINGPONG_MSM8996_MASK,
.sblk = &msm8996_pp_sblk,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14),
}, {
.name = "pingpong_3", .id = PINGPONG_3,
.base = 0x71800, .len = 0xd4,
- .features = PINGPONG_MSM8996_MASK,
.sblk = &msm8996_pp_sblk,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index df1eeb9082f74ab734c235f0cd0baf8c0eda14b5..75b679cd2bd27dd25971489a2d3a6f516b248235 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -95,14 +95,11 @@
#define MIXER_QCM2290_MASK \
(BIT(DPU_DIM_LAYER) | BIT(DPU_MIXER_COMBINED_ALPHA))
-#define PINGPONG_MSM8996_MASK \
- (BIT(DPU_PINGPONG_DSC))
-
#define PINGPONG_SDM845_MASK \
- (BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_DSC))
+ (BIT(DPU_PINGPONG_DITHER))
#define PINGPONG_SM8150_MASK \
- (BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_DSC))
+ (BIT(DPU_PINGPONG_DITHER))
#define WB_SDM845_MASK (BIT(DPU_WB_LINE_MODE) | \
BIT(DPU_WB_UBWC) | \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index bc71ec9a5bc8b6e15d7af13c42ba5d4197729822..ac63f753b43615f7c34d2da51fce919fd77142bf 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -118,14 +118,12 @@ enum {
* @DPU_PINGPONG_SPLIT PP block supports split fifo
* @DPU_PINGPONG_SLAVE PP block is a suitable slave for split fifo
* @DPU_PINGPONG_DITHER Dither blocks
- * @DPU_PINGPONG_DSC PP block supports DSC
* @DPU_PINGPONG_MAX
*/
enum {
DPU_PINGPONG_SPLIT = 0x1,
DPU_PINGPONG_SLAVE,
DPU_PINGPONG_DITHER,
- DPU_PINGPONG_DSC,
DPU_PINGPONG_MAX
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
index 36c0ec775b92036eaab26e1fa5331579651ac27c..49e03ecee9e8b567a3f809b977deb83731006ac0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
@@ -319,7 +319,7 @@ struct dpu_hw_pingpong *dpu_hw_pingpong_init(struct drm_device *dev,
c->ops.disable_autorefresh = dpu_hw_pp_disable_autorefresh;
}
- if (test_bit(DPU_PINGPONG_DSC, &cfg->features)) {
+ if (mdss_rev->core_major_ver < 7) {
c->ops.setup_dsc = dpu_hw_pp_setup_dsc;
c->ops.enable_dsc = dpu_hw_pp_dsc_enable;
c->ops.disable_dsc = dpu_hw_pp_dsc_disable;
--
2.39.5
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH v4 16/30] drm/msm/dpu: get rid of DPU_PINGPONG_DSC
2025-05-19 16:04 ` [PATCH v4 16/30] drm/msm/dpu: get rid of DPU_PINGPONG_DSC Dmitry Baryshkov
@ 2025-05-20 7:54 ` neil.armstrong
0 siblings, 0 replies; 64+ messages in thread
From: neil.armstrong @ 2025-05-20 7:54 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Abhinav Kumar, Sean Paul,
Marijn Suijten, David Airlie, Simona Vetter, Vinod Koul,
Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel,
Dmitry Baryshkov
On 19/05/2025 18:04, Dmitry Baryshkov wrote:
> From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>
> Continue migration to the MDSS-revision based checks and replace
> DPU_PINGPONG_DSC feature bit with the core_major_ver < 7 check.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h | 4 ----
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 7 ++-----
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 --
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 2 +-
> 4 files changed, 3 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
> index 8fe07a5683f734a058e7e7250f0811e3b7b7cf07..0e8e71775f2c1c38af018353c85ffeb6ccddb42f 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
> @@ -181,28 +181,24 @@ static const struct dpu_pingpong_cfg msm8996_pp[] = {
> {
> .name = "pingpong_0", .id = PINGPONG_0,
> .base = 0x70000, .len = 0xd4,
> - .features = PINGPONG_MSM8996_MASK,
> .sblk = &msm8996_pp_sblk,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
> }, {
> .name = "pingpong_1", .id = PINGPONG_1,
> .base = 0x70800, .len = 0xd4,
> - .features = PINGPONG_MSM8996_MASK,
> .sblk = &msm8996_pp_sblk,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13),
> }, {
> .name = "pingpong_2", .id = PINGPONG_2,
> .base = 0x71000, .len = 0xd4,
> - .features = PINGPONG_MSM8996_MASK,
> .sblk = &msm8996_pp_sblk,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
> .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14),
> }, {
> .name = "pingpong_3", .id = PINGPONG_3,
> .base = 0x71800, .len = 0xd4,
> - .features = PINGPONG_MSM8996_MASK,
> .sblk = &msm8996_pp_sblk,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
> .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15),
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index df1eeb9082f74ab734c235f0cd0baf8c0eda14b5..75b679cd2bd27dd25971489a2d3a6f516b248235 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -95,14 +95,11 @@
> #define MIXER_QCM2290_MASK \
> (BIT(DPU_DIM_LAYER) | BIT(DPU_MIXER_COMBINED_ALPHA))
>
> -#define PINGPONG_MSM8996_MASK \
> - (BIT(DPU_PINGPONG_DSC))
> -
> #define PINGPONG_SDM845_MASK \
> - (BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_DSC))
> + (BIT(DPU_PINGPONG_DITHER))
>
> #define PINGPONG_SM8150_MASK \
> - (BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_DSC))
> + (BIT(DPU_PINGPONG_DITHER))
>
> #define WB_SDM845_MASK (BIT(DPU_WB_LINE_MODE) | \
> BIT(DPU_WB_UBWC) | \
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index bc71ec9a5bc8b6e15d7af13c42ba5d4197729822..ac63f753b43615f7c34d2da51fce919fd77142bf 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -118,14 +118,12 @@ enum {
> * @DPU_PINGPONG_SPLIT PP block supports split fifo
> * @DPU_PINGPONG_SLAVE PP block is a suitable slave for split fifo
> * @DPU_PINGPONG_DITHER Dither blocks
> - * @DPU_PINGPONG_DSC PP block supports DSC
> * @DPU_PINGPONG_MAX
> */
> enum {
> DPU_PINGPONG_SPLIT = 0x1,
> DPU_PINGPONG_SLAVE,
> DPU_PINGPONG_DITHER,
> - DPU_PINGPONG_DSC,
> DPU_PINGPONG_MAX
> };
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
> index 36c0ec775b92036eaab26e1fa5331579651ac27c..49e03ecee9e8b567a3f809b977deb83731006ac0 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
> @@ -319,7 +319,7 @@ struct dpu_hw_pingpong *dpu_hw_pingpong_init(struct drm_device *dev,
> c->ops.disable_autorefresh = dpu_hw_pp_disable_autorefresh;
> }
>
> - if (test_bit(DPU_PINGPONG_DSC, &cfg->features)) {
> + if (mdss_rev->core_major_ver < 7) {
> c->ops.setup_dsc = dpu_hw_pp_setup_dsc;
> c->ops.enable_dsc = dpu_hw_pp_dsc_enable;
> c->ops.disable_dsc = dpu_hw_pp_dsc_disable;
>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH v4 17/30] drm/msm/dpu: get rid of DPU_PINGPONG_DITHER
2025-05-19 16:04 [PATCH v4 00/30] drm/msm/dpu: rework HW block feature handling Dmitry Baryshkov
` (15 preceding siblings ...)
2025-05-19 16:04 ` [PATCH v4 16/30] drm/msm/dpu: get rid of DPU_PINGPONG_DSC Dmitry Baryshkov
@ 2025-05-19 16:04 ` Dmitry Baryshkov
2025-05-20 7:54 ` neil.armstrong
2025-05-19 16:04 ` [PATCH v4 18/30] drm/msm/dpu: get rid of DPU_MDP_VSYNC_SEL Dmitry Baryshkov
` (12 subsequent siblings)
29 siblings, 1 reply; 64+ messages in thread
From: Dmitry Baryshkov @ 2025-05-19 16:04 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Sean Paul, Marijn Suijten, David Airlie,
Simona Vetter, Vinod Koul, Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel,
Dmitry Baryshkov
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Continue migration to the MDSS-revision based checks and replace
DPU_PINGPONG_DITHER feature bit with the core_major_ver >= 3 check.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 10 ----------
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 4 ----
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h | 4 ----
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h | 2 --
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 4 ----
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 6 ------
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 6 ------
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h | 4 ----
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h | 3 ---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 2 --
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 6 ------
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 2 --
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 2 --
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 6 ------
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 4 ----
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 6 ------
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 8 --------
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 8 --------
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 8 --------
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h | 8 --------
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 8 --------
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 6 ------
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 --
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 2 +-
27 files changed, 1 insertion(+), 123 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
index 88582fc257dea342f05b93dae6afe986eb7f32d0..37c88b393c12d8a04395b6e5dffb67211d2db9cd 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
@@ -203,67 +203,57 @@ static const struct dpu_pingpong_cfg sm8650_pp[] = {
{
.name = "pingpong_0", .id = PINGPONG_0,
.base = 0x69000, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_0,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
}, {
.name = "pingpong_1", .id = PINGPONG_1,
.base = 0x6a000, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_0,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
}, {
.name = "pingpong_2", .id = PINGPONG_2,
.base = 0x6b000, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_1,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
}, {
.name = "pingpong_3", .id = PINGPONG_3,
.base = 0x6c000, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_1,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
}, {
.name = "pingpong_4", .id = PINGPONG_4,
.base = 0x6d000, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_2,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
}, {
.name = "pingpong_5", .id = PINGPONG_5,
.base = 0x6e000, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_2,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
}, {
.name = "pingpong_cwb_0", .id = PINGPONG_CWB_0,
.base = 0x66000, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_3,
}, {
.name = "pingpong_cwb_1", .id = PINGPONG_CWB_1,
.base = 0x66400, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_3,
}, {
.name = "pingpong_cwb_2", .id = PINGPONG_CWB_2,
.base = 0x7e000, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_4,
}, {
.name = "pingpong_cwb_3", .id = PINGPONG_CWB_3,
.base = 0x7e400, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_4,
},
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
index 91285519c540025abce5c51f2f28442ed9d479b0..f2ec30837f9ccbff1041f0465d0123382a00355a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
@@ -170,28 +170,24 @@ static const struct dpu_pingpong_cfg msm8998_pp[] = {
{
.name = "pingpong_0", .id = PINGPONG_0,
.base = 0x70000, .len = 0xd4,
- .features = PINGPONG_SDM845_MASK,
.sblk = &sdm845_pp_sblk,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
}, {
.name = "pingpong_1", .id = PINGPONG_1,
.base = 0x70800, .len = 0xd4,
- .features = PINGPONG_SDM845_MASK,
.sblk = &sdm845_pp_sblk,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13),
}, {
.name = "pingpong_2", .id = PINGPONG_2,
.base = 0x71000, .len = 0xd4,
- .features = PINGPONG_SDM845_MASK,
.sblk = &sdm845_pp_sblk,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14),
}, {
.name = "pingpong_3", .id = PINGPONG_3,
.base = 0x71800, .len = 0xd4,
- .features = PINGPONG_SDM845_MASK,
.sblk = &sdm845_pp_sblk,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h
index 50e0e3aec23c02acc1ce2d2a8a5658d6d49a62ac..26f39acd82e07c71cbeaaa72c14d9b7e14d2dcc3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h
@@ -141,28 +141,24 @@ static const struct dpu_pingpong_cfg sdm660_pp[] = {
{
.name = "pingpong_0", .id = PINGPONG_0,
.base = 0x70000, .len = 0xd4,
- .features = PINGPONG_SDM845_MASK,
.sblk = &sdm845_pp_sblk,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
}, {
.name = "pingpong_1", .id = PINGPONG_1,
.base = 0x70800, .len = 0xd4,
- .features = PINGPONG_SDM845_MASK,
.sblk = &sdm845_pp_sblk,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13),
}, {
.name = "pingpong_2", .id = PINGPONG_2,
.base = 0x71000, .len = 0xd4,
- .features = PINGPONG_SDM845_MASK,
.sblk = &sdm845_pp_sblk,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14),
}, {
.name = "pingpong_3", .id = PINGPONG_3,
.base = 0x71800, .len = 0xd4,
- .features = PINGPONG_SDM845_MASK,
.sblk = &sdm845_pp_sblk,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h
index 1c299491e61f0465a164be74b7a754435f347cb6..657f733c9ffff73f9eb5051ba55ed2e4e7bb496d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h
@@ -115,14 +115,12 @@ static const struct dpu_pingpong_cfg sdm630_pp[] = {
{
.name = "pingpong_0", .id = PINGPONG_0,
.base = 0x70000, .len = 0xd4,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sdm845_pp_sblk,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
}, {
.name = "pingpong_2", .id = PINGPONG_2,
.base = 0x71000, .len = 0xd4,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sdm845_pp_sblk,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
index 50e40405a5271ea6b12caa7a931ff7fe3f2478a8..15da5ded19267711e6df8605d576539475fe634c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
@@ -190,28 +190,24 @@ static const struct dpu_pingpong_cfg sdm845_pp[] = {
{
.name = "pingpong_0", .id = PINGPONG_0,
.base = 0x70000, .len = 0xd4,
- .features = PINGPONG_SDM845_MASK,
.sblk = &sdm845_pp_sblk,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
}, {
.name = "pingpong_1", .id = PINGPONG_1,
.base = 0x70800, .len = 0xd4,
- .features = PINGPONG_SDM845_MASK,
.sblk = &sdm845_pp_sblk,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13),
}, {
.name = "pingpong_2", .id = PINGPONG_2,
.base = 0x71000, .len = 0xd4,
- .features = PINGPONG_SDM845_MASK,
.sblk = &sdm845_pp_sblk,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14),
}, {
.name = "pingpong_3", .id = PINGPONG_3,
.base = 0x71800, .len = 0xd4,
- .features = PINGPONG_SDM845_MASK,
.sblk = &sdm845_pp_sblk,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
.intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
index bcab869aafbe1e23e0267bbad377fc10d8c6256d..e07c2cc4188bb12e2253068ca8666ce9364c69c1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
@@ -207,42 +207,36 @@ static const struct dpu_pingpong_cfg sm8150_pp[] = {
{
.name = "pingpong_0", .id = PINGPONG_0,
.base = 0x70000, .len = 0xd4,
- .features = PINGPONG_SM8150_MASK,
.sblk = &sdm845_pp_sblk,
.merge_3d = MERGE_3D_0,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
}, {
.name = "pingpong_1", .id = PINGPONG_1,
.base = 0x70800, .len = 0xd4,
- .features = PINGPONG_SM8150_MASK,
.sblk = &sdm845_pp_sblk,
.merge_3d = MERGE_3D_0,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
}, {
.name = "pingpong_2", .id = PINGPONG_2,
.base = 0x71000, .len = 0xd4,
- .features = PINGPONG_SM8150_MASK,
.sblk = &sdm845_pp_sblk,
.merge_3d = MERGE_3D_1,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
}, {
.name = "pingpong_3", .id = PINGPONG_3,
.base = 0x71800, .len = 0xd4,
- .features = PINGPONG_SM8150_MASK,
.sblk = &sdm845_pp_sblk,
.merge_3d = MERGE_3D_1,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
}, {
.name = "pingpong_4", .id = PINGPONG_4,
.base = 0x72000, .len = 0xd4,
- .features = PINGPONG_SM8150_MASK,
.sblk = &sdm845_pp_sblk,
.merge_3d = MERGE_3D_2,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
}, {
.name = "pingpong_5", .id = PINGPONG_5,
.base = 0x72800, .len = 0xd4,
- .features = PINGPONG_SM8150_MASK,
.sblk = &sdm845_pp_sblk,
.merge_3d = MERGE_3D_2,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
index 4b61bc7eb79f00a184c95b2319b737fcee6c4cbb..b350dba28caed77e542d6a41ceac191a93e165a7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
@@ -207,42 +207,36 @@ static const struct dpu_pingpong_cfg sc8180x_pp[] = {
{
.name = "pingpong_0", .id = PINGPONG_0,
.base = 0x70000, .len = 0xd4,
- .features = PINGPONG_SM8150_MASK,
.sblk = &sdm845_pp_sblk,
.merge_3d = MERGE_3D_0,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
}, {
.name = "pingpong_1", .id = PINGPONG_1,
.base = 0x70800, .len = 0xd4,
- .features = PINGPONG_SM8150_MASK,
.sblk = &sdm845_pp_sblk,
.merge_3d = MERGE_3D_0,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
}, {
.name = "pingpong_2", .id = PINGPONG_2,
.base = 0x71000, .len = 0xd4,
- .features = PINGPONG_SM8150_MASK,
.sblk = &sdm845_pp_sblk,
.merge_3d = MERGE_3D_1,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
}, {
.name = "pingpong_3", .id = PINGPONG_3,
.base = 0x71800, .len = 0xd4,
- .features = PINGPONG_SM8150_MASK,
.sblk = &sdm845_pp_sblk,
.merge_3d = MERGE_3D_1,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
}, {
.name = "pingpong_4", .id = PINGPONG_4,
.base = 0x72000, .len = 0xd4,
- .features = PINGPONG_SM8150_MASK,
.sblk = &sdm845_pp_sblk,
.merge_3d = MERGE_3D_2,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
}, {
.name = "pingpong_5", .id = PINGPONG_5,
.base = 0x72800, .len = 0xd4,
- .features = PINGPONG_SM8150_MASK,
.sblk = &sdm845_pp_sblk,
.merge_3d = MERGE_3D_2,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
index 2e7ae68f7e922e9b71d79627806042f645cb4ad2..27c71a8a1f31921e5e1f4b6b15e0efc25fb63537 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
@@ -156,28 +156,24 @@ static const struct dpu_pingpong_cfg sm7150_pp[] = {
{
.name = "pingpong_0", .id = PINGPONG_0,
.base = 0x70000, .len = 0xd4,
- .features = PINGPONG_SM8150_MASK,
.sblk = &sdm845_pp_sblk,
.merge_3d = MERGE_3D_0,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
}, {
.name = "pingpong_1", .id = PINGPONG_1,
.base = 0x70800, .len = 0xd4,
- .features = PINGPONG_SM8150_MASK,
.sblk = &sdm845_pp_sblk,
.merge_3d = MERGE_3D_0,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
}, {
.name = "pingpong_2", .id = PINGPONG_2,
.base = 0x71000, .len = 0xd4,
- .features = PINGPONG_SM8150_MASK,
.sblk = &sdm845_pp_sblk,
.merge_3d = MERGE_3D_1,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
}, {
.name = "pingpong_3", .id = PINGPONG_3,
.base = 0x71800, .len = 0xd4,
- .features = PINGPONG_SM8150_MASK,
.sblk = &sdm845_pp_sblk,
.merge_3d = MERGE_3D_1,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
index a99c99ca37703cc3a7d4403d3f026f234b693319..e2306d314ef8f8b59078a8ca8c529f2e56385c98 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
@@ -138,19 +138,16 @@ static const struct dpu_pingpong_cfg sm6150_pp[] = {
{
.name = "pingpong_0", .id = PINGPONG_0,
.base = 0x70000, .len = 0xd4,
- .features = PINGPONG_SM8150_MASK,
.sblk = &sdm845_pp_sblk,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
}, {
.name = "pingpong_1", .id = PINGPONG_1,
.base = 0x70800, .len = 0xd4,
- .features = PINGPONG_SM8150_MASK,
.sblk = &sdm845_pp_sblk,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
}, {
.name = "pingpong_2", .id = PINGPONG_2,
.base = 0x71000, .len = 0xd4,
- .features = PINGPONG_SM8150_MASK,
.sblk = &sdm845_pp_sblk,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
},
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
index 72f1328deda87ccc0b97f3f03d5840a77426b2b7..62136811a530a6072accbd1ab3e02e7e24220ccb 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
@@ -119,14 +119,12 @@ static const struct dpu_pingpong_cfg sm6125_pp[] = {
{
.name = "pingpong_0", .id = PINGPONG_0,
.base = 0x70000, .len = 0xd4,
- .features = PINGPONG_SM8150_MASK,
.merge_3d = 0,
.sblk = &sdm845_pp_sblk,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
}, {
.name = "pingpong_1", .id = PINGPONG_1,
.base = 0x70800, .len = 0xd4,
- .features = PINGPONG_SM8150_MASK,
.merge_3d = 0,
.sblk = &sdm845_pp_sblk,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
index aee4adb3b73d2efb074abc58dff7d213a73207d9..34f11fb084c02cf994c272196299bb9f7bced4f1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
@@ -205,42 +205,36 @@ static const struct dpu_pingpong_cfg sm8250_pp[] = {
{
.name = "pingpong_0", .id = PINGPONG_0,
.base = 0x70000, .len = 0xd4,
- .features = PINGPONG_SM8150_MASK,
.sblk = &sdm845_pp_sblk,
.merge_3d = MERGE_3D_0,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
}, {
.name = "pingpong_1", .id = PINGPONG_1,
.base = 0x70800, .len = 0xd4,
- .features = PINGPONG_SM8150_MASK,
.sblk = &sdm845_pp_sblk,
.merge_3d = MERGE_3D_0,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
}, {
.name = "pingpong_2", .id = PINGPONG_2,
.base = 0x71000, .len = 0xd4,
- .features = PINGPONG_SM8150_MASK,
.sblk = &sdm845_pp_sblk,
.merge_3d = MERGE_3D_1,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
}, {
.name = "pingpong_3", .id = PINGPONG_3,
.base = 0x71800, .len = 0xd4,
- .features = PINGPONG_SM8150_MASK,
.sblk = &sdm845_pp_sblk,
.merge_3d = MERGE_3D_1,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
}, {
.name = "pingpong_4", .id = PINGPONG_4,
.base = 0x72000, .len = 0xd4,
- .features = PINGPONG_SM8150_MASK,
.sblk = &sdm845_pp_sblk,
.merge_3d = MERGE_3D_2,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
}, {
.name = "pingpong_5", .id = PINGPONG_5,
.base = 0x72800, .len = 0xd4,
- .features = PINGPONG_SM8150_MASK,
.sblk = &sdm845_pp_sblk,
.merge_3d = MERGE_3D_2,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
index 05c0f81b263c4a9aab8adbfa487f6cd20ce94079..135b4f8171360493e58a1945105f8722d513d720 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
@@ -111,14 +111,12 @@ static const struct dpu_pingpong_cfg sc7180_pp[] = {
{
.name = "pingpong_0", .id = PINGPONG_0,
.base = 0x70000, .len = 0xd4,
- .features = PINGPONG_SM8150_MASK,
.sblk = &sdm845_pp_sblk,
.merge_3d = 0,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
}, {
.name = "pingpong_1", .id = PINGPONG_1,
.base = 0x70800, .len = 0xd4,
- .features = PINGPONG_SM8150_MASK,
.sblk = &sdm845_pp_sblk,
.merge_3d = 0,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
index b729a01e8ff8443721bf993726ae9ebe21e89440..1189a5ecb3b7b50430eb275280c2309ee9d90b63 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
@@ -76,7 +76,6 @@ static const struct dpu_pingpong_cfg sm6115_pp[] = {
{
.name = "pingpong_0", .id = PINGPONG_0,
.base = 0x70000, .len = 0xd4,
- .features = PINGPONG_SM8150_MASK,
.sblk = &sdm845_pp_sblk,
.merge_3d = 0,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
index 25f56c55f373ef5e57082448bc1a1d1d17968b06..13ff6bdcc517fd566e7701f7a7cefe5ff19c5421 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
@@ -119,14 +119,12 @@ static struct dpu_pingpong_cfg sm6350_pp[] = {
{
.name = "pingpong_0", .id = PINGPONG_0,
.base = 0x70000, .len = 0xd4,
- .features = PINGPONG_SM8150_MASK,
.sblk = &sdm845_pp_sblk,
.merge_3d = 0,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
}, {
.name = "pingpong_1", .id = PINGPONG_1,
.base = 0x70800, .len = 0xd4,
- .features = PINGPONG_SM8150_MASK,
.sblk = &sdm845_pp_sblk,
.merge_3d = 0,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
index 20b12a68fb9dfe0291486ca827c6ca25a1711014..d4c2d2da91aac0bce46c4d65079f01484a769ae3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
@@ -76,7 +76,6 @@ static const struct dpu_pingpong_cfg qcm2290_pp[] = {
{
.name = "pingpong_0", .id = PINGPONG_0,
.base = 0x70000, .len = 0xd4,
- .features = PINGPONG_SM8150_MASK,
.sblk = &sdm845_pp_sblk,
.merge_3d = 0,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
index 6935ff7da3162dd7b86f3786b0f604d113e51649..9135853a0225fa60acb80d17f627153d25c612e6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
@@ -78,7 +78,6 @@ static const struct dpu_pingpong_cfg sm6375_pp[] = {
{
.name = "pingpong_0", .id = PINGPONG_0,
.base = 0x70000, .len = 0xd4,
- .features = PINGPONG_SM8150_MASK,
.sblk = &sdm845_pp_sblk,
.merge_3d = 0,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
index b6b1a4383efa72fc0bc8a6feac1c3adb7773ba42..6503f11f65c11806c5b9558a0f9fd05b228340be 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
@@ -205,42 +205,36 @@ static const struct dpu_pingpong_cfg sm8350_pp[] = {
{
.name = "pingpong_0", .id = PINGPONG_0,
.base = 0x69000, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_0,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
}, {
.name = "pingpong_1", .id = PINGPONG_1,
.base = 0x6a000, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_0,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
}, {
.name = "pingpong_2", .id = PINGPONG_2,
.base = 0x6b000, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_1,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
}, {
.name = "pingpong_3", .id = PINGPONG_3,
.base = 0x6c000, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_1,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
}, {
.name = "pingpong_4", .id = PINGPONG_4,
.base = 0x6d000, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_2,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
}, {
.name = "pingpong_5", .id = PINGPONG_5,
.base = 0x6e000, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_2,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
index d1dd895acbf666ceab39f9c38ae11bda100b5953..202de6f9b0c65c6f2caa9e9d5232f5b92d8bdf01 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
@@ -121,28 +121,24 @@ static const struct dpu_pingpong_cfg sc7280_pp[] = {
{
.name = "pingpong_0", .id = PINGPONG_0,
.base = 0x69000, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = 0,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
}, {
.name = "pingpong_1", .id = PINGPONG_1,
.base = 0x6a000, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = 0,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
}, {
.name = "pingpong_2", .id = PINGPONG_2,
.base = 0x6b000, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = 0,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
}, {
.name = "pingpong_3", .id = PINGPONG_3,
.base = 0x6c000, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = 0,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
index 481d36b80c4eddda53d2f9963392d9499f966792..785ca2b2e60f073b0a2db0c0c4ed3b2722de033c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
@@ -205,42 +205,36 @@ static const struct dpu_pingpong_cfg sc8280xp_pp[] = {
{
.name = "pingpong_0", .id = PINGPONG_0,
.base = 0x69000, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_0,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
}, {
.name = "pingpong_1", .id = PINGPONG_1,
.base = 0x6a000, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_0,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
}, {
.name = "pingpong_2", .id = PINGPONG_2,
.base = 0x6b000, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_1,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
}, {
.name = "pingpong_3", .id = PINGPONG_3,
.base = 0x6c000, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_1,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
}, {
.name = "pingpong_4", .id = PINGPONG_4,
.base = 0x6d000, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_2,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
}, {
.name = "pingpong_5", .id = PINGPONG_5,
.base = 0x6e000, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_2,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
index 32649f25fdcbc1fe45d7028352dfd4c0daa11d84..1401a84e0da5754fd2a3661d1421bb9b998271ca 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
@@ -206,55 +206,47 @@ static const struct dpu_pingpong_cfg sm8450_pp[] = {
{
.name = "pingpong_0", .id = PINGPONG_0,
.base = 0x69000, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_0,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
}, {
.name = "pingpong_1", .id = PINGPONG_1,
.base = 0x6a000, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_0,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
}, {
.name = "pingpong_2", .id = PINGPONG_2,
.base = 0x6b000, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_1,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
}, {
.name = "pingpong_3", .id = PINGPONG_3,
.base = 0x6c000, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_1,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
}, {
.name = "pingpong_4", .id = PINGPONG_4,
.base = 0x6d000, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_2,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
}, {
.name = "pingpong_5", .id = PINGPONG_5,
.base = 0x6e000, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_2,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
}, {
.name = "pingpong_cwb_0", .id = PINGPONG_CWB_0,
.base = 0x65800, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_3,
}, {
.name = "pingpong_cwb_1", .id = PINGPONG_CWB_1,
.base = 0x65c00, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_3,
},
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
index 4679b7e47d50e21d5b6df69fd0479b804ac69979..fbbdce36f0ad99d0b1d32d90627ff5b7f3fc2fc9 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
@@ -205,55 +205,47 @@ static const struct dpu_pingpong_cfg sa8775p_pp[] = {
{
.name = "pingpong_0", .id = PINGPONG_0,
.base = 0x69000, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_0,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
}, {
.name = "pingpong_1", .id = PINGPONG_1,
.base = 0x6a000, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_0,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
}, {
.name = "pingpong_2", .id = PINGPONG_2,
.base = 0x6b000, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_1,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
}, {
.name = "pingpong_3", .id = PINGPONG_3,
.base = 0x6c000, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_1,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
}, {
.name = "pingpong_4", .id = PINGPONG_4,
.base = 0x6d000, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_2,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
}, {
.name = "pingpong_5", .id = PINGPONG_5,
.base = 0x6e000, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_2,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
}, {
.name = "pingpong_6", .id = PINGPONG_CWB_0,
.base = 0x65800, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_3,
}, {
.name = "pingpong_7", .id = PINGPONG_CWB_1,
.base = 0x65c00, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_3,
},
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
index def7c161d787d9cecd219b4db0482158d3e5bc12..cc4413432cfdc636e38a56011d39f18d7e94c23a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
@@ -202,55 +202,47 @@ static const struct dpu_pingpong_cfg sm8550_pp[] = {
{
.name = "pingpong_0", .id = PINGPONG_0,
.base = 0x69000, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_0,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
}, {
.name = "pingpong_1", .id = PINGPONG_1,
.base = 0x6a000, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_0,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
}, {
.name = "pingpong_2", .id = PINGPONG_2,
.base = 0x6b000, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_1,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
}, {
.name = "pingpong_3", .id = PINGPONG_3,
.base = 0x6c000, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_1,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
}, {
.name = "pingpong_4", .id = PINGPONG_4,
.base = 0x6d000, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_2,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
}, {
.name = "pingpong_5", .id = PINGPONG_5,
.base = 0x6e000, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_2,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
}, {
.name = "pingpong_cwb_0", .id = PINGPONG_CWB_0,
.base = 0x66000, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_3,
}, {
.name = "pingpong_cwb_1", .id = PINGPONG_CWB_1,
.base = 0x66400, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_3,
},
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
index 979a674517d8b270309a4ce92534face0f2ba855..32f88533154584dc98a515b1ddef27ab2005fecd 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
@@ -202,55 +202,47 @@ static const struct dpu_pingpong_cfg sar2130p_pp[] = {
{
.name = "pingpong_0", .id = PINGPONG_0,
.base = 0x69000, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_0,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
}, {
.name = "pingpong_1", .id = PINGPONG_1,
.base = 0x6a000, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_0,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
}, {
.name = "pingpong_2", .id = PINGPONG_2,
.base = 0x6b000, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_1,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
}, {
.name = "pingpong_3", .id = PINGPONG_3,
.base = 0x6c000, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_1,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
}, {
.name = "pingpong_4", .id = PINGPONG_4,
.base = 0x6d000, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_2,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
}, {
.name = "pingpong_5", .id = PINGPONG_5,
.base = 0x6e000, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_2,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
}, {
.name = "pingpong_cwb_0", .id = PINGPONG_CWB_0,
.base = 0x66000, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_3,
}, {
.name = "pingpong_cwb_1", .id = PINGPONG_CWB_1,
.base = 0x66400, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_3,
},
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
index ffee0740ddb5c13dbbd2ca0d70855cba27f73ca6..e053324d76a2e5020e6a7477ddadc9f7d94fe57e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
@@ -202,55 +202,47 @@ static const struct dpu_pingpong_cfg x1e80100_pp[] = {
{
.name = "pingpong_0", .id = PINGPONG_0,
.base = 0x69000, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_0,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
}, {
.name = "pingpong_1", .id = PINGPONG_1,
.base = 0x6a000, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_0,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
}, {
.name = "pingpong_2", .id = PINGPONG_2,
.base = 0x6b000, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_1,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
}, {
.name = "pingpong_3", .id = PINGPONG_3,
.base = 0x6c000, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_1,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
}, {
.name = "pingpong_4", .id = PINGPONG_4,
.base = 0x6d000, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_2,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
}, {
.name = "pingpong_5", .id = PINGPONG_5,
.base = 0x6e000, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_2,
.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
}, {
.name = "pingpong_cwb_0", .id = PINGPONG_CWB_0,
.base = 0x66000, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_3,
}, {
.name = "pingpong_cwb_1", .id = PINGPONG_CWB_1,
.base = 0x66400, .len = 0,
- .features = BIT(DPU_PINGPONG_DITHER),
.sblk = &sc7280_pp_sblk,
.merge_3d = MERGE_3D_3,
},
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 75b679cd2bd27dd25971489a2d3a6f516b248235..4777a4a852da0d65e20cebc31fd05647e0b4c4b2 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -95,12 +95,6 @@
#define MIXER_QCM2290_MASK \
(BIT(DPU_DIM_LAYER) | BIT(DPU_MIXER_COMBINED_ALPHA))
-#define PINGPONG_SDM845_MASK \
- (BIT(DPU_PINGPONG_DITHER))
-
-#define PINGPONG_SM8150_MASK \
- (BIT(DPU_PINGPONG_DITHER))
-
#define WB_SDM845_MASK (BIT(DPU_WB_LINE_MODE) | \
BIT(DPU_WB_UBWC) | \
BIT(DPU_WB_YUV_CONFIG) | \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index ac63f753b43615f7c34d2da51fce919fd77142bf..d48c26a7cb6b69961cebc19576e3f7fc3b8dd2c5 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -117,13 +117,11 @@ enum {
* PINGPONG sub-blocks
* @DPU_PINGPONG_SPLIT PP block supports split fifo
* @DPU_PINGPONG_SLAVE PP block is a suitable slave for split fifo
- * @DPU_PINGPONG_DITHER Dither blocks
* @DPU_PINGPONG_MAX
*/
enum {
DPU_PINGPONG_SPLIT = 0x1,
DPU_PINGPONG_SLAVE,
- DPU_PINGPONG_DITHER,
DPU_PINGPONG_MAX
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
index 49e03ecee9e8b567a3f809b977deb83731006ac0..138071be56496da9fdcaff902f68ebb09a212e2e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
@@ -325,7 +325,7 @@ struct dpu_hw_pingpong *dpu_hw_pingpong_init(struct drm_device *dev,
c->ops.disable_dsc = dpu_hw_pp_dsc_disable;
}
- if (test_bit(DPU_PINGPONG_DITHER, &cfg->features))
+ if (mdss_rev->core_major_ver >= 3)
c->ops.setup_dither = dpu_hw_pp_setup_dither;
return c;
--
2.39.5
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH v4 17/30] drm/msm/dpu: get rid of DPU_PINGPONG_DITHER
2025-05-19 16:04 ` [PATCH v4 17/30] drm/msm/dpu: get rid of DPU_PINGPONG_DITHER Dmitry Baryshkov
@ 2025-05-20 7:54 ` neil.armstrong
0 siblings, 0 replies; 64+ messages in thread
From: neil.armstrong @ 2025-05-20 7:54 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Abhinav Kumar, Sean Paul,
Marijn Suijten, David Airlie, Simona Vetter, Vinod Koul,
Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel,
Dmitry Baryshkov
On 19/05/2025 18:04, Dmitry Baryshkov wrote:
> From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>
> Continue migration to the MDSS-revision based checks and replace
> DPU_PINGPONG_DITHER feature bit with the core_major_ver >= 3 check.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 10 ----------
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 4 ----
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h | 4 ----
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h | 2 --
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 4 ----
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 6 ------
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 6 ------
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h | 4 ----
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h | 3 ---
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 2 --
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 6 ------
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 2 --
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 1 -
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 2 --
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 1 -
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 1 -
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 6 ------
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 4 ----
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 6 ------
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 8 --------
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 8 --------
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 8 --------
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h | 8 --------
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 8 --------
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 6 ------
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 --
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 2 +-
> 27 files changed, 1 insertion(+), 123 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
> index 88582fc257dea342f05b93dae6afe986eb7f32d0..37c88b393c12d8a04395b6e5dffb67211d2db9cd 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
> @@ -203,67 +203,57 @@ static const struct dpu_pingpong_cfg sm8650_pp[] = {
> {
> .name = "pingpong_0", .id = PINGPONG_0,
> .base = 0x69000, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_0,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> }, {
> .name = "pingpong_1", .id = PINGPONG_1,
> .base = 0x6a000, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_0,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> }, {
> .name = "pingpong_2", .id = PINGPONG_2,
> .base = 0x6b000, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_1,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
> }, {
> .name = "pingpong_3", .id = PINGPONG_3,
> .base = 0x6c000, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_1,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
> }, {
> .name = "pingpong_4", .id = PINGPONG_4,
> .base = 0x6d000, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_2,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
> }, {
> .name = "pingpong_5", .id = PINGPONG_5,
> .base = 0x6e000, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_2,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
> }, {
> .name = "pingpong_cwb_0", .id = PINGPONG_CWB_0,
> .base = 0x66000, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_3,
> }, {
> .name = "pingpong_cwb_1", .id = PINGPONG_CWB_1,
> .base = 0x66400, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_3,
> }, {
> .name = "pingpong_cwb_2", .id = PINGPONG_CWB_2,
> .base = 0x7e000, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_4,
> }, {
> .name = "pingpong_cwb_3", .id = PINGPONG_CWB_3,
> .base = 0x7e400, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_4,
> },
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> index 91285519c540025abce5c51f2f28442ed9d479b0..f2ec30837f9ccbff1041f0465d0123382a00355a 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> @@ -170,28 +170,24 @@ static const struct dpu_pingpong_cfg msm8998_pp[] = {
> {
> .name = "pingpong_0", .id = PINGPONG_0,
> .base = 0x70000, .len = 0xd4,
> - .features = PINGPONG_SDM845_MASK,
> .sblk = &sdm845_pp_sblk,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
> }, {
> .name = "pingpong_1", .id = PINGPONG_1,
> .base = 0x70800, .len = 0xd4,
> - .features = PINGPONG_SDM845_MASK,
> .sblk = &sdm845_pp_sblk,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13),
> }, {
> .name = "pingpong_2", .id = PINGPONG_2,
> .base = 0x71000, .len = 0xd4,
> - .features = PINGPONG_SDM845_MASK,
> .sblk = &sdm845_pp_sblk,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
> .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14),
> }, {
> .name = "pingpong_3", .id = PINGPONG_3,
> .base = 0x71800, .len = 0xd4,
> - .features = PINGPONG_SDM845_MASK,
> .sblk = &sdm845_pp_sblk,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
> .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15),
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h
> index 50e0e3aec23c02acc1ce2d2a8a5658d6d49a62ac..26f39acd82e07c71cbeaaa72c14d9b7e14d2dcc3 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h
> @@ -141,28 +141,24 @@ static const struct dpu_pingpong_cfg sdm660_pp[] = {
> {
> .name = "pingpong_0", .id = PINGPONG_0,
> .base = 0x70000, .len = 0xd4,
> - .features = PINGPONG_SDM845_MASK,
> .sblk = &sdm845_pp_sblk,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
> }, {
> .name = "pingpong_1", .id = PINGPONG_1,
> .base = 0x70800, .len = 0xd4,
> - .features = PINGPONG_SDM845_MASK,
> .sblk = &sdm845_pp_sblk,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13),
> }, {
> .name = "pingpong_2", .id = PINGPONG_2,
> .base = 0x71000, .len = 0xd4,
> - .features = PINGPONG_SDM845_MASK,
> .sblk = &sdm845_pp_sblk,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
> .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14),
> }, {
> .name = "pingpong_3", .id = PINGPONG_3,
> .base = 0x71800, .len = 0xd4,
> - .features = PINGPONG_SDM845_MASK,
> .sblk = &sdm845_pp_sblk,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
> .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15),
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h
> index 1c299491e61f0465a164be74b7a754435f347cb6..657f733c9ffff73f9eb5051ba55ed2e4e7bb496d 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h
> @@ -115,14 +115,12 @@ static const struct dpu_pingpong_cfg sdm630_pp[] = {
> {
> .name = "pingpong_0", .id = PINGPONG_0,
> .base = 0x70000, .len = 0xd4,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sdm845_pp_sblk,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
> }, {
> .name = "pingpong_2", .id = PINGPONG_2,
> .base = 0x71000, .len = 0xd4,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sdm845_pp_sblk,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
> .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14),
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> index 50e40405a5271ea6b12caa7a931ff7fe3f2478a8..15da5ded19267711e6df8605d576539475fe634c 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> @@ -190,28 +190,24 @@ static const struct dpu_pingpong_cfg sdm845_pp[] = {
> {
> .name = "pingpong_0", .id = PINGPONG_0,
> .base = 0x70000, .len = 0xd4,
> - .features = PINGPONG_SDM845_MASK,
> .sblk = &sdm845_pp_sblk,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
> }, {
> .name = "pingpong_1", .id = PINGPONG_1,
> .base = 0x70800, .len = 0xd4,
> - .features = PINGPONG_SDM845_MASK,
> .sblk = &sdm845_pp_sblk,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13),
> }, {
> .name = "pingpong_2", .id = PINGPONG_2,
> .base = 0x71000, .len = 0xd4,
> - .features = PINGPONG_SDM845_MASK,
> .sblk = &sdm845_pp_sblk,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
> .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14),
> }, {
> .name = "pingpong_3", .id = PINGPONG_3,
> .base = 0x71800, .len = 0xd4,
> - .features = PINGPONG_SDM845_MASK,
> .sblk = &sdm845_pp_sblk,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
> .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15),
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> index bcab869aafbe1e23e0267bbad377fc10d8c6256d..e07c2cc4188bb12e2253068ca8666ce9364c69c1 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> @@ -207,42 +207,36 @@ static const struct dpu_pingpong_cfg sm8150_pp[] = {
> {
> .name = "pingpong_0", .id = PINGPONG_0,
> .base = 0x70000, .len = 0xd4,
> - .features = PINGPONG_SM8150_MASK,
> .sblk = &sdm845_pp_sblk,
> .merge_3d = MERGE_3D_0,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> }, {
> .name = "pingpong_1", .id = PINGPONG_1,
> .base = 0x70800, .len = 0xd4,
> - .features = PINGPONG_SM8150_MASK,
> .sblk = &sdm845_pp_sblk,
> .merge_3d = MERGE_3D_0,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> }, {
> .name = "pingpong_2", .id = PINGPONG_2,
> .base = 0x71000, .len = 0xd4,
> - .features = PINGPONG_SM8150_MASK,
> .sblk = &sdm845_pp_sblk,
> .merge_3d = MERGE_3D_1,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
> }, {
> .name = "pingpong_3", .id = PINGPONG_3,
> .base = 0x71800, .len = 0xd4,
> - .features = PINGPONG_SM8150_MASK,
> .sblk = &sdm845_pp_sblk,
> .merge_3d = MERGE_3D_1,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
> }, {
> .name = "pingpong_4", .id = PINGPONG_4,
> .base = 0x72000, .len = 0xd4,
> - .features = PINGPONG_SM8150_MASK,
> .sblk = &sdm845_pp_sblk,
> .merge_3d = MERGE_3D_2,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
> }, {
> .name = "pingpong_5", .id = PINGPONG_5,
> .base = 0x72800, .len = 0xd4,
> - .features = PINGPONG_SM8150_MASK,
> .sblk = &sdm845_pp_sblk,
> .merge_3d = MERGE_3D_2,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> index 4b61bc7eb79f00a184c95b2319b737fcee6c4cbb..b350dba28caed77e542d6a41ceac191a93e165a7 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> @@ -207,42 +207,36 @@ static const struct dpu_pingpong_cfg sc8180x_pp[] = {
> {
> .name = "pingpong_0", .id = PINGPONG_0,
> .base = 0x70000, .len = 0xd4,
> - .features = PINGPONG_SM8150_MASK,
> .sblk = &sdm845_pp_sblk,
> .merge_3d = MERGE_3D_0,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> }, {
> .name = "pingpong_1", .id = PINGPONG_1,
> .base = 0x70800, .len = 0xd4,
> - .features = PINGPONG_SM8150_MASK,
> .sblk = &sdm845_pp_sblk,
> .merge_3d = MERGE_3D_0,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> }, {
> .name = "pingpong_2", .id = PINGPONG_2,
> .base = 0x71000, .len = 0xd4,
> - .features = PINGPONG_SM8150_MASK,
> .sblk = &sdm845_pp_sblk,
> .merge_3d = MERGE_3D_1,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
> }, {
> .name = "pingpong_3", .id = PINGPONG_3,
> .base = 0x71800, .len = 0xd4,
> - .features = PINGPONG_SM8150_MASK,
> .sblk = &sdm845_pp_sblk,
> .merge_3d = MERGE_3D_1,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
> }, {
> .name = "pingpong_4", .id = PINGPONG_4,
> .base = 0x72000, .len = 0xd4,
> - .features = PINGPONG_SM8150_MASK,
> .sblk = &sdm845_pp_sblk,
> .merge_3d = MERGE_3D_2,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
> }, {
> .name = "pingpong_5", .id = PINGPONG_5,
> .base = 0x72800, .len = 0xd4,
> - .features = PINGPONG_SM8150_MASK,
> .sblk = &sdm845_pp_sblk,
> .merge_3d = MERGE_3D_2,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
> index 2e7ae68f7e922e9b71d79627806042f645cb4ad2..27c71a8a1f31921e5e1f4b6b15e0efc25fb63537 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
> @@ -156,28 +156,24 @@ static const struct dpu_pingpong_cfg sm7150_pp[] = {
> {
> .name = "pingpong_0", .id = PINGPONG_0,
> .base = 0x70000, .len = 0xd4,
> - .features = PINGPONG_SM8150_MASK,
> .sblk = &sdm845_pp_sblk,
> .merge_3d = MERGE_3D_0,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> }, {
> .name = "pingpong_1", .id = PINGPONG_1,
> .base = 0x70800, .len = 0xd4,
> - .features = PINGPONG_SM8150_MASK,
> .sblk = &sdm845_pp_sblk,
> .merge_3d = MERGE_3D_0,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> }, {
> .name = "pingpong_2", .id = PINGPONG_2,
> .base = 0x71000, .len = 0xd4,
> - .features = PINGPONG_SM8150_MASK,
> .sblk = &sdm845_pp_sblk,
> .merge_3d = MERGE_3D_1,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
> }, {
> .name = "pingpong_3", .id = PINGPONG_3,
> .base = 0x71800, .len = 0xd4,
> - .features = PINGPONG_SM8150_MASK,
> .sblk = &sdm845_pp_sblk,
> .merge_3d = MERGE_3D_1,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
> index a99c99ca37703cc3a7d4403d3f026f234b693319..e2306d314ef8f8b59078a8ca8c529f2e56385c98 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
> @@ -138,19 +138,16 @@ static const struct dpu_pingpong_cfg sm6150_pp[] = {
> {
> .name = "pingpong_0", .id = PINGPONG_0,
> .base = 0x70000, .len = 0xd4,
> - .features = PINGPONG_SM8150_MASK,
> .sblk = &sdm845_pp_sblk,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> }, {
> .name = "pingpong_1", .id = PINGPONG_1,
> .base = 0x70800, .len = 0xd4,
> - .features = PINGPONG_SM8150_MASK,
> .sblk = &sdm845_pp_sblk,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> }, {
> .name = "pingpong_2", .id = PINGPONG_2,
> .base = 0x71000, .len = 0xd4,
> - .features = PINGPONG_SM8150_MASK,
> .sblk = &sdm845_pp_sblk,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
> },
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
> index 72f1328deda87ccc0b97f3f03d5840a77426b2b7..62136811a530a6072accbd1ab3e02e7e24220ccb 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
> @@ -119,14 +119,12 @@ static const struct dpu_pingpong_cfg sm6125_pp[] = {
> {
> .name = "pingpong_0", .id = PINGPONG_0,
> .base = 0x70000, .len = 0xd4,
> - .features = PINGPONG_SM8150_MASK,
> .merge_3d = 0,
> .sblk = &sdm845_pp_sblk,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> }, {
> .name = "pingpong_1", .id = PINGPONG_1,
> .base = 0x70800, .len = 0xd4,
> - .features = PINGPONG_SM8150_MASK,
> .merge_3d = 0,
> .sblk = &sdm845_pp_sblk,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> index aee4adb3b73d2efb074abc58dff7d213a73207d9..34f11fb084c02cf994c272196299bb9f7bced4f1 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> @@ -205,42 +205,36 @@ static const struct dpu_pingpong_cfg sm8250_pp[] = {
> {
> .name = "pingpong_0", .id = PINGPONG_0,
> .base = 0x70000, .len = 0xd4,
> - .features = PINGPONG_SM8150_MASK,
> .sblk = &sdm845_pp_sblk,
> .merge_3d = MERGE_3D_0,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> }, {
> .name = "pingpong_1", .id = PINGPONG_1,
> .base = 0x70800, .len = 0xd4,
> - .features = PINGPONG_SM8150_MASK,
> .sblk = &sdm845_pp_sblk,
> .merge_3d = MERGE_3D_0,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> }, {
> .name = "pingpong_2", .id = PINGPONG_2,
> .base = 0x71000, .len = 0xd4,
> - .features = PINGPONG_SM8150_MASK,
> .sblk = &sdm845_pp_sblk,
> .merge_3d = MERGE_3D_1,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
> }, {
> .name = "pingpong_3", .id = PINGPONG_3,
> .base = 0x71800, .len = 0xd4,
> - .features = PINGPONG_SM8150_MASK,
> .sblk = &sdm845_pp_sblk,
> .merge_3d = MERGE_3D_1,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
> }, {
> .name = "pingpong_4", .id = PINGPONG_4,
> .base = 0x72000, .len = 0xd4,
> - .features = PINGPONG_SM8150_MASK,
> .sblk = &sdm845_pp_sblk,
> .merge_3d = MERGE_3D_2,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
> }, {
> .name = "pingpong_5", .id = PINGPONG_5,
> .base = 0x72800, .len = 0xd4,
> - .features = PINGPONG_SM8150_MASK,
> .sblk = &sdm845_pp_sblk,
> .merge_3d = MERGE_3D_2,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> index 05c0f81b263c4a9aab8adbfa487f6cd20ce94079..135b4f8171360493e58a1945105f8722d513d720 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> @@ -111,14 +111,12 @@ static const struct dpu_pingpong_cfg sc7180_pp[] = {
> {
> .name = "pingpong_0", .id = PINGPONG_0,
> .base = 0x70000, .len = 0xd4,
> - .features = PINGPONG_SM8150_MASK,
> .sblk = &sdm845_pp_sblk,
> .merge_3d = 0,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> }, {
> .name = "pingpong_1", .id = PINGPONG_1,
> .base = 0x70800, .len = 0xd4,
> - .features = PINGPONG_SM8150_MASK,
> .sblk = &sdm845_pp_sblk,
> .merge_3d = 0,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> index b729a01e8ff8443721bf993726ae9ebe21e89440..1189a5ecb3b7b50430eb275280c2309ee9d90b63 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> @@ -76,7 +76,6 @@ static const struct dpu_pingpong_cfg sm6115_pp[] = {
> {
> .name = "pingpong_0", .id = PINGPONG_0,
> .base = 0x70000, .len = 0xd4,
> - .features = PINGPONG_SM8150_MASK,
> .sblk = &sdm845_pp_sblk,
> .merge_3d = 0,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> index 25f56c55f373ef5e57082448bc1a1d1d17968b06..13ff6bdcc517fd566e7701f7a7cefe5ff19c5421 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> @@ -119,14 +119,12 @@ static struct dpu_pingpong_cfg sm6350_pp[] = {
> {
> .name = "pingpong_0", .id = PINGPONG_0,
> .base = 0x70000, .len = 0xd4,
> - .features = PINGPONG_SM8150_MASK,
> .sblk = &sdm845_pp_sblk,
> .merge_3d = 0,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> }, {
> .name = "pingpong_1", .id = PINGPONG_1,
> .base = 0x70800, .len = 0xd4,
> - .features = PINGPONG_SM8150_MASK,
> .sblk = &sdm845_pp_sblk,
> .merge_3d = 0,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> index 20b12a68fb9dfe0291486ca827c6ca25a1711014..d4c2d2da91aac0bce46c4d65079f01484a769ae3 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> @@ -76,7 +76,6 @@ static const struct dpu_pingpong_cfg qcm2290_pp[] = {
> {
> .name = "pingpong_0", .id = PINGPONG_0,
> .base = 0x70000, .len = 0xd4,
> - .features = PINGPONG_SM8150_MASK,
> .sblk = &sdm845_pp_sblk,
> .merge_3d = 0,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
> index 6935ff7da3162dd7b86f3786b0f604d113e51649..9135853a0225fa60acb80d17f627153d25c612e6 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
> @@ -78,7 +78,6 @@ static const struct dpu_pingpong_cfg sm6375_pp[] = {
> {
> .name = "pingpong_0", .id = PINGPONG_0,
> .base = 0x70000, .len = 0xd4,
> - .features = PINGPONG_SM8150_MASK,
> .sblk = &sdm845_pp_sblk,
> .merge_3d = 0,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> index b6b1a4383efa72fc0bc8a6feac1c3adb7773ba42..6503f11f65c11806c5b9558a0f9fd05b228340be 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> @@ -205,42 +205,36 @@ static const struct dpu_pingpong_cfg sm8350_pp[] = {
> {
> .name = "pingpong_0", .id = PINGPONG_0,
> .base = 0x69000, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_0,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> }, {
> .name = "pingpong_1", .id = PINGPONG_1,
> .base = 0x6a000, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_0,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> }, {
> .name = "pingpong_2", .id = PINGPONG_2,
> .base = 0x6b000, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_1,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
> }, {
> .name = "pingpong_3", .id = PINGPONG_3,
> .base = 0x6c000, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_1,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
> }, {
> .name = "pingpong_4", .id = PINGPONG_4,
> .base = 0x6d000, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_2,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
> }, {
> .name = "pingpong_5", .id = PINGPONG_5,
> .base = 0x6e000, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_2,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> index d1dd895acbf666ceab39f9c38ae11bda100b5953..202de6f9b0c65c6f2caa9e9d5232f5b92d8bdf01 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> @@ -121,28 +121,24 @@ static const struct dpu_pingpong_cfg sc7280_pp[] = {
> {
> .name = "pingpong_0", .id = PINGPONG_0,
> .base = 0x69000, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = 0,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> }, {
> .name = "pingpong_1", .id = PINGPONG_1,
> .base = 0x6a000, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = 0,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> }, {
> .name = "pingpong_2", .id = PINGPONG_2,
> .base = 0x6b000, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = 0,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
> }, {
> .name = "pingpong_3", .id = PINGPONG_3,
> .base = 0x6c000, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = 0,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> index 481d36b80c4eddda53d2f9963392d9499f966792..785ca2b2e60f073b0a2db0c0c4ed3b2722de033c 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> @@ -205,42 +205,36 @@ static const struct dpu_pingpong_cfg sc8280xp_pp[] = {
> {
> .name = "pingpong_0", .id = PINGPONG_0,
> .base = 0x69000, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_0,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> }, {
> .name = "pingpong_1", .id = PINGPONG_1,
> .base = 0x6a000, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_0,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> }, {
> .name = "pingpong_2", .id = PINGPONG_2,
> .base = 0x6b000, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_1,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
> }, {
> .name = "pingpong_3", .id = PINGPONG_3,
> .base = 0x6c000, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_1,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
> }, {
> .name = "pingpong_4", .id = PINGPONG_4,
> .base = 0x6d000, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_2,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
> }, {
> .name = "pingpong_5", .id = PINGPONG_5,
> .base = 0x6e000, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_2,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> index 32649f25fdcbc1fe45d7028352dfd4c0daa11d84..1401a84e0da5754fd2a3661d1421bb9b998271ca 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> @@ -206,55 +206,47 @@ static const struct dpu_pingpong_cfg sm8450_pp[] = {
> {
> .name = "pingpong_0", .id = PINGPONG_0,
> .base = 0x69000, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_0,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> }, {
> .name = "pingpong_1", .id = PINGPONG_1,
> .base = 0x6a000, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_0,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> }, {
> .name = "pingpong_2", .id = PINGPONG_2,
> .base = 0x6b000, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_1,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
> }, {
> .name = "pingpong_3", .id = PINGPONG_3,
> .base = 0x6c000, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_1,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
> }, {
> .name = "pingpong_4", .id = PINGPONG_4,
> .base = 0x6d000, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_2,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
> }, {
> .name = "pingpong_5", .id = PINGPONG_5,
> .base = 0x6e000, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_2,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
> }, {
> .name = "pingpong_cwb_0", .id = PINGPONG_CWB_0,
> .base = 0x65800, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_3,
> }, {
> .name = "pingpong_cwb_1", .id = PINGPONG_CWB_1,
> .base = 0x65c00, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_3,
> },
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
> index 4679b7e47d50e21d5b6df69fd0479b804ac69979..fbbdce36f0ad99d0b1d32d90627ff5b7f3fc2fc9 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
> @@ -205,55 +205,47 @@ static const struct dpu_pingpong_cfg sa8775p_pp[] = {
> {
> .name = "pingpong_0", .id = PINGPONG_0,
> .base = 0x69000, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_0,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> }, {
> .name = "pingpong_1", .id = PINGPONG_1,
> .base = 0x6a000, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_0,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> }, {
> .name = "pingpong_2", .id = PINGPONG_2,
> .base = 0x6b000, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_1,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
> }, {
> .name = "pingpong_3", .id = PINGPONG_3,
> .base = 0x6c000, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_1,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
> }, {
> .name = "pingpong_4", .id = PINGPONG_4,
> .base = 0x6d000, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_2,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
> }, {
> .name = "pingpong_5", .id = PINGPONG_5,
> .base = 0x6e000, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_2,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
> }, {
> .name = "pingpong_6", .id = PINGPONG_CWB_0,
> .base = 0x65800, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_3,
> }, {
> .name = "pingpong_7", .id = PINGPONG_CWB_1,
> .base = 0x65c00, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_3,
> },
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> index def7c161d787d9cecd219b4db0482158d3e5bc12..cc4413432cfdc636e38a56011d39f18d7e94c23a 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> @@ -202,55 +202,47 @@ static const struct dpu_pingpong_cfg sm8550_pp[] = {
> {
> .name = "pingpong_0", .id = PINGPONG_0,
> .base = 0x69000, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_0,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> }, {
> .name = "pingpong_1", .id = PINGPONG_1,
> .base = 0x6a000, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_0,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> }, {
> .name = "pingpong_2", .id = PINGPONG_2,
> .base = 0x6b000, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_1,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
> }, {
> .name = "pingpong_3", .id = PINGPONG_3,
> .base = 0x6c000, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_1,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
> }, {
> .name = "pingpong_4", .id = PINGPONG_4,
> .base = 0x6d000, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_2,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
> }, {
> .name = "pingpong_5", .id = PINGPONG_5,
> .base = 0x6e000, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_2,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
> }, {
> .name = "pingpong_cwb_0", .id = PINGPONG_CWB_0,
> .base = 0x66000, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_3,
> }, {
> .name = "pingpong_cwb_1", .id = PINGPONG_CWB_1,
> .base = 0x66400, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_3,
> },
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
> index 979a674517d8b270309a4ce92534face0f2ba855..32f88533154584dc98a515b1ddef27ab2005fecd 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
> @@ -202,55 +202,47 @@ static const struct dpu_pingpong_cfg sar2130p_pp[] = {
> {
> .name = "pingpong_0", .id = PINGPONG_0,
> .base = 0x69000, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_0,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> }, {
> .name = "pingpong_1", .id = PINGPONG_1,
> .base = 0x6a000, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_0,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> }, {
> .name = "pingpong_2", .id = PINGPONG_2,
> .base = 0x6b000, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_1,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
> }, {
> .name = "pingpong_3", .id = PINGPONG_3,
> .base = 0x6c000, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_1,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
> }, {
> .name = "pingpong_4", .id = PINGPONG_4,
> .base = 0x6d000, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_2,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
> }, {
> .name = "pingpong_5", .id = PINGPONG_5,
> .base = 0x6e000, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_2,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
> }, {
> .name = "pingpong_cwb_0", .id = PINGPONG_CWB_0,
> .base = 0x66000, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_3,
> }, {
> .name = "pingpong_cwb_1", .id = PINGPONG_CWB_1,
> .base = 0x66400, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_3,
> },
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
> index ffee0740ddb5c13dbbd2ca0d70855cba27f73ca6..e053324d76a2e5020e6a7477ddadc9f7d94fe57e 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
> @@ -202,55 +202,47 @@ static const struct dpu_pingpong_cfg x1e80100_pp[] = {
> {
> .name = "pingpong_0", .id = PINGPONG_0,
> .base = 0x69000, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_0,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
> }, {
> .name = "pingpong_1", .id = PINGPONG_1,
> .base = 0x6a000, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_0,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
> }, {
> .name = "pingpong_2", .id = PINGPONG_2,
> .base = 0x6b000, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_1,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
> }, {
> .name = "pingpong_3", .id = PINGPONG_3,
> .base = 0x6c000, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_1,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
> }, {
> .name = "pingpong_4", .id = PINGPONG_4,
> .base = 0x6d000, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_2,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
> }, {
> .name = "pingpong_5", .id = PINGPONG_5,
> .base = 0x6e000, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_2,
> .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
> }, {
> .name = "pingpong_cwb_0", .id = PINGPONG_CWB_0,
> .base = 0x66000, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_3,
> }, {
> .name = "pingpong_cwb_1", .id = PINGPONG_CWB_1,
> .base = 0x66400, .len = 0,
> - .features = BIT(DPU_PINGPONG_DITHER),
> .sblk = &sc7280_pp_sblk,
> .merge_3d = MERGE_3D_3,
> },
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index 75b679cd2bd27dd25971489a2d3a6f516b248235..4777a4a852da0d65e20cebc31fd05647e0b4c4b2 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -95,12 +95,6 @@
> #define MIXER_QCM2290_MASK \
> (BIT(DPU_DIM_LAYER) | BIT(DPU_MIXER_COMBINED_ALPHA))
>
> -#define PINGPONG_SDM845_MASK \
> - (BIT(DPU_PINGPONG_DITHER))
> -
> -#define PINGPONG_SM8150_MASK \
> - (BIT(DPU_PINGPONG_DITHER))
> -
> #define WB_SDM845_MASK (BIT(DPU_WB_LINE_MODE) | \
> BIT(DPU_WB_UBWC) | \
> BIT(DPU_WB_YUV_CONFIG) | \
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index ac63f753b43615f7c34d2da51fce919fd77142bf..d48c26a7cb6b69961cebc19576e3f7fc3b8dd2c5 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -117,13 +117,11 @@ enum {
> * PINGPONG sub-blocks
> * @DPU_PINGPONG_SPLIT PP block supports split fifo
> * @DPU_PINGPONG_SLAVE PP block is a suitable slave for split fifo
> - * @DPU_PINGPONG_DITHER Dither blocks
> * @DPU_PINGPONG_MAX
> */
> enum {
> DPU_PINGPONG_SPLIT = 0x1,
> DPU_PINGPONG_SLAVE,
> - DPU_PINGPONG_DITHER,
> DPU_PINGPONG_MAX
> };
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
> index 49e03ecee9e8b567a3f809b977deb83731006ac0..138071be56496da9fdcaff902f68ebb09a212e2e 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
> @@ -325,7 +325,7 @@ struct dpu_hw_pingpong *dpu_hw_pingpong_init(struct drm_device *dev,
> c->ops.disable_dsc = dpu_hw_pp_dsc_disable;
> }
>
> - if (test_bit(DPU_PINGPONG_DITHER, &cfg->features))
> + if (mdss_rev->core_major_ver >= 3)
> c->ops.setup_dither = dpu_hw_pp_setup_dither;
>
> return c;
>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH v4 18/30] drm/msm/dpu: get rid of DPU_MDP_VSYNC_SEL
2025-05-19 16:04 [PATCH v4 00/30] drm/msm/dpu: rework HW block feature handling Dmitry Baryshkov
` (16 preceding siblings ...)
2025-05-19 16:04 ` [PATCH v4 17/30] drm/msm/dpu: get rid of DPU_PINGPONG_DITHER Dmitry Baryshkov
@ 2025-05-19 16:04 ` Dmitry Baryshkov
2025-05-20 7:54 ` neil.armstrong
2025-05-19 16:04 ` [PATCH v4 19/30] drm/msm/dpu: get rid of DPU_MDP_PERIPH_0_REMOVED Dmitry Baryshkov
` (11 subsequent siblings)
29 siblings, 1 reply; 64+ messages in thread
From: Dmitry Baryshkov @ 2025-05-19 16:04 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Sean Paul, Marijn Suijten, David Airlie,
Simona Vetter, Vinod Koul, Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel,
Dmitry Baryshkov
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Continue migration to the MDSS-revision based checks and replace
DPU_MDP_VSYNC_SEL feature bit with the core_major_ver < 5 check.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 3 ---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 2 +-
10 files changed, 2 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h
index c0b4db94777c42efd941fdd52993b854ab54c694..29e0eba91930f96fb94c97c33b4490771c3a7c17 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h
@@ -19,7 +19,6 @@ static const struct dpu_mdp_cfg msm8937_mdp[] = {
{
.name = "top_0",
.base = 0x0, .len = 0x454,
- .features = BIT(DPU_MDP_VSYNC_SEL),
.clk_ctrls = {
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
[DPU_CLK_CTRL_RGB0] = { .reg_off = 0x2ac, .bit_off = 4 },
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h
index d3e4c48be306a04b457cc002910eb018a3f13154..cb1ee4b63f9fe8f0b069ad4a75b121d40e988d2b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h
@@ -19,7 +19,6 @@ static const struct dpu_mdp_cfg msm8917_mdp[] = {
{
.name = "top_0",
.base = 0x0, .len = 0x454,
- .features = BIT(DPU_MDP_VSYNC_SEL),
.clk_ctrls = {
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
[DPU_CLK_CTRL_RGB0] = { .reg_off = 0x2ac, .bit_off = 4 },
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h
index c488b88332d0e69cfb23bcf4e41a2e4f4be6844d..b44d02b48418f7bca50b04119540122fb861b971 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h
@@ -19,7 +19,6 @@ static const struct dpu_mdp_cfg msm8953_mdp[] = {
{
.name = "top_0",
.base = 0x0, .len = 0x454,
- .features = BIT(DPU_MDP_VSYNC_SEL),
.clk_ctrls = {
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
[DPU_CLK_CTRL_RGB0] = { .reg_off = 0x2ac, .bit_off = 4 },
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
index 0e8e71775f2c1c38af018353c85ffeb6ccddb42f..8af63db315b45a5a44836303c8ce92eeccc5b1f8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
@@ -22,7 +22,6 @@ static const struct dpu_mdp_cfg msm8996_mdp[] = {
{
.name = "top_0",
.base = 0x0, .len = 0x454,
- .features = BIT(DPU_MDP_VSYNC_SEL),
.clk_ctrls = {
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
index f2ec30837f9ccbff1041f0465d0123382a00355a..f91220496082bd101099c1817c41699215980d53 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
@@ -23,7 +23,6 @@ static const struct dpu_caps msm8998_dpu_caps = {
static const struct dpu_mdp_cfg msm8998_mdp = {
.name = "top_0",
.base = 0x0, .len = 0x458,
- .features = BIT(DPU_MDP_VSYNC_SEL),
.clk_ctrls = {
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h
index 26f39acd82e07c71cbeaaa72c14d9b7e14d2dcc3..8f9a097147c02b538e720dd52f77e705f7ff1ca2 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h
@@ -22,7 +22,6 @@ static const struct dpu_caps sdm660_dpu_caps = {
static const struct dpu_mdp_cfg sdm660_mdp = {
.name = "top_0",
.base = 0x0, .len = 0x458,
- .features = BIT(DPU_MDP_VSYNC_SEL),
.clk_ctrls = {
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h
index 657f733c9ffff73f9eb5051ba55ed2e4e7bb496d..0ad18bd273ff8c080f001f0bee654393cf0c24cd 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h
@@ -22,7 +22,6 @@ static const struct dpu_caps sdm630_dpu_caps = {
static const struct dpu_mdp_cfg sdm630_mdp = {
.name = "top_0",
.base = 0x0, .len = 0x458,
- .features = BIT(DPU_MDP_VSYNC_SEL),
.clk_ctrls = {
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
index 15da5ded19267711e6df8605d576539475fe634c..3e66feb3e18dcc1d9ed5403a42989d97f84a8edc 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
@@ -23,7 +23,7 @@ static const struct dpu_caps sdm845_dpu_caps = {
static const struct dpu_mdp_cfg sdm845_mdp = {
.name = "top_0",
.base = 0x0, .len = 0x45c,
- .features = BIT(DPU_MDP_AUDIO_SELECT) | BIT(DPU_MDP_VSYNC_SEL),
+ .features = BIT(DPU_MDP_AUDIO_SELECT),
.clk_ctrls = {
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index d48c26a7cb6b69961cebc19576e3f7fc3b8dd2c5..92dfbb5e7f916bf32afeffdb6b843f1da3f3fd44 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -34,8 +34,6 @@
* @DPU_MDP_10BIT_SUPPORT, Chipset supports 10 bit pixel formats
* @DPU_MDP_PERIPH_0_REMOVED Indicates that access to periph top0 block results
* in a failure
- * @DPU_MDP_VSYNC_SEL Enables vsync source selection via MDP_VSYNC_SEL register
- * (moved into INTF block since DPU 5.0.0)
* @DPU_MDP_MAX Maximum value
*/
@@ -44,7 +42,6 @@ enum {
DPU_MDP_10BIT_SUPPORT,
DPU_MDP_AUDIO_SELECT,
DPU_MDP_PERIPH_0_REMOVED,
- DPU_MDP_VSYNC_SEL,
DPU_MDP_MAX
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
index 562a3f4c5238a3ad6c8c1fa4d285b9165ada3cfd..cebe7ce7b258fc178a687770906f7c4c20aa0d4c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
@@ -270,7 +270,7 @@ static void _setup_mdp_ops(struct dpu_hw_mdp_ops *ops,
ops->setup_clk_force_ctrl = dpu_hw_setup_clk_force_ctrl;
ops->get_danger_status = dpu_hw_get_danger_status;
- if (cap & BIT(DPU_MDP_VSYNC_SEL))
+ if (mdss_rev->core_major_ver < 5)
ops->setup_vsync_source = dpu_hw_setup_vsync_sel;
else if (!(cap & BIT(DPU_MDP_PERIPH_0_REMOVED)))
ops->setup_vsync_source = dpu_hw_setup_wd_timer;
--
2.39.5
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH v4 18/30] drm/msm/dpu: get rid of DPU_MDP_VSYNC_SEL
2025-05-19 16:04 ` [PATCH v4 18/30] drm/msm/dpu: get rid of DPU_MDP_VSYNC_SEL Dmitry Baryshkov
@ 2025-05-20 7:54 ` neil.armstrong
0 siblings, 0 replies; 64+ messages in thread
From: neil.armstrong @ 2025-05-20 7:54 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Abhinav Kumar, Sean Paul,
Marijn Suijten, David Airlie, Simona Vetter, Vinod Koul,
Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel,
Dmitry Baryshkov
On 19/05/2025 18:04, Dmitry Baryshkov wrote:
> From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>
> Continue migration to the MDSS-revision based checks and replace
> DPU_MDP_VSYNC_SEL feature bit with the core_major_ver < 5 check.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h | 1 -
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h | 1 -
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h | 1 -
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h | 1 -
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 1 -
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h | 1 -
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h | 1 -
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 3 ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 2 +-
> 10 files changed, 2 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h
> index c0b4db94777c42efd941fdd52993b854ab54c694..29e0eba91930f96fb94c97c33b4490771c3a7c17 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h
> @@ -19,7 +19,6 @@ static const struct dpu_mdp_cfg msm8937_mdp[] = {
> {
> .name = "top_0",
> .base = 0x0, .len = 0x454,
> - .features = BIT(DPU_MDP_VSYNC_SEL),
> .clk_ctrls = {
> [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
> [DPU_CLK_CTRL_RGB0] = { .reg_off = 0x2ac, .bit_off = 4 },
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h
> index d3e4c48be306a04b457cc002910eb018a3f13154..cb1ee4b63f9fe8f0b069ad4a75b121d40e988d2b 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h
> @@ -19,7 +19,6 @@ static const struct dpu_mdp_cfg msm8917_mdp[] = {
> {
> .name = "top_0",
> .base = 0x0, .len = 0x454,
> - .features = BIT(DPU_MDP_VSYNC_SEL),
> .clk_ctrls = {
> [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
> [DPU_CLK_CTRL_RGB0] = { .reg_off = 0x2ac, .bit_off = 4 },
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h
> index c488b88332d0e69cfb23bcf4e41a2e4f4be6844d..b44d02b48418f7bca50b04119540122fb861b971 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h
> @@ -19,7 +19,6 @@ static const struct dpu_mdp_cfg msm8953_mdp[] = {
> {
> .name = "top_0",
> .base = 0x0, .len = 0x454,
> - .features = BIT(DPU_MDP_VSYNC_SEL),
> .clk_ctrls = {
> [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
> [DPU_CLK_CTRL_RGB0] = { .reg_off = 0x2ac, .bit_off = 4 },
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
> index 0e8e71775f2c1c38af018353c85ffeb6ccddb42f..8af63db315b45a5a44836303c8ce92eeccc5b1f8 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
> @@ -22,7 +22,6 @@ static const struct dpu_mdp_cfg msm8996_mdp[] = {
> {
> .name = "top_0",
> .base = 0x0, .len = 0x454,
> - .features = BIT(DPU_MDP_VSYNC_SEL),
> .clk_ctrls = {
> [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
> [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> index f2ec30837f9ccbff1041f0465d0123382a00355a..f91220496082bd101099c1817c41699215980d53 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> @@ -23,7 +23,6 @@ static const struct dpu_caps msm8998_dpu_caps = {
> static const struct dpu_mdp_cfg msm8998_mdp = {
> .name = "top_0",
> .base = 0x0, .len = 0x458,
> - .features = BIT(DPU_MDP_VSYNC_SEL),
> .clk_ctrls = {
> [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
> [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h
> index 26f39acd82e07c71cbeaaa72c14d9b7e14d2dcc3..8f9a097147c02b538e720dd52f77e705f7ff1ca2 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h
> @@ -22,7 +22,6 @@ static const struct dpu_caps sdm660_dpu_caps = {
> static const struct dpu_mdp_cfg sdm660_mdp = {
> .name = "top_0",
> .base = 0x0, .len = 0x458,
> - .features = BIT(DPU_MDP_VSYNC_SEL),
> .clk_ctrls = {
> [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
> [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h
> index 657f733c9ffff73f9eb5051ba55ed2e4e7bb496d..0ad18bd273ff8c080f001f0bee654393cf0c24cd 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h
> @@ -22,7 +22,6 @@ static const struct dpu_caps sdm630_dpu_caps = {
> static const struct dpu_mdp_cfg sdm630_mdp = {
> .name = "top_0",
> .base = 0x0, .len = 0x458,
> - .features = BIT(DPU_MDP_VSYNC_SEL),
> .clk_ctrls = {
> [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
> [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> index 15da5ded19267711e6df8605d576539475fe634c..3e66feb3e18dcc1d9ed5403a42989d97f84a8edc 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> @@ -23,7 +23,7 @@ static const struct dpu_caps sdm845_dpu_caps = {
> static const struct dpu_mdp_cfg sdm845_mdp = {
> .name = "top_0",
> .base = 0x0, .len = 0x45c,
> - .features = BIT(DPU_MDP_AUDIO_SELECT) | BIT(DPU_MDP_VSYNC_SEL),
> + .features = BIT(DPU_MDP_AUDIO_SELECT),
> .clk_ctrls = {
> [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
> [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index d48c26a7cb6b69961cebc19576e3f7fc3b8dd2c5..92dfbb5e7f916bf32afeffdb6b843f1da3f3fd44 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -34,8 +34,6 @@
> * @DPU_MDP_10BIT_SUPPORT, Chipset supports 10 bit pixel formats
> * @DPU_MDP_PERIPH_0_REMOVED Indicates that access to periph top0 block results
> * in a failure
> - * @DPU_MDP_VSYNC_SEL Enables vsync source selection via MDP_VSYNC_SEL register
> - * (moved into INTF block since DPU 5.0.0)
> * @DPU_MDP_MAX Maximum value
>
> */
> @@ -44,7 +42,6 @@ enum {
> DPU_MDP_10BIT_SUPPORT,
> DPU_MDP_AUDIO_SELECT,
> DPU_MDP_PERIPH_0_REMOVED,
> - DPU_MDP_VSYNC_SEL,
> DPU_MDP_MAX
> };
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
> index 562a3f4c5238a3ad6c8c1fa4d285b9165ada3cfd..cebe7ce7b258fc178a687770906f7c4c20aa0d4c 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
> @@ -270,7 +270,7 @@ static void _setup_mdp_ops(struct dpu_hw_mdp_ops *ops,
> ops->setup_clk_force_ctrl = dpu_hw_setup_clk_force_ctrl;
> ops->get_danger_status = dpu_hw_get_danger_status;
>
> - if (cap & BIT(DPU_MDP_VSYNC_SEL))
> + if (mdss_rev->core_major_ver < 5)
> ops->setup_vsync_source = dpu_hw_setup_vsync_sel;
> else if (!(cap & BIT(DPU_MDP_PERIPH_0_REMOVED)))
> ops->setup_vsync_source = dpu_hw_setup_wd_timer;
>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH v4 19/30] drm/msm/dpu: get rid of DPU_MDP_PERIPH_0_REMOVED
2025-05-19 16:04 [PATCH v4 00/30] drm/msm/dpu: rework HW block feature handling Dmitry Baryshkov
` (17 preceding siblings ...)
2025-05-19 16:04 ` [PATCH v4 18/30] drm/msm/dpu: get rid of DPU_MDP_VSYNC_SEL Dmitry Baryshkov
@ 2025-05-19 16:04 ` Dmitry Baryshkov
2025-05-20 7:54 ` neil.armstrong
2025-05-19 16:04 ` [PATCH v4 20/30] drm/msm/dpu: get rid of DPU_MDP_AUDIO_SELECT Dmitry Baryshkov
` (10 subsequent siblings)
29 siblings, 1 reply; 64+ messages in thread
From: Dmitry Baryshkov @ 2025-05-19 16:04 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Sean Paul, Marijn Suijten, David Airlie,
Simona Vetter, Vinod Koul, Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel,
Dmitry Baryshkov
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Continue migration to the MDSS-revision based checks and replace
DPU_MDP_PERIPH_0_REMOVED feature bit with the core_major_ver >= 8 check.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 3 ---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +-
10 files changed, 2 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
index 37c88b393c12d8a04395b6e5dffb67211d2db9cd..ae66c338250664f9306a7d431cfa18ca07a916a5 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
@@ -21,7 +21,6 @@ static const struct dpu_caps sm8650_dpu_caps = {
static const struct dpu_mdp_cfg sm8650_mdp = {
.name = "top_0",
.base = 0, .len = 0x494,
- .features = BIT(DPU_MDP_PERIPH_0_REMOVED),
.clk_ctrls = {
[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
},
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
index 785ca2b2e60f073b0a2db0c0c4ed3b2722de033c..85778071bc1347008dbe4522aeb9ca4fd21aa097 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
@@ -21,7 +21,6 @@ static const struct dpu_caps sc8280xp_dpu_caps = {
static const struct dpu_mdp_cfg sc8280xp_mdp = {
.name = "top_0",
.base = 0x0, .len = 0x494,
- .features = BIT(DPU_MDP_PERIPH_0_REMOVED),
.clk_ctrls = {
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
index 1401a84e0da5754fd2a3661d1421bb9b998271ca..f9676f804f9132296467bc751e11036696afa942 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
@@ -21,7 +21,6 @@ static const struct dpu_caps sm8450_dpu_caps = {
static const struct dpu_mdp_cfg sm8450_mdp = {
.name = "top_0",
.base = 0x0, .len = 0x494,
- .features = BIT(DPU_MDP_PERIPH_0_REMOVED),
.clk_ctrls = {
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
index fbbdce36f0ad99d0b1d32d90627ff5b7f3fc2fc9..7462cfc4cf8de4a10326c83d3341dbee76e437e8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
@@ -20,7 +20,6 @@ static const struct dpu_caps sa8775p_dpu_caps = {
static const struct dpu_mdp_cfg sa8775p_mdp = {
.name = "top_0",
.base = 0x0, .len = 0x494,
- .features = BIT(DPU_MDP_PERIPH_0_REMOVED),
.clk_ctrls = {
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
index cc4413432cfdc636e38a56011d39f18d7e94c23a..695ae7581a88b36fa1f28aa3cd0c9166090e940c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
@@ -21,7 +21,6 @@ static const struct dpu_caps sm8550_dpu_caps = {
static const struct dpu_mdp_cfg sm8550_mdp = {
.name = "top_0",
.base = 0, .len = 0x494,
- .features = BIT(DPU_MDP_PERIPH_0_REMOVED),
.clk_ctrls = {
[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
},
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
index 32f88533154584dc98a515b1ddef27ab2005fecd..9a25113df5aec527baa514aaa61f2b47c2443d27 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
@@ -21,7 +21,6 @@ static const struct dpu_caps sar2130p_dpu_caps = {
static const struct dpu_mdp_cfg sar2130p_mdp = {
.name = "top_0",
.base = 0, .len = 0x494,
- .features = BIT(DPU_MDP_PERIPH_0_REMOVED),
.clk_ctrls = {
[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
},
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
index e053324d76a2e5020e6a7477ddadc9f7d94fe57e..54815c613f087454aa7b4befc84462265d8dfc23 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
@@ -20,7 +20,6 @@ static const struct dpu_caps x1e80100_dpu_caps = {
static const struct dpu_mdp_cfg x1e80100_mdp = {
.name = "top_0",
.base = 0, .len = 0x494,
- .features = BIT(DPU_MDP_PERIPH_0_REMOVED),
.clk_ctrls = {
[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
},
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 92dfbb5e7f916bf32afeffdb6b843f1da3f3fd44..d3a7f46488a21e81a24a9af5071a9a7f5f48cdac 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -32,8 +32,6 @@
* MDP TOP BLOCK features
* @DPU_MDP_PANIC_PER_PIPE Panic configuration needs to be done per pipe
* @DPU_MDP_10BIT_SUPPORT, Chipset supports 10 bit pixel formats
- * @DPU_MDP_PERIPH_0_REMOVED Indicates that access to periph top0 block results
- * in a failure
* @DPU_MDP_MAX Maximum value
*/
@@ -41,7 +39,6 @@ enum {
DPU_MDP_PANIC_PER_PIPE = 0x1,
DPU_MDP_10BIT_SUPPORT,
DPU_MDP_AUDIO_SELECT,
- DPU_MDP_PERIPH_0_REMOVED,
DPU_MDP_MAX
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
index cebe7ce7b258fc178a687770906f7c4c20aa0d4c..c49a67da86b0d46d12c32466981be7f00519974c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
@@ -272,7 +272,7 @@ static void _setup_mdp_ops(struct dpu_hw_mdp_ops *ops,
if (mdss_rev->core_major_ver < 5)
ops->setup_vsync_source = dpu_hw_setup_vsync_sel;
- else if (!(cap & BIT(DPU_MDP_PERIPH_0_REMOVED)))
+ else if (mdss_rev->core_major_ver < 8)
ops->setup_vsync_source = dpu_hw_setup_wd_timer;
ops->get_safe_status = dpu_hw_get_safe_status;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 1fd82b6747e9058ce11dc2620729921492d5ebdd..80ffd46cbfe69fc90afcdc1a144fc5de7bb6af42 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1022,7 +1022,7 @@ static void dpu_kms_mdp_snapshot(struct msm_disp_state *disp_state, struct msm_k
dpu_kms->mmio + cat->wb[i].base, "%s",
cat->wb[i].name);
- if (cat->mdp[0].features & BIT(DPU_MDP_PERIPH_0_REMOVED)) {
+ if (dpu_kms->catalog->mdss_ver->core_major_ver >= 8) {
msm_disp_snapshot_add_block(disp_state, MDP_PERIPH_TOP0,
dpu_kms->mmio + cat->mdp[0].base, "top");
msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len - MDP_PERIPH_TOP0_END,
--
2.39.5
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH v4 19/30] drm/msm/dpu: get rid of DPU_MDP_PERIPH_0_REMOVED
2025-05-19 16:04 ` [PATCH v4 19/30] drm/msm/dpu: get rid of DPU_MDP_PERIPH_0_REMOVED Dmitry Baryshkov
@ 2025-05-20 7:54 ` neil.armstrong
0 siblings, 0 replies; 64+ messages in thread
From: neil.armstrong @ 2025-05-20 7:54 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Abhinav Kumar, Sean Paul,
Marijn Suijten, David Airlie, Simona Vetter, Vinod Koul,
Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel,
Dmitry Baryshkov
On 19/05/2025 18:04, Dmitry Baryshkov wrote:
> From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>
> Continue migration to the MDSS-revision based checks and replace
> DPU_MDP_PERIPH_0_REMOVED feature bit with the core_major_ver >= 8 check.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 1 -
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 1 -
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 1 -
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 1 -
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 1 -
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h | 1 -
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 1 -
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 3 ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +-
> 10 files changed, 2 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
> index 37c88b393c12d8a04395b6e5dffb67211d2db9cd..ae66c338250664f9306a7d431cfa18ca07a916a5 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
> @@ -21,7 +21,6 @@ static const struct dpu_caps sm8650_dpu_caps = {
> static const struct dpu_mdp_cfg sm8650_mdp = {
> .name = "top_0",
> .base = 0, .len = 0x494,
> - .features = BIT(DPU_MDP_PERIPH_0_REMOVED),
> .clk_ctrls = {
> [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
> },
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> index 785ca2b2e60f073b0a2db0c0c4ed3b2722de033c..85778071bc1347008dbe4522aeb9ca4fd21aa097 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> @@ -21,7 +21,6 @@ static const struct dpu_caps sc8280xp_dpu_caps = {
> static const struct dpu_mdp_cfg sc8280xp_mdp = {
> .name = "top_0",
> .base = 0x0, .len = 0x494,
> - .features = BIT(DPU_MDP_PERIPH_0_REMOVED),
> .clk_ctrls = {
> [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
> [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> index 1401a84e0da5754fd2a3661d1421bb9b998271ca..f9676f804f9132296467bc751e11036696afa942 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> @@ -21,7 +21,6 @@ static const struct dpu_caps sm8450_dpu_caps = {
> static const struct dpu_mdp_cfg sm8450_mdp = {
> .name = "top_0",
> .base = 0x0, .len = 0x494,
> - .features = BIT(DPU_MDP_PERIPH_0_REMOVED),
> .clk_ctrls = {
> [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
> [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
> index fbbdce36f0ad99d0b1d32d90627ff5b7f3fc2fc9..7462cfc4cf8de4a10326c83d3341dbee76e437e8 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
> @@ -20,7 +20,6 @@ static const struct dpu_caps sa8775p_dpu_caps = {
> static const struct dpu_mdp_cfg sa8775p_mdp = {
> .name = "top_0",
> .base = 0x0, .len = 0x494,
> - .features = BIT(DPU_MDP_PERIPH_0_REMOVED),
> .clk_ctrls = {
> [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
> [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> index cc4413432cfdc636e38a56011d39f18d7e94c23a..695ae7581a88b36fa1f28aa3cd0c9166090e940c 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> @@ -21,7 +21,6 @@ static const struct dpu_caps sm8550_dpu_caps = {
> static const struct dpu_mdp_cfg sm8550_mdp = {
> .name = "top_0",
> .base = 0, .len = 0x494,
> - .features = BIT(DPU_MDP_PERIPH_0_REMOVED),
> .clk_ctrls = {
> [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
> },
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
> index 32f88533154584dc98a515b1ddef27ab2005fecd..9a25113df5aec527baa514aaa61f2b47c2443d27 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
> @@ -21,7 +21,6 @@ static const struct dpu_caps sar2130p_dpu_caps = {
> static const struct dpu_mdp_cfg sar2130p_mdp = {
> .name = "top_0",
> .base = 0, .len = 0x494,
> - .features = BIT(DPU_MDP_PERIPH_0_REMOVED),
> .clk_ctrls = {
> [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
> },
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
> index e053324d76a2e5020e6a7477ddadc9f7d94fe57e..54815c613f087454aa7b4befc84462265d8dfc23 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
> @@ -20,7 +20,6 @@ static const struct dpu_caps x1e80100_dpu_caps = {
> static const struct dpu_mdp_cfg x1e80100_mdp = {
> .name = "top_0",
> .base = 0, .len = 0x494,
> - .features = BIT(DPU_MDP_PERIPH_0_REMOVED),
> .clk_ctrls = {
> [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
> },
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index 92dfbb5e7f916bf32afeffdb6b843f1da3f3fd44..d3a7f46488a21e81a24a9af5071a9a7f5f48cdac 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -32,8 +32,6 @@
> * MDP TOP BLOCK features
> * @DPU_MDP_PANIC_PER_PIPE Panic configuration needs to be done per pipe
> * @DPU_MDP_10BIT_SUPPORT, Chipset supports 10 bit pixel formats
> - * @DPU_MDP_PERIPH_0_REMOVED Indicates that access to periph top0 block results
> - * in a failure
> * @DPU_MDP_MAX Maximum value
>
> */
> @@ -41,7 +39,6 @@ enum {
> DPU_MDP_PANIC_PER_PIPE = 0x1,
> DPU_MDP_10BIT_SUPPORT,
> DPU_MDP_AUDIO_SELECT,
> - DPU_MDP_PERIPH_0_REMOVED,
> DPU_MDP_MAX
> };
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
> index cebe7ce7b258fc178a687770906f7c4c20aa0d4c..c49a67da86b0d46d12c32466981be7f00519974c 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
> @@ -272,7 +272,7 @@ static void _setup_mdp_ops(struct dpu_hw_mdp_ops *ops,
>
> if (mdss_rev->core_major_ver < 5)
> ops->setup_vsync_source = dpu_hw_setup_vsync_sel;
> - else if (!(cap & BIT(DPU_MDP_PERIPH_0_REMOVED)))
> + else if (mdss_rev->core_major_ver < 8)
> ops->setup_vsync_source = dpu_hw_setup_wd_timer;
>
> ops->get_safe_status = dpu_hw_get_safe_status;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> index 1fd82b6747e9058ce11dc2620729921492d5ebdd..80ffd46cbfe69fc90afcdc1a144fc5de7bb6af42 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> @@ -1022,7 +1022,7 @@ static void dpu_kms_mdp_snapshot(struct msm_disp_state *disp_state, struct msm_k
> dpu_kms->mmio + cat->wb[i].base, "%s",
> cat->wb[i].name);
>
> - if (cat->mdp[0].features & BIT(DPU_MDP_PERIPH_0_REMOVED)) {
> + if (dpu_kms->catalog->mdss_ver->core_major_ver >= 8) {
> msm_disp_snapshot_add_block(disp_state, MDP_PERIPH_TOP0,
> dpu_kms->mmio + cat->mdp[0].base, "top");
> msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len - MDP_PERIPH_TOP0_END,
>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH v4 20/30] drm/msm/dpu: get rid of DPU_MDP_AUDIO_SELECT
2025-05-19 16:04 [PATCH v4 00/30] drm/msm/dpu: rework HW block feature handling Dmitry Baryshkov
` (18 preceding siblings ...)
2025-05-19 16:04 ` [PATCH v4 19/30] drm/msm/dpu: get rid of DPU_MDP_PERIPH_0_REMOVED Dmitry Baryshkov
@ 2025-05-19 16:04 ` Dmitry Baryshkov
2025-05-20 7:53 ` neil.armstrong
2025-05-19 16:04 ` [PATCH v4 21/30] drm/msm/dpu: get rid of DPU_MIXER_COMBINED_ALPHA Dmitry Baryshkov
` (9 subsequent siblings)
29 siblings, 1 reply; 64+ messages in thread
From: Dmitry Baryshkov @ 2025-05-19 16:04 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Sean Paul, Marijn Suijten, David Airlie,
Simona Vetter, Vinod Koul, Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel,
Dmitry Baryshkov
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Continue migration to the MDSS-revision based checks and replace
DPU_MDP_AUDIO_SELECT feature bit with the core_major_ver == 8 ||
core_major_ver == 5 check.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 3 ++-
7 files changed, 2 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
index 3e66feb3e18dcc1d9ed5403a42989d97f84a8edc..72a7257b4d7ba5bfe89ec76bac19550e023a2b50 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
@@ -23,7 +23,6 @@ static const struct dpu_caps sdm845_dpu_caps = {
static const struct dpu_mdp_cfg sdm845_mdp = {
.name = "top_0",
.base = 0x0, .len = 0x45c,
- .features = BIT(DPU_MDP_AUDIO_SELECT),
.clk_ctrls = {
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h
index 3a60432a758a942eb1541f143018bd466b2bdf20..ce169a610e195cbb6f0fee1362bcaaf05df777cb 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h
@@ -11,7 +11,6 @@
static const struct dpu_mdp_cfg sdm670_mdp = {
.name = "top_0",
.base = 0x0, .len = 0x45c,
- .features = BIT(DPU_MDP_AUDIO_SELECT),
.clk_ctrls = {
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
index e07c2cc4188bb12e2253068ca8666ce9364c69c1..23a3a458dd5c260399a42e5f4d4361b3c4e82c4f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
@@ -23,7 +23,6 @@ static const struct dpu_caps sm8150_dpu_caps = {
static const struct dpu_mdp_cfg sm8150_mdp = {
.name = "top_0",
.base = 0x0, .len = 0x45c,
- .features = BIT(DPU_MDP_AUDIO_SELECT),
.clk_ctrls = {
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
index b350dba28caed77e542d6a41ceac191a93e165a7..75f8f69123a4a6afe8234a9de21ce68b23c11605 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
@@ -23,7 +23,6 @@ static const struct dpu_caps sc8180x_dpu_caps = {
static const struct dpu_mdp_cfg sc8180x_mdp = {
.name = "top_0",
.base = 0x0, .len = 0x45c,
- .features = BIT(DPU_MDP_AUDIO_SELECT),
.clk_ctrls = {
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
index 27c71a8a1f31921e5e1f4b6b15e0efc25fb63537..6b895eca2fac53505f7a1d857d30bb8a5d23d4c8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
@@ -23,7 +23,6 @@ static const struct dpu_caps sm7150_dpu_caps = {
static const struct dpu_mdp_cfg sm7150_mdp = {
.name = "top_0",
.base = 0x0, .len = 0x45c,
- .features = BIT(DPU_MDP_AUDIO_SELECT),
.clk_ctrls = {
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index d3a7f46488a21e81a24a9af5071a9a7f5f48cdac..9ba9e273f81ab1966db1865b4ce28f8c18f750b8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -38,7 +38,6 @@
enum {
DPU_MDP_PANIC_PER_PIPE = 0x1,
DPU_MDP_10BIT_SUPPORT,
- DPU_MDP_AUDIO_SELECT,
DPU_MDP_MAX
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
index c49a67da86b0d46d12c32466981be7f00519974c..5c811f0142d5e2a012d7e9b3a918818f22ec11cf 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
@@ -280,7 +280,8 @@ static void _setup_mdp_ops(struct dpu_hw_mdp_ops *ops,
if (mdss_rev->core_major_ver >= 5)
ops->dp_phy_intf_sel = dpu_hw_dp_phy_intf_sel;
- if (cap & BIT(DPU_MDP_AUDIO_SELECT))
+ if (mdss_rev->core_major_ver == 4 ||
+ mdss_rev->core_major_ver == 5)
ops->intf_audio_select = dpu_hw_intf_audio_select;
}
--
2.39.5
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH v4 20/30] drm/msm/dpu: get rid of DPU_MDP_AUDIO_SELECT
2025-05-19 16:04 ` [PATCH v4 20/30] drm/msm/dpu: get rid of DPU_MDP_AUDIO_SELECT Dmitry Baryshkov
@ 2025-05-20 7:53 ` neil.armstrong
2025-05-20 21:30 ` Dmitry Baryshkov
0 siblings, 1 reply; 64+ messages in thread
From: neil.armstrong @ 2025-05-20 7:53 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Abhinav Kumar, Sean Paul,
Marijn Suijten, David Airlie, Simona Vetter, Vinod Koul,
Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel,
Dmitry Baryshkov
On 19/05/2025 18:04, Dmitry Baryshkov wrote:
> From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>
> Continue migration to the MDSS-revision based checks and replace
> DPU_MDP_AUDIO_SELECT feature bit with the core_major_ver == 8 ||
> core_major_ver == 5 check.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 1 -
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h | 1 -
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 1 -
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 1 -
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h | 1 -
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 -
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 3 ++-
> 7 files changed, 2 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> index 3e66feb3e18dcc1d9ed5403a42989d97f84a8edc..72a7257b4d7ba5bfe89ec76bac19550e023a2b50 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> @@ -23,7 +23,6 @@ static const struct dpu_caps sdm845_dpu_caps = {
> static const struct dpu_mdp_cfg sdm845_mdp = {
> .name = "top_0",
> .base = 0x0, .len = 0x45c,
> - .features = BIT(DPU_MDP_AUDIO_SELECT),
> .clk_ctrls = {
> [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
> [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h
> index 3a60432a758a942eb1541f143018bd466b2bdf20..ce169a610e195cbb6f0fee1362bcaaf05df777cb 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h
> @@ -11,7 +11,6 @@
> static const struct dpu_mdp_cfg sdm670_mdp = {
> .name = "top_0",
> .base = 0x0, .len = 0x45c,
> - .features = BIT(DPU_MDP_AUDIO_SELECT),
> .clk_ctrls = {
> [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
> [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> index e07c2cc4188bb12e2253068ca8666ce9364c69c1..23a3a458dd5c260399a42e5f4d4361b3c4e82c4f 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> @@ -23,7 +23,6 @@ static const struct dpu_caps sm8150_dpu_caps = {
> static const struct dpu_mdp_cfg sm8150_mdp = {
> .name = "top_0",
> .base = 0x0, .len = 0x45c,
> - .features = BIT(DPU_MDP_AUDIO_SELECT),
> .clk_ctrls = {
> [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
> [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> index b350dba28caed77e542d6a41ceac191a93e165a7..75f8f69123a4a6afe8234a9de21ce68b23c11605 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> @@ -23,7 +23,6 @@ static const struct dpu_caps sc8180x_dpu_caps = {
> static const struct dpu_mdp_cfg sc8180x_mdp = {
> .name = "top_0",
> .base = 0x0, .len = 0x45c,
> - .features = BIT(DPU_MDP_AUDIO_SELECT),
> .clk_ctrls = {
> [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
> [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
> index 27c71a8a1f31921e5e1f4b6b15e0efc25fb63537..6b895eca2fac53505f7a1d857d30bb8a5d23d4c8 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
> @@ -23,7 +23,6 @@ static const struct dpu_caps sm7150_dpu_caps = {
> static const struct dpu_mdp_cfg sm7150_mdp = {
> .name = "top_0",
> .base = 0x0, .len = 0x45c,
> - .features = BIT(DPU_MDP_AUDIO_SELECT),
> .clk_ctrls = {
> [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
> [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index d3a7f46488a21e81a24a9af5071a9a7f5f48cdac..9ba9e273f81ab1966db1865b4ce28f8c18f750b8 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -38,7 +38,6 @@
> enum {
> DPU_MDP_PANIC_PER_PIPE = 0x1,
> DPU_MDP_10BIT_SUPPORT,
> - DPU_MDP_AUDIO_SELECT,
> DPU_MDP_MAX
> };
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
> index c49a67da86b0d46d12c32466981be7f00519974c..5c811f0142d5e2a012d7e9b3a918818f22ec11cf 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
> @@ -280,7 +280,8 @@ static void _setup_mdp_ops(struct dpu_hw_mdp_ops *ops,
> if (mdss_rev->core_major_ver >= 5)
> ops->dp_phy_intf_sel = dpu_hw_dp_phy_intf_sel;
>
> - if (cap & BIT(DPU_MDP_AUDIO_SELECT))
> + if (mdss_rev->core_major_ver == 4 ||
> + mdss_rev->core_major_ver == 5)
Commit message says: core_major_ver == 8 || core_major_ver == 5
Which one is right ?
Neil
> ops->intf_audio_select = dpu_hw_intf_audio_select;
> }
>
>
^ permalink raw reply [flat|nested] 64+ messages in thread* Re: [PATCH v4 20/30] drm/msm/dpu: get rid of DPU_MDP_AUDIO_SELECT
2025-05-20 7:53 ` neil.armstrong
@ 2025-05-20 21:30 ` Dmitry Baryshkov
0 siblings, 0 replies; 64+ messages in thread
From: Dmitry Baryshkov @ 2025-05-20 21:30 UTC (permalink / raw)
To: Neil Armstrong
Cc: Rob Clark, Abhinav Kumar, Sean Paul, Marijn Suijten, David Airlie,
Simona Vetter, Vinod Koul, Konrad Dybcio, linux-arm-msm,
dri-devel, freedreno, linux-kernel
On Tue, May 20, 2025 at 09:53:42AM +0200, neil.armstrong@linaro.org wrote:
> On 19/05/2025 18:04, Dmitry Baryshkov wrote:
> > From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> >
> > Continue migration to the MDSS-revision based checks and replace
> > DPU_MDP_AUDIO_SELECT feature bit with the core_major_ver == 8 ||
> > core_major_ver == 5 check.
> >
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> > ---
> > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 1 -
> > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h | 1 -
> > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 1 -
> > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 1 -
> > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h | 1 -
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 -
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 3 ++-
> > 7 files changed, 2 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> > index 3e66feb3e18dcc1d9ed5403a42989d97f84a8edc..72a7257b4d7ba5bfe89ec76bac19550e023a2b50 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> > @@ -23,7 +23,6 @@ static const struct dpu_caps sdm845_dpu_caps = {
> > static const struct dpu_mdp_cfg sdm845_mdp = {
> > .name = "top_0",
> > .base = 0x0, .len = 0x45c,
> > - .features = BIT(DPU_MDP_AUDIO_SELECT),
> > .clk_ctrls = {
> > [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
> > [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h
> > index 3a60432a758a942eb1541f143018bd466b2bdf20..ce169a610e195cbb6f0fee1362bcaaf05df777cb 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h
> > @@ -11,7 +11,6 @@
> > static const struct dpu_mdp_cfg sdm670_mdp = {
> > .name = "top_0",
> > .base = 0x0, .len = 0x45c,
> > - .features = BIT(DPU_MDP_AUDIO_SELECT),
> > .clk_ctrls = {
> > [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
> > [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> > index e07c2cc4188bb12e2253068ca8666ce9364c69c1..23a3a458dd5c260399a42e5f4d4361b3c4e82c4f 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> > @@ -23,7 +23,6 @@ static const struct dpu_caps sm8150_dpu_caps = {
> > static const struct dpu_mdp_cfg sm8150_mdp = {
> > .name = "top_0",
> > .base = 0x0, .len = 0x45c,
> > - .features = BIT(DPU_MDP_AUDIO_SELECT),
> > .clk_ctrls = {
> > [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
> > [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> > index b350dba28caed77e542d6a41ceac191a93e165a7..75f8f69123a4a6afe8234a9de21ce68b23c11605 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> > @@ -23,7 +23,6 @@ static const struct dpu_caps sc8180x_dpu_caps = {
> > static const struct dpu_mdp_cfg sc8180x_mdp = {
> > .name = "top_0",
> > .base = 0x0, .len = 0x45c,
> > - .features = BIT(DPU_MDP_AUDIO_SELECT),
> > .clk_ctrls = {
> > [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
> > [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
> > index 27c71a8a1f31921e5e1f4b6b15e0efc25fb63537..6b895eca2fac53505f7a1d857d30bb8a5d23d4c8 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
> > @@ -23,7 +23,6 @@ static const struct dpu_caps sm7150_dpu_caps = {
> > static const struct dpu_mdp_cfg sm7150_mdp = {
> > .name = "top_0",
> > .base = 0x0, .len = 0x45c,
> > - .features = BIT(DPU_MDP_AUDIO_SELECT),
> > .clk_ctrls = {
> > [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
> > [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> > index d3a7f46488a21e81a24a9af5071a9a7f5f48cdac..9ba9e273f81ab1966db1865b4ce28f8c18f750b8 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> > @@ -38,7 +38,6 @@
> > enum {
> > DPU_MDP_PANIC_PER_PIPE = 0x1,
> > DPU_MDP_10BIT_SUPPORT,
> > - DPU_MDP_AUDIO_SELECT,
> > DPU_MDP_MAX
> > };
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
> > index c49a67da86b0d46d12c32466981be7f00519974c..5c811f0142d5e2a012d7e9b3a918818f22ec11cf 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
> > @@ -280,7 +280,8 @@ static void _setup_mdp_ops(struct dpu_hw_mdp_ops *ops,
> > if (mdss_rev->core_major_ver >= 5)
> > ops->dp_phy_intf_sel = dpu_hw_dp_phy_intf_sel;
> > - if (cap & BIT(DPU_MDP_AUDIO_SELECT))
> > + if (mdss_rev->core_major_ver == 4 ||
> > + mdss_rev->core_major_ver == 5)
>
> Commit message says: core_major_ver == 8 || core_major_ver == 5
>
> Which one is right ?
It should be 4, as in the code, I'll fix it later on.
>
> Neil
>
> > ops->intf_audio_select = dpu_hw_intf_audio_select;
> > }
> >
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH v4 21/30] drm/msm/dpu: get rid of DPU_MIXER_COMBINED_ALPHA
2025-05-19 16:04 [PATCH v4 00/30] drm/msm/dpu: rework HW block feature handling Dmitry Baryshkov
` (19 preceding siblings ...)
2025-05-19 16:04 ` [PATCH v4 20/30] drm/msm/dpu: get rid of DPU_MDP_AUDIO_SELECT Dmitry Baryshkov
@ 2025-05-19 16:04 ` Dmitry Baryshkov
2025-05-20 7:59 ` neil.armstrong
2025-05-19 16:04 ` [PATCH v4 22/30] drm/msm/dpu: get rid of DPU_DIM_LAYER Dmitry Baryshkov
` (8 subsequent siblings)
29 siblings, 1 reply; 64+ messages in thread
From: Dmitry Baryshkov @ 2025-05-19 16:04 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Sean Paul, Marijn Suijten, David Airlie,
Simona Vetter, Vinod Koul, Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel,
Dmitry Baryshkov
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Continue migration to the MDSS-revision based checks and replace
DPU_MIXER_COMBINED_ALPHA feature bit with the core_major_ver >= 4 check.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 4 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 --
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 6 ++++--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h | 3 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 2 +-
5 files changed, 9 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 4777a4a852da0d65e20cebc31fd05647e0b4c4b2..d64ebc729bfb589bf90af89c094181f879d5b1ef 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -90,10 +90,10 @@
(BIT(DPU_MIXER_SOURCESPLIT))
#define MIXER_SDM845_MASK \
- (BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER) | BIT(DPU_MIXER_COMBINED_ALPHA))
+ (BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER))
#define MIXER_QCM2290_MASK \
- (BIT(DPU_DIM_LAYER) | BIT(DPU_MIXER_COMBINED_ALPHA))
+ (BIT(DPU_DIM_LAYER))
#define WB_SDM845_MASK (BIT(DPU_WB_LINE_MODE) | \
BIT(DPU_WB_UBWC) | \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 9ba9e273f81ab1966db1865b4ce28f8c18f750b8..5e4608d10c6d4fee387c9a599a73b15661148430 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -85,7 +85,6 @@ enum {
* @DPU_MIXER_SOURCESPLIT Layer mixer supports source-split configuration
* @DPU_MIXER_GC Gamma correction block
* @DPU_DIM_LAYER Layer mixer supports dim layer
- * @DPU_MIXER_COMBINED_ALPHA Layer mixer has combined alpha register
* @DPU_MIXER_MAX maximum value
*/
enum {
@@ -93,7 +92,6 @@ enum {
DPU_MIXER_SOURCESPLIT,
DPU_MIXER_GC,
DPU_DIM_LAYER,
- DPU_MIXER_COMBINED_ALPHA,
DPU_MIXER_MAX
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
index 4f57cfca89bd3962e7e512952809db0300cb9baf..3bfb61cb83672dca4236bdbbbfb1e442223576d2 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
@@ -150,10 +150,12 @@ static void dpu_hw_lm_setup_color3(struct dpu_hw_mixer *ctx,
* @dev: Corresponding device for devres management
* @cfg: mixer catalog entry for which driver object is required
* @addr: mapped register io address of MDP
+ * @mdss_ver: DPU core's major and minor versions
*/
struct dpu_hw_mixer *dpu_hw_lm_init(struct drm_device *dev,
const struct dpu_lm_cfg *cfg,
- void __iomem *addr)
+ void __iomem *addr,
+ const struct dpu_mdss_version *mdss_ver)
{
struct dpu_hw_mixer *c;
@@ -173,7 +175,7 @@ struct dpu_hw_mixer *dpu_hw_lm_init(struct drm_device *dev,
c->idx = cfg->id;
c->cap = cfg;
c->ops.setup_mixer_out = dpu_hw_lm_setup_out;
- if (test_bit(DPU_MIXER_COMBINED_ALPHA, &c->cap->features))
+ if (mdss_ver->core_major_ver >= 4)
c->ops.setup_blend_config = dpu_hw_lm_setup_blend_config_combined_alpha;
else
c->ops.setup_blend_config = dpu_hw_lm_setup_blend_config;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h
index 6f60fa9b3cd78160699a97dc7a86a5ec0b599281..fff1156add683fec8ce6785e7fe1d769d0de3fe0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h
@@ -95,6 +95,7 @@ static inline struct dpu_hw_mixer *to_dpu_hw_mixer(struct dpu_hw_blk *hw)
struct dpu_hw_mixer *dpu_hw_lm_init(struct drm_device *dev,
const struct dpu_lm_cfg *cfg,
- void __iomem *addr);
+ void __iomem *addr,
+ const struct dpu_mdss_version *mdss_ver);
#endif /*_DPU_HW_LM_H */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index d728e275ac427f7849dad4f4a055c56840ca2d23..7bcb1e057b143a5512aafbd640199c8f3b436527 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -60,7 +60,7 @@ int dpu_rm_init(struct drm_device *dev,
struct dpu_hw_mixer *hw;
const struct dpu_lm_cfg *lm = &cat->mixer[i];
- hw = dpu_hw_lm_init(dev, lm, mmio);
+ hw = dpu_hw_lm_init(dev, lm, mmio, cat->mdss_ver);
if (IS_ERR(hw)) {
rc = PTR_ERR(hw);
DPU_ERROR("failed lm object creation: err %d\n", rc);
--
2.39.5
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH v4 21/30] drm/msm/dpu: get rid of DPU_MIXER_COMBINED_ALPHA
2025-05-19 16:04 ` [PATCH v4 21/30] drm/msm/dpu: get rid of DPU_MIXER_COMBINED_ALPHA Dmitry Baryshkov
@ 2025-05-20 7:59 ` neil.armstrong
0 siblings, 0 replies; 64+ messages in thread
From: neil.armstrong @ 2025-05-20 7:59 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Abhinav Kumar, Sean Paul,
Marijn Suijten, David Airlie, Simona Vetter, Vinod Koul,
Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel,
Dmitry Baryshkov
On 19/05/2025 18:04, Dmitry Baryshkov wrote:
> From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>
> Continue migration to the MDSS-revision based checks and replace
> DPU_MIXER_COMBINED_ALPHA feature bit with the core_major_ver >= 4 check.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 4 ++--
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 --
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 6 ++++--
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h | 3 ++-
> drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 2 +-
> 5 files changed, 9 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index 4777a4a852da0d65e20cebc31fd05647e0b4c4b2..d64ebc729bfb589bf90af89c094181f879d5b1ef 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -90,10 +90,10 @@
> (BIT(DPU_MIXER_SOURCESPLIT))
>
> #define MIXER_SDM845_MASK \
> - (BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER) | BIT(DPU_MIXER_COMBINED_ALPHA))
> + (BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER))
>
> #define MIXER_QCM2290_MASK \
> - (BIT(DPU_DIM_LAYER) | BIT(DPU_MIXER_COMBINED_ALPHA))
> + (BIT(DPU_DIM_LAYER))
>
> #define WB_SDM845_MASK (BIT(DPU_WB_LINE_MODE) | \
> BIT(DPU_WB_UBWC) | \
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index 9ba9e273f81ab1966db1865b4ce28f8c18f750b8..5e4608d10c6d4fee387c9a599a73b15661148430 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -85,7 +85,6 @@ enum {
> * @DPU_MIXER_SOURCESPLIT Layer mixer supports source-split configuration
> * @DPU_MIXER_GC Gamma correction block
> * @DPU_DIM_LAYER Layer mixer supports dim layer
> - * @DPU_MIXER_COMBINED_ALPHA Layer mixer has combined alpha register
> * @DPU_MIXER_MAX maximum value
> */
> enum {
> @@ -93,7 +92,6 @@ enum {
> DPU_MIXER_SOURCESPLIT,
> DPU_MIXER_GC,
> DPU_DIM_LAYER,
> - DPU_MIXER_COMBINED_ALPHA,
> DPU_MIXER_MAX
> };
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
> index 4f57cfca89bd3962e7e512952809db0300cb9baf..3bfb61cb83672dca4236bdbbbfb1e442223576d2 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
> @@ -150,10 +150,12 @@ static void dpu_hw_lm_setup_color3(struct dpu_hw_mixer *ctx,
> * @dev: Corresponding device for devres management
> * @cfg: mixer catalog entry for which driver object is required
> * @addr: mapped register io address of MDP
> + * @mdss_ver: DPU core's major and minor versions
> */
> struct dpu_hw_mixer *dpu_hw_lm_init(struct drm_device *dev,
> const struct dpu_lm_cfg *cfg,
> - void __iomem *addr)
> + void __iomem *addr,
> + const struct dpu_mdss_version *mdss_ver)
> {
> struct dpu_hw_mixer *c;
>
> @@ -173,7 +175,7 @@ struct dpu_hw_mixer *dpu_hw_lm_init(struct drm_device *dev,
> c->idx = cfg->id;
> c->cap = cfg;
> c->ops.setup_mixer_out = dpu_hw_lm_setup_out;
> - if (test_bit(DPU_MIXER_COMBINED_ALPHA, &c->cap->features))
> + if (mdss_ver->core_major_ver >= 4)
> c->ops.setup_blend_config = dpu_hw_lm_setup_blend_config_combined_alpha;
> else
> c->ops.setup_blend_config = dpu_hw_lm_setup_blend_config;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h
> index 6f60fa9b3cd78160699a97dc7a86a5ec0b599281..fff1156add683fec8ce6785e7fe1d769d0de3fe0 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h
> @@ -95,6 +95,7 @@ static inline struct dpu_hw_mixer *to_dpu_hw_mixer(struct dpu_hw_blk *hw)
>
> struct dpu_hw_mixer *dpu_hw_lm_init(struct drm_device *dev,
> const struct dpu_lm_cfg *cfg,
> - void __iomem *addr);
> + void __iomem *addr,
> + const struct dpu_mdss_version *mdss_ver);
>
> #endif /*_DPU_HW_LM_H */
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> index d728e275ac427f7849dad4f4a055c56840ca2d23..7bcb1e057b143a5512aafbd640199c8f3b436527 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> @@ -60,7 +60,7 @@ int dpu_rm_init(struct drm_device *dev,
> struct dpu_hw_mixer *hw;
> const struct dpu_lm_cfg *lm = &cat->mixer[i];
>
> - hw = dpu_hw_lm_init(dev, lm, mmio);
> + hw = dpu_hw_lm_init(dev, lm, mmio, cat->mdss_ver);
> if (IS_ERR(hw)) {
> rc = PTR_ERR(hw);
> DPU_ERROR("failed lm object creation: err %d\n", rc);
>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH v4 22/30] drm/msm/dpu: get rid of DPU_DIM_LAYER
2025-05-19 16:04 [PATCH v4 00/30] drm/msm/dpu: rework HW block feature handling Dmitry Baryshkov
` (20 preceding siblings ...)
2025-05-19 16:04 ` [PATCH v4 21/30] drm/msm/dpu: get rid of DPU_MIXER_COMBINED_ALPHA Dmitry Baryshkov
@ 2025-05-19 16:04 ` Dmitry Baryshkov
2025-05-20 8:03 ` neil.armstrong
2025-05-19 16:04 ` [PATCH v4 23/30] drm/msm/dpu: get rid of DPU_DSC_HW_REV_1_2 Dmitry Baryshkov
` (7 subsequent siblings)
29 siblings, 1 reply; 64+ messages in thread
From: Dmitry Baryshkov @ 2025-05-19 16:04 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Sean Paul, Marijn Suijten, David Airlie,
Simona Vetter, Vinod Koul, Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel,
Dmitry Baryshkov
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Continue migration to the MDSS-revision based checks and drop the
DPU_DIM_LAYER feature bit. It is currently unused, but can be replaed
with the core_major_ver >= 4 check.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 12 ++++++------
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 8 ++++----
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h | 8 ++++----
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 12 ++++++------
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 12 ++++++------
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h | 8 ++++----
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h | 3 ---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 2 --
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 12 ++++++------
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 4 ++--
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 4 ++--
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 12 ++++++------
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 6 +++---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 12 ++++++------
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 12 ++++++------
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 12 ++++++------
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 12 ++++++------
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h | 12 ++++++------
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 12 ++++++------
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 6 ------
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 --
24 files changed, 85 insertions(+), 101 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
index ae66c338250664f9306a7d431cfa18ca07a916a5..9a8f6043370997cb12414c4132eb68cc73f7030a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
@@ -132,7 +132,7 @@ static const struct dpu_lm_cfg sm8650_lm[] = {
{
.name = "lm_0", .id = LM_0,
.base = 0x44000, .len = 0x400,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_1,
.pingpong = PINGPONG_0,
@@ -140,7 +140,7 @@ static const struct dpu_lm_cfg sm8650_lm[] = {
}, {
.name = "lm_1", .id = LM_1,
.base = 0x45000, .len = 0x400,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_0,
.pingpong = PINGPONG_1,
@@ -148,7 +148,7 @@ static const struct dpu_lm_cfg sm8650_lm[] = {
}, {
.name = "lm_2", .id = LM_2,
.base = 0x46000, .len = 0x400,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_3,
.pingpong = PINGPONG_2,
@@ -156,7 +156,7 @@ static const struct dpu_lm_cfg sm8650_lm[] = {
}, {
.name = "lm_3", .id = LM_3,
.base = 0x47000, .len = 0x400,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_2,
.pingpong = PINGPONG_3,
@@ -164,14 +164,14 @@ static const struct dpu_lm_cfg sm8650_lm[] = {
}, {
.name = "lm_4", .id = LM_4,
.base = 0x48000, .len = 0x400,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_5,
.pingpong = PINGPONG_4,
}, {
.name = "lm_5", .id = LM_5,
.base = 0x49000, .len = 0x400,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_4,
.pingpong = PINGPONG_5,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
index 72a7257b4d7ba5bfe89ec76bac19550e023a2b50..5cc9f55d542b79bd2859cdd13d7f9640bf385866 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
@@ -133,7 +133,7 @@ static const struct dpu_lm_cfg sdm845_lm[] = {
{
.name = "lm_0", .id = LM_0,
.base = 0x44000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_1,
.pingpong = PINGPONG_0,
@@ -141,7 +141,7 @@ static const struct dpu_lm_cfg sdm845_lm[] = {
}, {
.name = "lm_1", .id = LM_1,
.base = 0x45000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_0,
.pingpong = PINGPONG_1,
@@ -149,7 +149,7 @@ static const struct dpu_lm_cfg sdm845_lm[] = {
}, {
.name = "lm_2", .id = LM_2,
.base = 0x46000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_5,
.pingpong = PINGPONG_2,
@@ -157,7 +157,7 @@ static const struct dpu_lm_cfg sdm845_lm[] = {
}, {
.name = "lm_5", .id = LM_5,
.base = 0x49000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_2,
.pingpong = PINGPONG_3,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h
index ce169a610e195cbb6f0fee1362bcaaf05df777cb..0f5e9babdeea837c77546cd60cf9b545434c9746 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h
@@ -68,7 +68,7 @@ static const struct dpu_lm_cfg sdm670_lm[] = {
{
.name = "lm_0", .id = LM_0,
.base = 0x44000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_1,
.pingpong = PINGPONG_0,
@@ -76,7 +76,7 @@ static const struct dpu_lm_cfg sdm670_lm[] = {
}, {
.name = "lm_1", .id = LM_1,
.base = 0x45000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_0,
.pingpong = PINGPONG_1,
@@ -84,14 +84,14 @@ static const struct dpu_lm_cfg sdm670_lm[] = {
}, {
.name = "lm_2", .id = LM_2,
.base = 0x46000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_5,
.pingpong = PINGPONG_2,
}, {
.name = "lm_5", .id = LM_5,
.base = 0x49000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_2,
.pingpong = PINGPONG_3,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
index 23a3a458dd5c260399a42e5f4d4361b3c4e82c4f..8e37c40620b62aacdcb47c7a04bcfce944ab0b4c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
@@ -136,7 +136,7 @@ static const struct dpu_lm_cfg sm8150_lm[] = {
{
.name = "lm_0", .id = LM_0,
.base = 0x44000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_1,
.pingpong = PINGPONG_0,
@@ -144,7 +144,7 @@ static const struct dpu_lm_cfg sm8150_lm[] = {
}, {
.name = "lm_1", .id = LM_1,
.base = 0x45000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_0,
.pingpong = PINGPONG_1,
@@ -152,7 +152,7 @@ static const struct dpu_lm_cfg sm8150_lm[] = {
}, {
.name = "lm_2", .id = LM_2,
.base = 0x46000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_3,
.pingpong = PINGPONG_2,
@@ -160,7 +160,7 @@ static const struct dpu_lm_cfg sm8150_lm[] = {
}, {
.name = "lm_3", .id = LM_3,
.base = 0x47000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_2,
.pingpong = PINGPONG_3,
@@ -168,14 +168,14 @@ static const struct dpu_lm_cfg sm8150_lm[] = {
}, {
.name = "lm_4", .id = LM_4,
.base = 0x48000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_5,
.pingpong = PINGPONG_4,
}, {
.name = "lm_5", .id = LM_5,
.base = 0x49000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_4,
.pingpong = PINGPONG_5,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
index 75f8f69123a4a6afe8234a9de21ce68b23c11605..a05d2ef8fc9d217898b8c12d4639563b28b4477b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
@@ -136,7 +136,7 @@ static const struct dpu_lm_cfg sc8180x_lm[] = {
{
.name = "lm_0", .id = LM_0,
.base = 0x44000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_1,
.pingpong = PINGPONG_0,
@@ -144,7 +144,7 @@ static const struct dpu_lm_cfg sc8180x_lm[] = {
}, {
.name = "lm_1", .id = LM_1,
.base = 0x45000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_0,
.pingpong = PINGPONG_1,
@@ -152,7 +152,7 @@ static const struct dpu_lm_cfg sc8180x_lm[] = {
}, {
.name = "lm_2", .id = LM_2,
.base = 0x46000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_3,
.pingpong = PINGPONG_2,
@@ -160,7 +160,7 @@ static const struct dpu_lm_cfg sc8180x_lm[] = {
}, {
.name = "lm_3", .id = LM_3,
.base = 0x47000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_2,
.pingpong = PINGPONG_3,
@@ -168,14 +168,14 @@ static const struct dpu_lm_cfg sc8180x_lm[] = {
}, {
.name = "lm_4", .id = LM_4,
.base = 0x48000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_5,
.pingpong = PINGPONG_4,
}, {
.name = "lm_5", .id = LM_5,
.base = 0x49000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_4,
.pingpong = PINGPONG_5,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
index 6b895eca2fac53505f7a1d857d30bb8a5d23d4c8..cb0b5687b5239418f50c539447f9cfa56e81fcc6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
@@ -109,7 +109,7 @@ static const struct dpu_lm_cfg sm7150_lm[] = {
{
.name = "lm_0", .id = LM_0,
.base = 0x44000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_1,
.pingpong = PINGPONG_0,
@@ -117,7 +117,7 @@ static const struct dpu_lm_cfg sm7150_lm[] = {
}, {
.name = "lm_1", .id = LM_1,
.base = 0x45000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_0,
.pingpong = PINGPONG_1,
@@ -125,14 +125,14 @@ static const struct dpu_lm_cfg sm7150_lm[] = {
}, {
.name = "lm_2", .id = LM_2,
.base = 0x46000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_3,
.pingpong = PINGPONG_2,
}, {
.name = "lm_3", .id = LM_3,
.base = 0x47000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_2,
.pingpong = PINGPONG_3,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
index e2306d314ef8f8b59078a8ca8c529f2e56385c98..8fb926bff36d32fb4ce1036cb69513599dc7b6b7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
@@ -107,20 +107,17 @@ static const struct dpu_lm_cfg sm6150_lm[] = {
{
.name = "lm_0", .id = LM_0,
.base = 0x44000, .len = 0x320,
- .features = MIXER_QCM2290_MASK,
.sblk = &sdm845_lm_sblk,
.pingpong = PINGPONG_0,
.dspp = DSPP_0,
}, {
.name = "lm_1", .id = LM_1,
.base = 0x45000, .len = 0x320,
- .features = MIXER_QCM2290_MASK,
.sblk = &sdm845_lm_sblk,
.pingpong = PINGPONG_1,
}, {
.name = "lm_2", .id = LM_2,
.base = 0x46000, .len = 0x320,
- .features = MIXER_QCM2290_MASK,
.sblk = &sdm845_lm_sblk,
.pingpong = PINGPONG_2,
},
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
index 62136811a530a6072accbd1ab3e02e7e24220ccb..5c2c8c5f812347970c534769d72f9699e6e7049a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
@@ -91,7 +91,6 @@ static const struct dpu_lm_cfg sm6125_lm[] = {
{
.name = "lm_0", .id = LM_0,
.base = 0x44000, .len = 0x320,
- .features = MIXER_QCM2290_MASK,
.sblk = &sdm845_lm_sblk,
.pingpong = PINGPONG_0,
.dspp = DSPP_0,
@@ -99,7 +98,6 @@ static const struct dpu_lm_cfg sm6125_lm[] = {
}, {
.name = "lm_1", .id = LM_1,
.base = 0x45000, .len = 0x320,
- .features = MIXER_QCM2290_MASK,
.sblk = &sdm845_lm_sblk,
.pingpong = PINGPONG_1,
.dspp = 0,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
index 34f11fb084c02cf994c272196299bb9f7bced4f1..17fa0ef9ac03e4649a218cd837b296211ef4506c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
@@ -135,7 +135,7 @@ static const struct dpu_lm_cfg sm8250_lm[] = {
{
.name = "lm_0", .id = LM_0,
.base = 0x44000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_1,
.pingpong = PINGPONG_0,
@@ -143,7 +143,7 @@ static const struct dpu_lm_cfg sm8250_lm[] = {
}, {
.name = "lm_1", .id = LM_1,
.base = 0x45000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_0,
.pingpong = PINGPONG_1,
@@ -151,7 +151,7 @@ static const struct dpu_lm_cfg sm8250_lm[] = {
}, {
.name = "lm_2", .id = LM_2,
.base = 0x46000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_3,
.pingpong = PINGPONG_2,
@@ -159,7 +159,7 @@ static const struct dpu_lm_cfg sm8250_lm[] = {
}, {
.name = "lm_3", .id = LM_3,
.base = 0x47000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_2,
.pingpong = PINGPONG_3,
@@ -167,14 +167,14 @@ static const struct dpu_lm_cfg sm8250_lm[] = {
}, {
.name = "lm_4", .id = LM_4,
.base = 0x48000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_5,
.pingpong = PINGPONG_4,
}, {
.name = "lm_5", .id = LM_5,
.base = 0x49000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_4,
.pingpong = PINGPONG_5,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
index 135b4f8171360493e58a1945105f8722d513d720..f6a0f1a39dcc3c9e82c07889d71905434274cdf9 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
@@ -84,7 +84,7 @@ static const struct dpu_lm_cfg sc7180_lm[] = {
{
.name = "lm_0", .id = LM_0,
.base = 0x44000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sc7180_lm_sblk,
.lm_pair = LM_1,
.pingpong = PINGPONG_0,
@@ -92,7 +92,7 @@ static const struct dpu_lm_cfg sc7180_lm[] = {
}, {
.name = "lm_1", .id = LM_1,
.base = 0x45000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sc7180_lm_sblk,
.lm_pair = LM_0,
.pingpong = PINGPONG_1,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
index 1189a5ecb3b7b50430eb275280c2309ee9d90b63..343ff5482382645fbd440d18d7ee46e5b3fc868c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
@@ -57,7 +57,6 @@ static const struct dpu_lm_cfg sm6115_lm[] = {
{
.name = "lm_0", .id = LM_0,
.base = 0x44000, .len = 0x320,
- .features = MIXER_QCM2290_MASK,
.sblk = &qcm2290_lm_sblk,
.pingpong = PINGPONG_0,
.dspp = DSPP_0,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
index 13ff6bdcc517fd566e7701f7a7cefe5ff19c5421..06bcaf4d8b0db74c349112af6884f7f3139a7ff8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
@@ -91,7 +91,7 @@ static const struct dpu_lm_cfg sm6350_lm[] = {
{
.name = "lm_0", .id = LM_0,
.base = 0x44000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sc7180_lm_sblk,
.lm_pair = LM_1,
.pingpong = PINGPONG_0,
@@ -99,7 +99,7 @@ static const struct dpu_lm_cfg sm6350_lm[] = {
}, {
.name = "lm_1", .id = LM_1,
.base = 0x45000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sc7180_lm_sblk,
.lm_pair = LM_0,
.pingpong = PINGPONG_1,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
index d4c2d2da91aac0bce46c4d65079f01484a769ae3..47053bf9b0a205302b3937e625fbeca8d17f0c82 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
@@ -57,7 +57,6 @@ static const struct dpu_lm_cfg qcm2290_lm[] = {
{
.name = "lm_0", .id = LM_0,
.base = 0x44000, .len = 0x320,
- .features = MIXER_QCM2290_MASK,
.sblk = &qcm2290_lm_sblk,
.pingpong = PINGPONG_0,
.dspp = DSPP_0,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
index 9135853a0225fa60acb80d17f627153d25c612e6..9c4e8450b67760c880d9bd2528c6a954a0282e08 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
@@ -58,7 +58,6 @@ static const struct dpu_lm_cfg sm6375_lm[] = {
{
.name = "lm_0", .id = LM_0,
.base = 0x44000, .len = 0x320,
- .features = MIXER_QCM2290_MASK,
.sblk = &qcm2290_lm_sblk,
.lm_pair = 0,
.pingpong = PINGPONG_0,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
index 6503f11f65c11806c5b9558a0f9fd05b228340be..e81a2a02e0a6379382058fd89500cf2064a2193f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
@@ -135,7 +135,7 @@ static const struct dpu_lm_cfg sm8350_lm[] = {
{
.name = "lm_0", .id = LM_0,
.base = 0x44000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_1,
.pingpong = PINGPONG_0,
@@ -143,7 +143,7 @@ static const struct dpu_lm_cfg sm8350_lm[] = {
}, {
.name = "lm_1", .id = LM_1,
.base = 0x45000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_0,
.pingpong = PINGPONG_1,
@@ -151,7 +151,7 @@ static const struct dpu_lm_cfg sm8350_lm[] = {
}, {
.name = "lm_2", .id = LM_2,
.base = 0x46000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_3,
.pingpong = PINGPONG_2,
@@ -159,7 +159,7 @@ static const struct dpu_lm_cfg sm8350_lm[] = {
}, {
.name = "lm_3", .id = LM_3,
.base = 0x47000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_2,
.pingpong = PINGPONG_3,
@@ -167,14 +167,14 @@ static const struct dpu_lm_cfg sm8350_lm[] = {
}, {
.name = "lm_4", .id = LM_4,
.base = 0x48000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_5,
.pingpong = PINGPONG_4,
}, {
.name = "lm_5", .id = LM_5,
.base = 0x49000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_4,
.pingpong = PINGPONG_5,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
index 202de6f9b0c65c6f2caa9e9d5232f5b92d8bdf01..b0e94ccf7f83e9c3c41f1df363cb6a8c24f1503d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
@@ -88,21 +88,21 @@ static const struct dpu_lm_cfg sc7280_lm[] = {
{
.name = "lm_0", .id = LM_0,
.base = 0x44000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sc7180_lm_sblk,
.pingpong = PINGPONG_0,
.dspp = DSPP_0,
}, {
.name = "lm_2", .id = LM_2,
.base = 0x46000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sc7180_lm_sblk,
.lm_pair = LM_3,
.pingpong = PINGPONG_2,
}, {
.name = "lm_3", .id = LM_3,
.base = 0x47000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sc7180_lm_sblk,
.lm_pair = LM_2,
.pingpong = PINGPONG_3,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
index 85778071bc1347008dbe4522aeb9ca4fd21aa097..2cf30234e45da8a7776d61c49c26abd75d070941 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
@@ -134,7 +134,7 @@ static const struct dpu_lm_cfg sc8280xp_lm[] = {
{
.name = "lm_0", .id = LM_0,
.base = 0x44000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_1,
.pingpong = PINGPONG_0,
@@ -142,7 +142,7 @@ static const struct dpu_lm_cfg sc8280xp_lm[] = {
}, {
.name = "lm_1", .id = LM_1,
.base = 0x45000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_0,
.pingpong = PINGPONG_1,
@@ -150,7 +150,7 @@ static const struct dpu_lm_cfg sc8280xp_lm[] = {
}, {
.name = "lm_2", .id = LM_2,
.base = 0x46000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_3,
.pingpong = PINGPONG_2,
@@ -158,7 +158,7 @@ static const struct dpu_lm_cfg sc8280xp_lm[] = {
}, {
.name = "lm_3", .id = LM_3,
.base = 0x47000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_2,
.pingpong = PINGPONG_3,
@@ -166,14 +166,14 @@ static const struct dpu_lm_cfg sc8280xp_lm[] = {
}, {
.name = "lm_4", .id = LM_4,
.base = 0x48000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_5,
.pingpong = PINGPONG_4,
}, {
.name = "lm_5", .id = LM_5,
.base = 0x49000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_4,
.pingpong = PINGPONG_5,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
index f9676f804f9132296467bc751e11036696afa942..dcef56683224b5715c2608b5472d2d5a0da62010 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
@@ -135,7 +135,7 @@ static const struct dpu_lm_cfg sm8450_lm[] = {
{
.name = "lm_0", .id = LM_0,
.base = 0x44000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_1,
.pingpong = PINGPONG_0,
@@ -143,7 +143,7 @@ static const struct dpu_lm_cfg sm8450_lm[] = {
}, {
.name = "lm_1", .id = LM_1,
.base = 0x45000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_0,
.pingpong = PINGPONG_1,
@@ -151,7 +151,7 @@ static const struct dpu_lm_cfg sm8450_lm[] = {
}, {
.name = "lm_2", .id = LM_2,
.base = 0x46000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_3,
.pingpong = PINGPONG_2,
@@ -159,7 +159,7 @@ static const struct dpu_lm_cfg sm8450_lm[] = {
}, {
.name = "lm_3", .id = LM_3,
.base = 0x47000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_2,
.pingpong = PINGPONG_3,
@@ -167,14 +167,14 @@ static const struct dpu_lm_cfg sm8450_lm[] = {
}, {
.name = "lm_4", .id = LM_4,
.base = 0x48000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_5,
.pingpong = PINGPONG_4,
}, {
.name = "lm_5", .id = LM_5,
.base = 0x49000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_4,
.pingpong = PINGPONG_5,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
index 7462cfc4cf8de4a10326c83d3341dbee76e437e8..5f5987d5fc602df29c5eb289823de5dd359df014 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
@@ -134,7 +134,7 @@ static const struct dpu_lm_cfg sa8775p_lm[] = {
{
.name = "lm_0", .id = LM_0,
.base = 0x44000, .len = 0x400,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_1,
.pingpong = PINGPONG_0,
@@ -142,7 +142,7 @@ static const struct dpu_lm_cfg sa8775p_lm[] = {
}, {
.name = "lm_1", .id = LM_1,
.base = 0x45000, .len = 0x400,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_0,
.pingpong = PINGPONG_1,
@@ -150,7 +150,7 @@ static const struct dpu_lm_cfg sa8775p_lm[] = {
}, {
.name = "lm_2", .id = LM_2,
.base = 0x46000, .len = 0x400,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_3,
.pingpong = PINGPONG_2,
@@ -158,7 +158,7 @@ static const struct dpu_lm_cfg sa8775p_lm[] = {
}, {
.name = "lm_3", .id = LM_3,
.base = 0x47000, .len = 0x400,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_2,
.pingpong = PINGPONG_3,
@@ -166,14 +166,14 @@ static const struct dpu_lm_cfg sa8775p_lm[] = {
}, {
.name = "lm_4", .id = LM_4,
.base = 0x48000, .len = 0x400,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_5,
.pingpong = PINGPONG_4,
}, {
.name = "lm_5", .id = LM_5,
.base = 0x49000, .len = 0x400,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_4,
.pingpong = PINGPONG_5,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
index 695ae7581a88b36fa1f28aa3cd0c9166090e940c..6f310216fbccb985308f617db20c1878e622340a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
@@ -132,7 +132,7 @@ static const struct dpu_lm_cfg sm8550_lm[] = {
{
.name = "lm_0", .id = LM_0,
.base = 0x44000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_1,
.pingpong = PINGPONG_0,
@@ -140,7 +140,7 @@ static const struct dpu_lm_cfg sm8550_lm[] = {
}, {
.name = "lm_1", .id = LM_1,
.base = 0x45000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_0,
.pingpong = PINGPONG_1,
@@ -148,7 +148,7 @@ static const struct dpu_lm_cfg sm8550_lm[] = {
}, {
.name = "lm_2", .id = LM_2,
.base = 0x46000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_3,
.pingpong = PINGPONG_2,
@@ -156,7 +156,7 @@ static const struct dpu_lm_cfg sm8550_lm[] = {
}, {
.name = "lm_3", .id = LM_3,
.base = 0x47000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_2,
.pingpong = PINGPONG_3,
@@ -164,14 +164,14 @@ static const struct dpu_lm_cfg sm8550_lm[] = {
}, {
.name = "lm_4", .id = LM_4,
.base = 0x48000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_5,
.pingpong = PINGPONG_4,
}, {
.name = "lm_5", .id = LM_5,
.base = 0x49000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_4,
.pingpong = PINGPONG_5,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
index 9a25113df5aec527baa514aaa61f2b47c2443d27..ba8a2c5dc5e2b3474b295c86afbbbe8f8d416ccd 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
@@ -132,7 +132,7 @@ static const struct dpu_lm_cfg sar2130p_lm[] = {
{
.name = "lm_0", .id = LM_0,
.base = 0x44000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_1,
.pingpong = PINGPONG_0,
@@ -140,7 +140,7 @@ static const struct dpu_lm_cfg sar2130p_lm[] = {
}, {
.name = "lm_1", .id = LM_1,
.base = 0x45000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_0,
.pingpong = PINGPONG_1,
@@ -148,7 +148,7 @@ static const struct dpu_lm_cfg sar2130p_lm[] = {
}, {
.name = "lm_2", .id = LM_2,
.base = 0x46000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_3,
.pingpong = PINGPONG_2,
@@ -156,7 +156,7 @@ static const struct dpu_lm_cfg sar2130p_lm[] = {
}, {
.name = "lm_3", .id = LM_3,
.base = 0x47000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_2,
.pingpong = PINGPONG_3,
@@ -164,14 +164,14 @@ static const struct dpu_lm_cfg sar2130p_lm[] = {
}, {
.name = "lm_4", .id = LM_4,
.base = 0x48000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_5,
.pingpong = PINGPONG_4,
}, {
.name = "lm_5", .id = LM_5,
.base = 0x49000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_4,
.pingpong = PINGPONG_5,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
index 54815c613f087454aa7b4befc84462265d8dfc23..77986a7bd62c1b6323482426e596e5974ba40865 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
@@ -131,7 +131,7 @@ static const struct dpu_lm_cfg x1e80100_lm[] = {
{
.name = "lm_0", .id = LM_0,
.base = 0x44000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_1,
.pingpong = PINGPONG_0,
@@ -139,7 +139,7 @@ static const struct dpu_lm_cfg x1e80100_lm[] = {
}, {
.name = "lm_1", .id = LM_1,
.base = 0x45000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_0,
.pingpong = PINGPONG_1,
@@ -147,7 +147,7 @@ static const struct dpu_lm_cfg x1e80100_lm[] = {
}, {
.name = "lm_2", .id = LM_2,
.base = 0x46000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_3,
.pingpong = PINGPONG_2,
@@ -155,7 +155,7 @@ static const struct dpu_lm_cfg x1e80100_lm[] = {
}, {
.name = "lm_3", .id = LM_3,
.base = 0x47000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_2,
.pingpong = PINGPONG_3,
@@ -163,14 +163,14 @@ static const struct dpu_lm_cfg x1e80100_lm[] = {
}, {
.name = "lm_4", .id = LM_4,
.base = 0x48000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_5,
.pingpong = PINGPONG_4,
}, {
.name = "lm_5", .id = LM_5,
.base = 0x49000, .len = 0x320,
- .features = MIXER_SDM845_MASK,
+ .features = MIXER_MSM8998_MASK,
.sblk = &sdm845_lm_sblk,
.lm_pair = LM_4,
.pingpong = PINGPONG_5,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index d64ebc729bfb589bf90af89c094181f879d5b1ef..ad0460aa5b5ce5a373dab18c89e4159855da4d2b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -89,12 +89,6 @@
#define MIXER_MSM8998_MASK \
(BIT(DPU_MIXER_SOURCESPLIT))
-#define MIXER_SDM845_MASK \
- (BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER))
-
-#define MIXER_QCM2290_MASK \
- (BIT(DPU_DIM_LAYER))
-
#define WB_SDM845_MASK (BIT(DPU_WB_LINE_MODE) | \
BIT(DPU_WB_UBWC) | \
BIT(DPU_WB_YUV_CONFIG) | \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 5e4608d10c6d4fee387c9a599a73b15661148430..cc17b20a7d4c15b0cd9c5dc8b9a4b78d4cb78315 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -84,14 +84,12 @@ enum {
* @DPU_MIXER_LAYER Layer mixer layer blend configuration,
* @DPU_MIXER_SOURCESPLIT Layer mixer supports source-split configuration
* @DPU_MIXER_GC Gamma correction block
- * @DPU_DIM_LAYER Layer mixer supports dim layer
* @DPU_MIXER_MAX maximum value
*/
enum {
DPU_MIXER_LAYER = 0x1,
DPU_MIXER_SOURCESPLIT,
DPU_MIXER_GC,
- DPU_DIM_LAYER,
DPU_MIXER_MAX
};
--
2.39.5
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH v4 22/30] drm/msm/dpu: get rid of DPU_DIM_LAYER
2025-05-19 16:04 ` [PATCH v4 22/30] drm/msm/dpu: get rid of DPU_DIM_LAYER Dmitry Baryshkov
@ 2025-05-20 8:03 ` neil.armstrong
0 siblings, 0 replies; 64+ messages in thread
From: neil.armstrong @ 2025-05-20 8:03 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Abhinav Kumar, Sean Paul,
Marijn Suijten, David Airlie, Simona Vetter, Vinod Koul,
Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel,
Dmitry Baryshkov
On 19/05/2025 18:04, Dmitry Baryshkov wrote:
> From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>
> Continue migration to the MDSS-revision based checks and drop the
> DPU_DIM_LAYER feature bit. It is currently unused, but can be replaed
> with the core_major_ver >= 4 check.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 12 ++++++------
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 8 ++++----
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h | 8 ++++----
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 12 ++++++------
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 12 ++++++------
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h | 8 ++++----
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h | 3 ---
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 2 --
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 12 ++++++------
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 4 ++--
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 1 -
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 4 ++--
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 1 -
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 1 -
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 12 ++++++------
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 6 +++---
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 12 ++++++------
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 12 ++++++------
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 12 ++++++------
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 12 ++++++------
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h | 12 ++++++------
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 12 ++++++------
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 6 ------
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 --
> 24 files changed, 85 insertions(+), 101 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
> index ae66c338250664f9306a7d431cfa18ca07a916a5..9a8f6043370997cb12414c4132eb68cc73f7030a 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
> @@ -132,7 +132,7 @@ static const struct dpu_lm_cfg sm8650_lm[] = {
> {
> .name = "lm_0", .id = LM_0,
> .base = 0x44000, .len = 0x400,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_1,
> .pingpong = PINGPONG_0,
> @@ -140,7 +140,7 @@ static const struct dpu_lm_cfg sm8650_lm[] = {
> }, {
> .name = "lm_1", .id = LM_1,
> .base = 0x45000, .len = 0x400,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_0,
> .pingpong = PINGPONG_1,
> @@ -148,7 +148,7 @@ static const struct dpu_lm_cfg sm8650_lm[] = {
> }, {
> .name = "lm_2", .id = LM_2,
> .base = 0x46000, .len = 0x400,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_3,
> .pingpong = PINGPONG_2,
> @@ -156,7 +156,7 @@ static const struct dpu_lm_cfg sm8650_lm[] = {
> }, {
> .name = "lm_3", .id = LM_3,
> .base = 0x47000, .len = 0x400,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_2,
> .pingpong = PINGPONG_3,
> @@ -164,14 +164,14 @@ static const struct dpu_lm_cfg sm8650_lm[] = {
> }, {
> .name = "lm_4", .id = LM_4,
> .base = 0x48000, .len = 0x400,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_5,
> .pingpong = PINGPONG_4,
> }, {
> .name = "lm_5", .id = LM_5,
> .base = 0x49000, .len = 0x400,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_4,
> .pingpong = PINGPONG_5,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> index 72a7257b4d7ba5bfe89ec76bac19550e023a2b50..5cc9f55d542b79bd2859cdd13d7f9640bf385866 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> @@ -133,7 +133,7 @@ static const struct dpu_lm_cfg sdm845_lm[] = {
> {
> .name = "lm_0", .id = LM_0,
> .base = 0x44000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_1,
> .pingpong = PINGPONG_0,
> @@ -141,7 +141,7 @@ static const struct dpu_lm_cfg sdm845_lm[] = {
> }, {
> .name = "lm_1", .id = LM_1,
> .base = 0x45000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_0,
> .pingpong = PINGPONG_1,
> @@ -149,7 +149,7 @@ static const struct dpu_lm_cfg sdm845_lm[] = {
> }, {
> .name = "lm_2", .id = LM_2,
> .base = 0x46000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_5,
> .pingpong = PINGPONG_2,
> @@ -157,7 +157,7 @@ static const struct dpu_lm_cfg sdm845_lm[] = {
> }, {
> .name = "lm_5", .id = LM_5,
> .base = 0x49000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_2,
> .pingpong = PINGPONG_3,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h
> index ce169a610e195cbb6f0fee1362bcaaf05df777cb..0f5e9babdeea837c77546cd60cf9b545434c9746 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h
> @@ -68,7 +68,7 @@ static const struct dpu_lm_cfg sdm670_lm[] = {
> {
> .name = "lm_0", .id = LM_0,
> .base = 0x44000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_1,
> .pingpong = PINGPONG_0,
> @@ -76,7 +76,7 @@ static const struct dpu_lm_cfg sdm670_lm[] = {
> }, {
> .name = "lm_1", .id = LM_1,
> .base = 0x45000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_0,
> .pingpong = PINGPONG_1,
> @@ -84,14 +84,14 @@ static const struct dpu_lm_cfg sdm670_lm[] = {
> }, {
> .name = "lm_2", .id = LM_2,
> .base = 0x46000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_5,
> .pingpong = PINGPONG_2,
> }, {
> .name = "lm_5", .id = LM_5,
> .base = 0x49000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_2,
> .pingpong = PINGPONG_3,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> index 23a3a458dd5c260399a42e5f4d4361b3c4e82c4f..8e37c40620b62aacdcb47c7a04bcfce944ab0b4c 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> @@ -136,7 +136,7 @@ static const struct dpu_lm_cfg sm8150_lm[] = {
> {
> .name = "lm_0", .id = LM_0,
> .base = 0x44000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_1,
> .pingpong = PINGPONG_0,
> @@ -144,7 +144,7 @@ static const struct dpu_lm_cfg sm8150_lm[] = {
> }, {
> .name = "lm_1", .id = LM_1,
> .base = 0x45000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_0,
> .pingpong = PINGPONG_1,
> @@ -152,7 +152,7 @@ static const struct dpu_lm_cfg sm8150_lm[] = {
> }, {
> .name = "lm_2", .id = LM_2,
> .base = 0x46000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_3,
> .pingpong = PINGPONG_2,
> @@ -160,7 +160,7 @@ static const struct dpu_lm_cfg sm8150_lm[] = {
> }, {
> .name = "lm_3", .id = LM_3,
> .base = 0x47000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_2,
> .pingpong = PINGPONG_3,
> @@ -168,14 +168,14 @@ static const struct dpu_lm_cfg sm8150_lm[] = {
> }, {
> .name = "lm_4", .id = LM_4,
> .base = 0x48000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_5,
> .pingpong = PINGPONG_4,
> }, {
> .name = "lm_5", .id = LM_5,
> .base = 0x49000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_4,
> .pingpong = PINGPONG_5,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> index 75f8f69123a4a6afe8234a9de21ce68b23c11605..a05d2ef8fc9d217898b8c12d4639563b28b4477b 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> @@ -136,7 +136,7 @@ static const struct dpu_lm_cfg sc8180x_lm[] = {
> {
> .name = "lm_0", .id = LM_0,
> .base = 0x44000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_1,
> .pingpong = PINGPONG_0,
> @@ -144,7 +144,7 @@ static const struct dpu_lm_cfg sc8180x_lm[] = {
> }, {
> .name = "lm_1", .id = LM_1,
> .base = 0x45000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_0,
> .pingpong = PINGPONG_1,
> @@ -152,7 +152,7 @@ static const struct dpu_lm_cfg sc8180x_lm[] = {
> }, {
> .name = "lm_2", .id = LM_2,
> .base = 0x46000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_3,
> .pingpong = PINGPONG_2,
> @@ -160,7 +160,7 @@ static const struct dpu_lm_cfg sc8180x_lm[] = {
> }, {
> .name = "lm_3", .id = LM_3,
> .base = 0x47000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_2,
> .pingpong = PINGPONG_3,
> @@ -168,14 +168,14 @@ static const struct dpu_lm_cfg sc8180x_lm[] = {
> }, {
> .name = "lm_4", .id = LM_4,
> .base = 0x48000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_5,
> .pingpong = PINGPONG_4,
> }, {
> .name = "lm_5", .id = LM_5,
> .base = 0x49000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_4,
> .pingpong = PINGPONG_5,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
> index 6b895eca2fac53505f7a1d857d30bb8a5d23d4c8..cb0b5687b5239418f50c539447f9cfa56e81fcc6 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
> @@ -109,7 +109,7 @@ static const struct dpu_lm_cfg sm7150_lm[] = {
> {
> .name = "lm_0", .id = LM_0,
> .base = 0x44000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_1,
> .pingpong = PINGPONG_0,
> @@ -117,7 +117,7 @@ static const struct dpu_lm_cfg sm7150_lm[] = {
> }, {
> .name = "lm_1", .id = LM_1,
> .base = 0x45000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_0,
> .pingpong = PINGPONG_1,
> @@ -125,14 +125,14 @@ static const struct dpu_lm_cfg sm7150_lm[] = {
> }, {
> .name = "lm_2", .id = LM_2,
> .base = 0x46000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_3,
> .pingpong = PINGPONG_2,
> }, {
> .name = "lm_3", .id = LM_3,
> .base = 0x47000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_2,
> .pingpong = PINGPONG_3,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
> index e2306d314ef8f8b59078a8ca8c529f2e56385c98..8fb926bff36d32fb4ce1036cb69513599dc7b6b7 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
> @@ -107,20 +107,17 @@ static const struct dpu_lm_cfg sm6150_lm[] = {
> {
> .name = "lm_0", .id = LM_0,
> .base = 0x44000, .len = 0x320,
> - .features = MIXER_QCM2290_MASK,
> .sblk = &sdm845_lm_sblk,
> .pingpong = PINGPONG_0,
> .dspp = DSPP_0,
> }, {
> .name = "lm_1", .id = LM_1,
> .base = 0x45000, .len = 0x320,
> - .features = MIXER_QCM2290_MASK,
> .sblk = &sdm845_lm_sblk,
> .pingpong = PINGPONG_1,
> }, {
> .name = "lm_2", .id = LM_2,
> .base = 0x46000, .len = 0x320,
> - .features = MIXER_QCM2290_MASK,
> .sblk = &sdm845_lm_sblk,
> .pingpong = PINGPONG_2,
> },
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
> index 62136811a530a6072accbd1ab3e02e7e24220ccb..5c2c8c5f812347970c534769d72f9699e6e7049a 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
> @@ -91,7 +91,6 @@ static const struct dpu_lm_cfg sm6125_lm[] = {
> {
> .name = "lm_0", .id = LM_0,
> .base = 0x44000, .len = 0x320,
> - .features = MIXER_QCM2290_MASK,
> .sblk = &sdm845_lm_sblk,
> .pingpong = PINGPONG_0,
> .dspp = DSPP_0,
> @@ -99,7 +98,6 @@ static const struct dpu_lm_cfg sm6125_lm[] = {
> }, {
> .name = "lm_1", .id = LM_1,
> .base = 0x45000, .len = 0x320,
> - .features = MIXER_QCM2290_MASK,
> .sblk = &sdm845_lm_sblk,
> .pingpong = PINGPONG_1,
> .dspp = 0,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> index 34f11fb084c02cf994c272196299bb9f7bced4f1..17fa0ef9ac03e4649a218cd837b296211ef4506c 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> @@ -135,7 +135,7 @@ static const struct dpu_lm_cfg sm8250_lm[] = {
> {
> .name = "lm_0", .id = LM_0,
> .base = 0x44000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_1,
> .pingpong = PINGPONG_0,
> @@ -143,7 +143,7 @@ static const struct dpu_lm_cfg sm8250_lm[] = {
> }, {
> .name = "lm_1", .id = LM_1,
> .base = 0x45000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_0,
> .pingpong = PINGPONG_1,
> @@ -151,7 +151,7 @@ static const struct dpu_lm_cfg sm8250_lm[] = {
> }, {
> .name = "lm_2", .id = LM_2,
> .base = 0x46000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_3,
> .pingpong = PINGPONG_2,
> @@ -159,7 +159,7 @@ static const struct dpu_lm_cfg sm8250_lm[] = {
> }, {
> .name = "lm_3", .id = LM_3,
> .base = 0x47000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_2,
> .pingpong = PINGPONG_3,
> @@ -167,14 +167,14 @@ static const struct dpu_lm_cfg sm8250_lm[] = {
> }, {
> .name = "lm_4", .id = LM_4,
> .base = 0x48000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_5,
> .pingpong = PINGPONG_4,
> }, {
> .name = "lm_5", .id = LM_5,
> .base = 0x49000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_4,
> .pingpong = PINGPONG_5,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> index 135b4f8171360493e58a1945105f8722d513d720..f6a0f1a39dcc3c9e82c07889d71905434274cdf9 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> @@ -84,7 +84,7 @@ static const struct dpu_lm_cfg sc7180_lm[] = {
> {
> .name = "lm_0", .id = LM_0,
> .base = 0x44000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sc7180_lm_sblk,
> .lm_pair = LM_1,
> .pingpong = PINGPONG_0,
> @@ -92,7 +92,7 @@ static const struct dpu_lm_cfg sc7180_lm[] = {
> }, {
> .name = "lm_1", .id = LM_1,
> .base = 0x45000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sc7180_lm_sblk,
> .lm_pair = LM_0,
> .pingpong = PINGPONG_1,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> index 1189a5ecb3b7b50430eb275280c2309ee9d90b63..343ff5482382645fbd440d18d7ee46e5b3fc868c 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> @@ -57,7 +57,6 @@ static const struct dpu_lm_cfg sm6115_lm[] = {
> {
> .name = "lm_0", .id = LM_0,
> .base = 0x44000, .len = 0x320,
> - .features = MIXER_QCM2290_MASK,
> .sblk = &qcm2290_lm_sblk,
> .pingpong = PINGPONG_0,
> .dspp = DSPP_0,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> index 13ff6bdcc517fd566e7701f7a7cefe5ff19c5421..06bcaf4d8b0db74c349112af6884f7f3139a7ff8 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> @@ -91,7 +91,7 @@ static const struct dpu_lm_cfg sm6350_lm[] = {
> {
> .name = "lm_0", .id = LM_0,
> .base = 0x44000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sc7180_lm_sblk,
> .lm_pair = LM_1,
> .pingpong = PINGPONG_0,
> @@ -99,7 +99,7 @@ static const struct dpu_lm_cfg sm6350_lm[] = {
> }, {
> .name = "lm_1", .id = LM_1,
> .base = 0x45000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sc7180_lm_sblk,
> .lm_pair = LM_0,
> .pingpong = PINGPONG_1,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> index d4c2d2da91aac0bce46c4d65079f01484a769ae3..47053bf9b0a205302b3937e625fbeca8d17f0c82 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> @@ -57,7 +57,6 @@ static const struct dpu_lm_cfg qcm2290_lm[] = {
> {
> .name = "lm_0", .id = LM_0,
> .base = 0x44000, .len = 0x320,
> - .features = MIXER_QCM2290_MASK,
> .sblk = &qcm2290_lm_sblk,
> .pingpong = PINGPONG_0,
> .dspp = DSPP_0,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
> index 9135853a0225fa60acb80d17f627153d25c612e6..9c4e8450b67760c880d9bd2528c6a954a0282e08 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
> @@ -58,7 +58,6 @@ static const struct dpu_lm_cfg sm6375_lm[] = {
> {
> .name = "lm_0", .id = LM_0,
> .base = 0x44000, .len = 0x320,
> - .features = MIXER_QCM2290_MASK,
> .sblk = &qcm2290_lm_sblk,
> .lm_pair = 0,
> .pingpong = PINGPONG_0,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> index 6503f11f65c11806c5b9558a0f9fd05b228340be..e81a2a02e0a6379382058fd89500cf2064a2193f 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> @@ -135,7 +135,7 @@ static const struct dpu_lm_cfg sm8350_lm[] = {
> {
> .name = "lm_0", .id = LM_0,
> .base = 0x44000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_1,
> .pingpong = PINGPONG_0,
> @@ -143,7 +143,7 @@ static const struct dpu_lm_cfg sm8350_lm[] = {
> }, {
> .name = "lm_1", .id = LM_1,
> .base = 0x45000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_0,
> .pingpong = PINGPONG_1,
> @@ -151,7 +151,7 @@ static const struct dpu_lm_cfg sm8350_lm[] = {
> }, {
> .name = "lm_2", .id = LM_2,
> .base = 0x46000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_3,
> .pingpong = PINGPONG_2,
> @@ -159,7 +159,7 @@ static const struct dpu_lm_cfg sm8350_lm[] = {
> }, {
> .name = "lm_3", .id = LM_3,
> .base = 0x47000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_2,
> .pingpong = PINGPONG_3,
> @@ -167,14 +167,14 @@ static const struct dpu_lm_cfg sm8350_lm[] = {
> }, {
> .name = "lm_4", .id = LM_4,
> .base = 0x48000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_5,
> .pingpong = PINGPONG_4,
> }, {
> .name = "lm_5", .id = LM_5,
> .base = 0x49000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_4,
> .pingpong = PINGPONG_5,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> index 202de6f9b0c65c6f2caa9e9d5232f5b92d8bdf01..b0e94ccf7f83e9c3c41f1df363cb6a8c24f1503d 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> @@ -88,21 +88,21 @@ static const struct dpu_lm_cfg sc7280_lm[] = {
> {
> .name = "lm_0", .id = LM_0,
> .base = 0x44000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sc7180_lm_sblk,
> .pingpong = PINGPONG_0,
> .dspp = DSPP_0,
> }, {
> .name = "lm_2", .id = LM_2,
> .base = 0x46000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sc7180_lm_sblk,
> .lm_pair = LM_3,
> .pingpong = PINGPONG_2,
> }, {
> .name = "lm_3", .id = LM_3,
> .base = 0x47000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sc7180_lm_sblk,
> .lm_pair = LM_2,
> .pingpong = PINGPONG_3,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> index 85778071bc1347008dbe4522aeb9ca4fd21aa097..2cf30234e45da8a7776d61c49c26abd75d070941 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> @@ -134,7 +134,7 @@ static const struct dpu_lm_cfg sc8280xp_lm[] = {
> {
> .name = "lm_0", .id = LM_0,
> .base = 0x44000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_1,
> .pingpong = PINGPONG_0,
> @@ -142,7 +142,7 @@ static const struct dpu_lm_cfg sc8280xp_lm[] = {
> }, {
> .name = "lm_1", .id = LM_1,
> .base = 0x45000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_0,
> .pingpong = PINGPONG_1,
> @@ -150,7 +150,7 @@ static const struct dpu_lm_cfg sc8280xp_lm[] = {
> }, {
> .name = "lm_2", .id = LM_2,
> .base = 0x46000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_3,
> .pingpong = PINGPONG_2,
> @@ -158,7 +158,7 @@ static const struct dpu_lm_cfg sc8280xp_lm[] = {
> }, {
> .name = "lm_3", .id = LM_3,
> .base = 0x47000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_2,
> .pingpong = PINGPONG_3,
> @@ -166,14 +166,14 @@ static const struct dpu_lm_cfg sc8280xp_lm[] = {
> }, {
> .name = "lm_4", .id = LM_4,
> .base = 0x48000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_5,
> .pingpong = PINGPONG_4,
> }, {
> .name = "lm_5", .id = LM_5,
> .base = 0x49000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_4,
> .pingpong = PINGPONG_5,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> index f9676f804f9132296467bc751e11036696afa942..dcef56683224b5715c2608b5472d2d5a0da62010 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> @@ -135,7 +135,7 @@ static const struct dpu_lm_cfg sm8450_lm[] = {
> {
> .name = "lm_0", .id = LM_0,
> .base = 0x44000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_1,
> .pingpong = PINGPONG_0,
> @@ -143,7 +143,7 @@ static const struct dpu_lm_cfg sm8450_lm[] = {
> }, {
> .name = "lm_1", .id = LM_1,
> .base = 0x45000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_0,
> .pingpong = PINGPONG_1,
> @@ -151,7 +151,7 @@ static const struct dpu_lm_cfg sm8450_lm[] = {
> }, {
> .name = "lm_2", .id = LM_2,
> .base = 0x46000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_3,
> .pingpong = PINGPONG_2,
> @@ -159,7 +159,7 @@ static const struct dpu_lm_cfg sm8450_lm[] = {
> }, {
> .name = "lm_3", .id = LM_3,
> .base = 0x47000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_2,
> .pingpong = PINGPONG_3,
> @@ -167,14 +167,14 @@ static const struct dpu_lm_cfg sm8450_lm[] = {
> }, {
> .name = "lm_4", .id = LM_4,
> .base = 0x48000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_5,
> .pingpong = PINGPONG_4,
> }, {
> .name = "lm_5", .id = LM_5,
> .base = 0x49000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_4,
> .pingpong = PINGPONG_5,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
> index 7462cfc4cf8de4a10326c83d3341dbee76e437e8..5f5987d5fc602df29c5eb289823de5dd359df014 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
> @@ -134,7 +134,7 @@ static const struct dpu_lm_cfg sa8775p_lm[] = {
> {
> .name = "lm_0", .id = LM_0,
> .base = 0x44000, .len = 0x400,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_1,
> .pingpong = PINGPONG_0,
> @@ -142,7 +142,7 @@ static const struct dpu_lm_cfg sa8775p_lm[] = {
> }, {
> .name = "lm_1", .id = LM_1,
> .base = 0x45000, .len = 0x400,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_0,
> .pingpong = PINGPONG_1,
> @@ -150,7 +150,7 @@ static const struct dpu_lm_cfg sa8775p_lm[] = {
> }, {
> .name = "lm_2", .id = LM_2,
> .base = 0x46000, .len = 0x400,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_3,
> .pingpong = PINGPONG_2,
> @@ -158,7 +158,7 @@ static const struct dpu_lm_cfg sa8775p_lm[] = {
> }, {
> .name = "lm_3", .id = LM_3,
> .base = 0x47000, .len = 0x400,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_2,
> .pingpong = PINGPONG_3,
> @@ -166,14 +166,14 @@ static const struct dpu_lm_cfg sa8775p_lm[] = {
> }, {
> .name = "lm_4", .id = LM_4,
> .base = 0x48000, .len = 0x400,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_5,
> .pingpong = PINGPONG_4,
> }, {
> .name = "lm_5", .id = LM_5,
> .base = 0x49000, .len = 0x400,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_4,
> .pingpong = PINGPONG_5,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> index 695ae7581a88b36fa1f28aa3cd0c9166090e940c..6f310216fbccb985308f617db20c1878e622340a 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> @@ -132,7 +132,7 @@ static const struct dpu_lm_cfg sm8550_lm[] = {
> {
> .name = "lm_0", .id = LM_0,
> .base = 0x44000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_1,
> .pingpong = PINGPONG_0,
> @@ -140,7 +140,7 @@ static const struct dpu_lm_cfg sm8550_lm[] = {
> }, {
> .name = "lm_1", .id = LM_1,
> .base = 0x45000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_0,
> .pingpong = PINGPONG_1,
> @@ -148,7 +148,7 @@ static const struct dpu_lm_cfg sm8550_lm[] = {
> }, {
> .name = "lm_2", .id = LM_2,
> .base = 0x46000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_3,
> .pingpong = PINGPONG_2,
> @@ -156,7 +156,7 @@ static const struct dpu_lm_cfg sm8550_lm[] = {
> }, {
> .name = "lm_3", .id = LM_3,
> .base = 0x47000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_2,
> .pingpong = PINGPONG_3,
> @@ -164,14 +164,14 @@ static const struct dpu_lm_cfg sm8550_lm[] = {
> }, {
> .name = "lm_4", .id = LM_4,
> .base = 0x48000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_5,
> .pingpong = PINGPONG_4,
> }, {
> .name = "lm_5", .id = LM_5,
> .base = 0x49000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_4,
> .pingpong = PINGPONG_5,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
> index 9a25113df5aec527baa514aaa61f2b47c2443d27..ba8a2c5dc5e2b3474b295c86afbbbe8f8d416ccd 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
> @@ -132,7 +132,7 @@ static const struct dpu_lm_cfg sar2130p_lm[] = {
> {
> .name = "lm_0", .id = LM_0,
> .base = 0x44000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_1,
> .pingpong = PINGPONG_0,
> @@ -140,7 +140,7 @@ static const struct dpu_lm_cfg sar2130p_lm[] = {
> }, {
> .name = "lm_1", .id = LM_1,
> .base = 0x45000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_0,
> .pingpong = PINGPONG_1,
> @@ -148,7 +148,7 @@ static const struct dpu_lm_cfg sar2130p_lm[] = {
> }, {
> .name = "lm_2", .id = LM_2,
> .base = 0x46000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_3,
> .pingpong = PINGPONG_2,
> @@ -156,7 +156,7 @@ static const struct dpu_lm_cfg sar2130p_lm[] = {
> }, {
> .name = "lm_3", .id = LM_3,
> .base = 0x47000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_2,
> .pingpong = PINGPONG_3,
> @@ -164,14 +164,14 @@ static const struct dpu_lm_cfg sar2130p_lm[] = {
> }, {
> .name = "lm_4", .id = LM_4,
> .base = 0x48000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_5,
> .pingpong = PINGPONG_4,
> }, {
> .name = "lm_5", .id = LM_5,
> .base = 0x49000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_4,
> .pingpong = PINGPONG_5,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
> index 54815c613f087454aa7b4befc84462265d8dfc23..77986a7bd62c1b6323482426e596e5974ba40865 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
> @@ -131,7 +131,7 @@ static const struct dpu_lm_cfg x1e80100_lm[] = {
> {
> .name = "lm_0", .id = LM_0,
> .base = 0x44000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_1,
> .pingpong = PINGPONG_0,
> @@ -139,7 +139,7 @@ static const struct dpu_lm_cfg x1e80100_lm[] = {
> }, {
> .name = "lm_1", .id = LM_1,
> .base = 0x45000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_0,
> .pingpong = PINGPONG_1,
> @@ -147,7 +147,7 @@ static const struct dpu_lm_cfg x1e80100_lm[] = {
> }, {
> .name = "lm_2", .id = LM_2,
> .base = 0x46000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_3,
> .pingpong = PINGPONG_2,
> @@ -155,7 +155,7 @@ static const struct dpu_lm_cfg x1e80100_lm[] = {
> }, {
> .name = "lm_3", .id = LM_3,
> .base = 0x47000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_2,
> .pingpong = PINGPONG_3,
> @@ -163,14 +163,14 @@ static const struct dpu_lm_cfg x1e80100_lm[] = {
> }, {
> .name = "lm_4", .id = LM_4,
> .base = 0x48000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_5,
> .pingpong = PINGPONG_4,
> }, {
> .name = "lm_5", .id = LM_5,
> .base = 0x49000, .len = 0x320,
> - .features = MIXER_SDM845_MASK,
> + .features = MIXER_MSM8998_MASK,
> .sblk = &sdm845_lm_sblk,
> .lm_pair = LM_4,
> .pingpong = PINGPONG_5,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index d64ebc729bfb589bf90af89c094181f879d5b1ef..ad0460aa5b5ce5a373dab18c89e4159855da4d2b 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -89,12 +89,6 @@
> #define MIXER_MSM8998_MASK \
> (BIT(DPU_MIXER_SOURCESPLIT))
>
> -#define MIXER_SDM845_MASK \
> - (BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER))
> -
> -#define MIXER_QCM2290_MASK \
> - (BIT(DPU_DIM_LAYER))
> -
> #define WB_SDM845_MASK (BIT(DPU_WB_LINE_MODE) | \
> BIT(DPU_WB_UBWC) | \
> BIT(DPU_WB_YUV_CONFIG) | \
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index 5e4608d10c6d4fee387c9a599a73b15661148430..cc17b20a7d4c15b0cd9c5dc8b9a4b78d4cb78315 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -84,14 +84,12 @@ enum {
> * @DPU_MIXER_LAYER Layer mixer layer blend configuration,
> * @DPU_MIXER_SOURCESPLIT Layer mixer supports source-split configuration
> * @DPU_MIXER_GC Gamma correction block
> - * @DPU_DIM_LAYER Layer mixer supports dim layer
> * @DPU_MIXER_MAX maximum value
> */
> enum {
> DPU_MIXER_LAYER = 0x1,
> DPU_MIXER_SOURCESPLIT,
> DPU_MIXER_GC,
> - DPU_DIM_LAYER,
> DPU_MIXER_MAX
> };
>
>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH v4 23/30] drm/msm/dpu: get rid of DPU_DSC_HW_REV_1_2
2025-05-19 16:04 [PATCH v4 00/30] drm/msm/dpu: rework HW block feature handling Dmitry Baryshkov
` (21 preceding siblings ...)
2025-05-19 16:04 ` [PATCH v4 22/30] drm/msm/dpu: get rid of DPU_DIM_LAYER Dmitry Baryshkov
@ 2025-05-19 16:04 ` Dmitry Baryshkov
2025-05-20 8:03 ` neil.armstrong
2025-05-19 16:04 ` [PATCH v4 24/30] drm/msm/dpu: get rid of DPU_DSC_OUTPUT_CTRL Dmitry Baryshkov
` (6 subsequent siblings)
29 siblings, 1 reply; 64+ messages in thread
From: Dmitry Baryshkov @ 2025-05-19 16:04 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Sean Paul, Marijn Suijten, David Airlie,
Simona Vetter, Vinod Koul, Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel,
Dmitry Baryshkov
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Continue migration to the MDSS-revision based checks and replace
DPU_DSC_HW_REV_1_2 feature bit with the core_major_ver >= 7 check.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 10 ++++------
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 6 ++----
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 8 ++------
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 6 ++----
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 8 ++------
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 6 ++----
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h | 6 ++----
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 6 ++----
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 --
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 2 +-
12 files changed, 21 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
index 9a8f6043370997cb12414c4132eb68cc73f7030a..013314b2e716a6d939393b77b0edc87170dba27b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
@@ -286,32 +286,30 @@ static const struct dpu_dsc_cfg sm8650_dsc[] = {
{
.name = "dce_0_0", .id = DSC_0,
.base = 0x80000, .len = 0x6,
- .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+ .features = BIT(DPU_DSC_NATIVE_42x_EN),
.sblk = &dsc_sblk_0,
}, {
.name = "dce_0_1", .id = DSC_1,
.base = 0x80000, .len = 0x6,
- .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+ .features = BIT(DPU_DSC_NATIVE_42x_EN),
.sblk = &dsc_sblk_1,
}, {
.name = "dce_1_0", .id = DSC_2,
.base = 0x81000, .len = 0x6,
- .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+ .features = BIT(DPU_DSC_NATIVE_42x_EN),
.sblk = &dsc_sblk_0,
}, {
.name = "dce_1_1", .id = DSC_3,
.base = 0x81000, .len = 0x6,
- .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+ .features = BIT(DPU_DSC_NATIVE_42x_EN),
.sblk = &dsc_sblk_1,
}, {
.name = "dce_2_0", .id = DSC_4,
.base = 0x82000, .len = 0x6,
- .features = BIT(DPU_DSC_HW_REV_1_2),
.sblk = &dsc_sblk_0,
}, {
.name = "dce_2_1", .id = DSC_5,
.base = 0x82000, .len = 0x6,
- .features = BIT(DPU_DSC_HW_REV_1_2),
.sblk = &dsc_sblk_1,
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
index e81a2a02e0a6379382058fd89500cf2064a2193f..b4d41e2644349bdbdbdacbe1e9b3748f90df4f3b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
@@ -263,22 +263,20 @@ static const struct dpu_dsc_cfg sm8350_dsc[] = {
{
.name = "dce_0_0", .id = DSC_0,
.base = 0x80000, .len = 0x4,
- .features = BIT(DPU_DSC_HW_REV_1_2),
.sblk = &dsc_sblk_0,
}, {
.name = "dce_0_1", .id = DSC_1,
.base = 0x80000, .len = 0x4,
- .features = BIT(DPU_DSC_HW_REV_1_2),
.sblk = &dsc_sblk_1,
}, {
.name = "dce_1_0", .id = DSC_2,
.base = 0x81000, .len = 0x4,
- .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+ .features = BIT(DPU_DSC_NATIVE_42x_EN),
.sblk = &dsc_sblk_0,
}, {
.name = "dce_1_1", .id = DSC_3,
.base = 0x81000, .len = 0x4,
- .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+ .features = BIT(DPU_DSC_NATIVE_42x_EN),
.sblk = &dsc_sblk_1,
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
index b0e94ccf7f83e9c3c41f1df363cb6a8c24f1503d..5d88f0261d8320a78f8d64c9bb68b938f83160a0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
@@ -150,7 +150,7 @@ static const struct dpu_dsc_cfg sc7280_dsc[] = {
{
.name = "dce_0_0", .id = DSC_0,
.base = 0x80000, .len = 0x4,
- .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+ .features = BIT(DPU_DSC_NATIVE_42x_EN),
.sblk = &dsc_sblk_0,
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
index 2cf30234e45da8a7776d61c49c26abd75d070941..303d33dc7783ac91a496fa0a19860564ad0b6d5d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
@@ -262,32 +262,28 @@ static const struct dpu_dsc_cfg sc8280xp_dsc[] = {
{
.name = "dce_0_0", .id = DSC_0,
.base = 0x80000, .len = 0x4,
- .features = BIT(DPU_DSC_HW_REV_1_2),
.sblk = &dsc_sblk_0,
}, {
.name = "dce_0_1", .id = DSC_1,
.base = 0x80000, .len = 0x4,
- .features = BIT(DPU_DSC_HW_REV_1_2),
.sblk = &dsc_sblk_1,
}, {
.name = "dce_1_0", .id = DSC_2,
.base = 0x81000, .len = 0x4,
- .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+ .features = BIT(DPU_DSC_NATIVE_42x_EN),
.sblk = &dsc_sblk_0,
}, {
.name = "dce_1_1", .id = DSC_3,
.base = 0x81000, .len = 0x4,
- .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+ .features = BIT(DPU_DSC_NATIVE_42x_EN),
.sblk = &dsc_sblk_1,
}, {
.name = "dce_2_0", .id = DSC_4,
.base = 0x82000, .len = 0x4,
- .features = BIT(DPU_DSC_HW_REV_1_2),
.sblk = &dsc_sblk_0,
}, {
.name = "dce_2_1", .id = DSC_5,
.base = 0x82000, .len = 0x4,
- .features = BIT(DPU_DSC_HW_REV_1_2),
.sblk = &dsc_sblk_1,
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
index dcef56683224b5715c2608b5472d2d5a0da62010..3c0728a4b37ea6af25ab64315cfe63ba6f8d2774 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
@@ -276,22 +276,20 @@ static const struct dpu_dsc_cfg sm8450_dsc[] = {
{
.name = "dce_0_0", .id = DSC_0,
.base = 0x80000, .len = 0x4,
- .features = BIT(DPU_DSC_HW_REV_1_2),
.sblk = &dsc_sblk_0,
}, {
.name = "dce_0_1", .id = DSC_1,
.base = 0x80000, .len = 0x4,
- .features = BIT(DPU_DSC_HW_REV_1_2),
.sblk = &dsc_sblk_1,
}, {
.name = "dce_1_0", .id = DSC_2,
.base = 0x81000, .len = 0x4,
- .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+ .features = BIT(DPU_DSC_NATIVE_42x_EN),
.sblk = &dsc_sblk_0,
}, {
.name = "dce_1_1", .id = DSC_3,
.base = 0x81000, .len = 0x4,
- .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+ .features = BIT(DPU_DSC_NATIVE_42x_EN),
.sblk = &dsc_sblk_1,
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
index 5f5987d5fc602df29c5eb289823de5dd359df014..b8a1646395916fde04b9750cf548edca5729d9c2 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
@@ -275,32 +275,28 @@ static const struct dpu_dsc_cfg sa8775p_dsc[] = {
{
.name = "dce_0_0", .id = DSC_0,
.base = 0x80000, .len = 0x4,
- .features = BIT(DPU_DSC_HW_REV_1_2),
.sblk = &dsc_sblk_0,
}, {
.name = "dce_0_1", .id = DSC_1,
.base = 0x80000, .len = 0x4,
- .features = BIT(DPU_DSC_HW_REV_1_2),
.sblk = &dsc_sblk_1,
}, {
.name = "dce_1_0", .id = DSC_2,
.base = 0x81000, .len = 0x4,
- .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+ .features = BIT(DPU_DSC_NATIVE_42x_EN),
.sblk = &dsc_sblk_0,
}, {
.name = "dce_1_1", .id = DSC_3,
.base = 0x81000, .len = 0x4,
- .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+ .features = BIT(DPU_DSC_NATIVE_42x_EN),
.sblk = &dsc_sblk_1,
}, {
.name = "dce_2_0", .id = DSC_4,
.base = 0x82000, .len = 0x4,
- .features = BIT(DPU_DSC_HW_REV_1_2),
.sblk = &dsc_sblk_0,
}, {
.name = "dce_2_1", .id = DSC_5,
.base = 0x82000, .len = 0x4,
- .features = BIT(DPU_DSC_HW_REV_1_2),
.sblk = &dsc_sblk_1,
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
index 6f310216fbccb985308f617db20c1878e622340a..ef22a9adf43ddc9d15be5f1359ea5f6690e9f27c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
@@ -272,22 +272,20 @@ static const struct dpu_dsc_cfg sm8550_dsc[] = {
{
.name = "dce_0_0", .id = DSC_0,
.base = 0x80000, .len = 0x4,
- .features = BIT(DPU_DSC_HW_REV_1_2),
.sblk = &dsc_sblk_0,
}, {
.name = "dce_0_1", .id = DSC_1,
.base = 0x80000, .len = 0x4,
- .features = BIT(DPU_DSC_HW_REV_1_2),
.sblk = &dsc_sblk_1,
}, {
.name = "dce_1_0", .id = DSC_2,
.base = 0x81000, .len = 0x4,
- .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+ .features = BIT(DPU_DSC_NATIVE_42x_EN),
.sblk = &dsc_sblk_0,
}, {
.name = "dce_1_1", .id = DSC_3,
.base = 0x81000, .len = 0x4,
- .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+ .features = BIT(DPU_DSC_NATIVE_42x_EN),
.sblk = &dsc_sblk_1,
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
index ba8a2c5dc5e2b3474b295c86afbbbe8f8d416ccd..2e7d4403835353927bc85a5acd3e6c5967cac455 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
@@ -272,22 +272,20 @@ static const struct dpu_dsc_cfg sar2130p_dsc[] = {
{
.name = "dce_0_0", .id = DSC_0,
.base = 0x80000, .len = 0x4,
- .features = BIT(DPU_DSC_HW_REV_1_2),
.sblk = &dsc_sblk_0,
}, {
.name = "dce_0_1", .id = DSC_1,
.base = 0x80000, .len = 0x4,
- .features = BIT(DPU_DSC_HW_REV_1_2),
.sblk = &dsc_sblk_1,
}, {
.name = "dce_1_0", .id = DSC_2,
.base = 0x81000, .len = 0x4,
- .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+ .features = BIT(DPU_DSC_NATIVE_42x_EN),
.sblk = &dsc_sblk_0,
}, {
.name = "dce_1_1", .id = DSC_3,
.base = 0x81000, .len = 0x4,
- .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+ .features = BIT(DPU_DSC_NATIVE_42x_EN),
.sblk = &dsc_sblk_1,
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
index 77986a7bd62c1b6323482426e596e5974ba40865..ac95d46b3ecf2d95ec0d516a79567fe9c204b5f6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
@@ -272,22 +272,20 @@ static const struct dpu_dsc_cfg x1e80100_dsc[] = {
{
.name = "dce_0_0", .id = DSC_0,
.base = 0x80000, .len = 0x4,
- .features = BIT(DPU_DSC_HW_REV_1_2),
.sblk = &dsc_sblk_0,
}, {
.name = "dce_0_1", .id = DSC_1,
.base = 0x80000, .len = 0x4,
- .features = BIT(DPU_DSC_HW_REV_1_2),
.sblk = &dsc_sblk_1,
}, {
.name = "dce_1_0", .id = DSC_2,
.base = 0x81000, .len = 0x4,
- .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+ .features = BIT(DPU_DSC_NATIVE_42x_EN),
.sblk = &dsc_sblk_0,
}, {
.name = "dce_1_1", .id = DSC_3,
.base = 0x81000, .len = 0x4,
- .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
+ .features = BIT(DPU_DSC_NATIVE_42x_EN),
.sblk = &dsc_sblk_1,
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index cc17b20a7d4c15b0cd9c5dc8b9a4b78d4cb78315..01430ff90ab0988bdaa91b85458dd649aab543b3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -176,13 +176,11 @@ enum {
* DSC sub-blocks/features
* @DPU_DSC_OUTPUT_CTRL Configure which PINGPONG block gets
* the pixel output from this DSC.
- * @DPU_DSC_HW_REV_1_2 DSC block supports DSC 1.1 and 1.2
* @DPU_DSC_NATIVE_42x_EN Supports NATIVE_422_EN and NATIVE_420_EN encoding
* @DPU_DSC_MAX
*/
enum {
DPU_DSC_OUTPUT_CTRL = 0x1,
- DPU_DSC_HW_REV_1_2,
DPU_DSC_NATIVE_42x_EN,
DPU_DSC_MAX
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 80ffd46cbfe69fc90afcdc1a144fc5de7bb6af42..d478a7bce7568ab000d73467bcad91e29f049abc 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1043,7 +1043,7 @@ static void dpu_kms_mdp_snapshot(struct msm_disp_state *disp_state, struct msm_k
msm_disp_snapshot_add_block(disp_state, cat->dsc[i].len, base,
"%s", cat->dsc[i].name);
- if (cat->dsc[i].features & BIT(DPU_DSC_HW_REV_1_2)) {
+ if (cat->mdss_ver->core_major_ver >= 7) {
struct dpu_dsc_blk enc = cat->dsc[i].sblk->enc;
struct dpu_dsc_blk ctl = cat->dsc[i].sblk->ctl;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index 7bcb1e057b143a5512aafbd640199c8f3b436527..c2a659512cb747e1dd5ed9e28534286ff8d67f4f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -168,7 +168,7 @@ int dpu_rm_init(struct drm_device *dev,
struct dpu_hw_dsc *hw;
const struct dpu_dsc_cfg *dsc = &cat->dsc[i];
- if (test_bit(DPU_DSC_HW_REV_1_2, &dsc->features))
+ if (cat->mdss_ver->core_major_ver >= 7)
hw = dpu_hw_dsc_init_1_2(dev, dsc, mmio);
else
hw = dpu_hw_dsc_init(dev, dsc, mmio);
--
2.39.5
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH v4 23/30] drm/msm/dpu: get rid of DPU_DSC_HW_REV_1_2
2025-05-19 16:04 ` [PATCH v4 23/30] drm/msm/dpu: get rid of DPU_DSC_HW_REV_1_2 Dmitry Baryshkov
@ 2025-05-20 8:03 ` neil.armstrong
0 siblings, 0 replies; 64+ messages in thread
From: neil.armstrong @ 2025-05-20 8:03 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Abhinav Kumar, Sean Paul,
Marijn Suijten, David Airlie, Simona Vetter, Vinod Koul,
Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel,
Dmitry Baryshkov
On 19/05/2025 18:04, Dmitry Baryshkov wrote:
> From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>
> Continue migration to the MDSS-revision based checks and replace
> DPU_DSC_HW_REV_1_2 feature bit with the core_major_ver >= 7 check.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 10 ++++------
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 6 ++----
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 8 ++------
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 6 ++----
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 8 ++------
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 6 ++----
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h | 6 ++----
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 6 ++----
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 --
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 2 +-
> 12 files changed, 21 insertions(+), 43 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
> index 9a8f6043370997cb12414c4132eb68cc73f7030a..013314b2e716a6d939393b77b0edc87170dba27b 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
> @@ -286,32 +286,30 @@ static const struct dpu_dsc_cfg sm8650_dsc[] = {
> {
> .name = "dce_0_0", .id = DSC_0,
> .base = 0x80000, .len = 0x6,
> - .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
> + .features = BIT(DPU_DSC_NATIVE_42x_EN),
> .sblk = &dsc_sblk_0,
> }, {
> .name = "dce_0_1", .id = DSC_1,
> .base = 0x80000, .len = 0x6,
> - .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
> + .features = BIT(DPU_DSC_NATIVE_42x_EN),
> .sblk = &dsc_sblk_1,
> }, {
> .name = "dce_1_0", .id = DSC_2,
> .base = 0x81000, .len = 0x6,
> - .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
> + .features = BIT(DPU_DSC_NATIVE_42x_EN),
> .sblk = &dsc_sblk_0,
> }, {
> .name = "dce_1_1", .id = DSC_3,
> .base = 0x81000, .len = 0x6,
> - .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
> + .features = BIT(DPU_DSC_NATIVE_42x_EN),
> .sblk = &dsc_sblk_1,
> }, {
> .name = "dce_2_0", .id = DSC_4,
> .base = 0x82000, .len = 0x6,
> - .features = BIT(DPU_DSC_HW_REV_1_2),
> .sblk = &dsc_sblk_0,
> }, {
> .name = "dce_2_1", .id = DSC_5,
> .base = 0x82000, .len = 0x6,
> - .features = BIT(DPU_DSC_HW_REV_1_2),
> .sblk = &dsc_sblk_1,
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> index e81a2a02e0a6379382058fd89500cf2064a2193f..b4d41e2644349bdbdbdacbe1e9b3748f90df4f3b 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> @@ -263,22 +263,20 @@ static const struct dpu_dsc_cfg sm8350_dsc[] = {
> {
> .name = "dce_0_0", .id = DSC_0,
> .base = 0x80000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2),
> .sblk = &dsc_sblk_0,
> }, {
> .name = "dce_0_1", .id = DSC_1,
> .base = 0x80000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2),
> .sblk = &dsc_sblk_1,
> }, {
> .name = "dce_1_0", .id = DSC_2,
> .base = 0x81000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
> + .features = BIT(DPU_DSC_NATIVE_42x_EN),
> .sblk = &dsc_sblk_0,
> }, {
> .name = "dce_1_1", .id = DSC_3,
> .base = 0x81000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
> + .features = BIT(DPU_DSC_NATIVE_42x_EN),
> .sblk = &dsc_sblk_1,
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> index b0e94ccf7f83e9c3c41f1df363cb6a8c24f1503d..5d88f0261d8320a78f8d64c9bb68b938f83160a0 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> @@ -150,7 +150,7 @@ static const struct dpu_dsc_cfg sc7280_dsc[] = {
> {
> .name = "dce_0_0", .id = DSC_0,
> .base = 0x80000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
> + .features = BIT(DPU_DSC_NATIVE_42x_EN),
> .sblk = &dsc_sblk_0,
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> index 2cf30234e45da8a7776d61c49c26abd75d070941..303d33dc7783ac91a496fa0a19860564ad0b6d5d 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> @@ -262,32 +262,28 @@ static const struct dpu_dsc_cfg sc8280xp_dsc[] = {
> {
> .name = "dce_0_0", .id = DSC_0,
> .base = 0x80000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2),
> .sblk = &dsc_sblk_0,
> }, {
> .name = "dce_0_1", .id = DSC_1,
> .base = 0x80000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2),
> .sblk = &dsc_sblk_1,
> }, {
> .name = "dce_1_0", .id = DSC_2,
> .base = 0x81000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
> + .features = BIT(DPU_DSC_NATIVE_42x_EN),
> .sblk = &dsc_sblk_0,
> }, {
> .name = "dce_1_1", .id = DSC_3,
> .base = 0x81000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
> + .features = BIT(DPU_DSC_NATIVE_42x_EN),
> .sblk = &dsc_sblk_1,
> }, {
> .name = "dce_2_0", .id = DSC_4,
> .base = 0x82000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2),
> .sblk = &dsc_sblk_0,
> }, {
> .name = "dce_2_1", .id = DSC_5,
> .base = 0x82000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2),
> .sblk = &dsc_sblk_1,
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> index dcef56683224b5715c2608b5472d2d5a0da62010..3c0728a4b37ea6af25ab64315cfe63ba6f8d2774 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> @@ -276,22 +276,20 @@ static const struct dpu_dsc_cfg sm8450_dsc[] = {
> {
> .name = "dce_0_0", .id = DSC_0,
> .base = 0x80000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2),
> .sblk = &dsc_sblk_0,
> }, {
> .name = "dce_0_1", .id = DSC_1,
> .base = 0x80000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2),
> .sblk = &dsc_sblk_1,
> }, {
> .name = "dce_1_0", .id = DSC_2,
> .base = 0x81000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
> + .features = BIT(DPU_DSC_NATIVE_42x_EN),
> .sblk = &dsc_sblk_0,
> }, {
> .name = "dce_1_1", .id = DSC_3,
> .base = 0x81000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
> + .features = BIT(DPU_DSC_NATIVE_42x_EN),
> .sblk = &dsc_sblk_1,
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
> index 5f5987d5fc602df29c5eb289823de5dd359df014..b8a1646395916fde04b9750cf548edca5729d9c2 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
> @@ -275,32 +275,28 @@ static const struct dpu_dsc_cfg sa8775p_dsc[] = {
> {
> .name = "dce_0_0", .id = DSC_0,
> .base = 0x80000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2),
> .sblk = &dsc_sblk_0,
> }, {
> .name = "dce_0_1", .id = DSC_1,
> .base = 0x80000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2),
> .sblk = &dsc_sblk_1,
> }, {
> .name = "dce_1_0", .id = DSC_2,
> .base = 0x81000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
> + .features = BIT(DPU_DSC_NATIVE_42x_EN),
> .sblk = &dsc_sblk_0,
> }, {
> .name = "dce_1_1", .id = DSC_3,
> .base = 0x81000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
> + .features = BIT(DPU_DSC_NATIVE_42x_EN),
> .sblk = &dsc_sblk_1,
> }, {
> .name = "dce_2_0", .id = DSC_4,
> .base = 0x82000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2),
> .sblk = &dsc_sblk_0,
> }, {
> .name = "dce_2_1", .id = DSC_5,
> .base = 0x82000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2),
> .sblk = &dsc_sblk_1,
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> index 6f310216fbccb985308f617db20c1878e622340a..ef22a9adf43ddc9d15be5f1359ea5f6690e9f27c 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> @@ -272,22 +272,20 @@ static const struct dpu_dsc_cfg sm8550_dsc[] = {
> {
> .name = "dce_0_0", .id = DSC_0,
> .base = 0x80000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2),
> .sblk = &dsc_sblk_0,
> }, {
> .name = "dce_0_1", .id = DSC_1,
> .base = 0x80000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2),
> .sblk = &dsc_sblk_1,
> }, {
> .name = "dce_1_0", .id = DSC_2,
> .base = 0x81000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
> + .features = BIT(DPU_DSC_NATIVE_42x_EN),
> .sblk = &dsc_sblk_0,
> }, {
> .name = "dce_1_1", .id = DSC_3,
> .base = 0x81000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
> + .features = BIT(DPU_DSC_NATIVE_42x_EN),
> .sblk = &dsc_sblk_1,
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
> index ba8a2c5dc5e2b3474b295c86afbbbe8f8d416ccd..2e7d4403835353927bc85a5acd3e6c5967cac455 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
> @@ -272,22 +272,20 @@ static const struct dpu_dsc_cfg sar2130p_dsc[] = {
> {
> .name = "dce_0_0", .id = DSC_0,
> .base = 0x80000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2),
> .sblk = &dsc_sblk_0,
> }, {
> .name = "dce_0_1", .id = DSC_1,
> .base = 0x80000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2),
> .sblk = &dsc_sblk_1,
> }, {
> .name = "dce_1_0", .id = DSC_2,
> .base = 0x81000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
> + .features = BIT(DPU_DSC_NATIVE_42x_EN),
> .sblk = &dsc_sblk_0,
> }, {
> .name = "dce_1_1", .id = DSC_3,
> .base = 0x81000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
> + .features = BIT(DPU_DSC_NATIVE_42x_EN),
> .sblk = &dsc_sblk_1,
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
> index 77986a7bd62c1b6323482426e596e5974ba40865..ac95d46b3ecf2d95ec0d516a79567fe9c204b5f6 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
> @@ -272,22 +272,20 @@ static const struct dpu_dsc_cfg x1e80100_dsc[] = {
> {
> .name = "dce_0_0", .id = DSC_0,
> .base = 0x80000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2),
> .sblk = &dsc_sblk_0,
> }, {
> .name = "dce_0_1", .id = DSC_1,
> .base = 0x80000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2),
> .sblk = &dsc_sblk_1,
> }, {
> .name = "dce_1_0", .id = DSC_2,
> .base = 0x81000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
> + .features = BIT(DPU_DSC_NATIVE_42x_EN),
> .sblk = &dsc_sblk_0,
> }, {
> .name = "dce_1_1", .id = DSC_3,
> .base = 0x81000, .len = 0x4,
> - .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
> + .features = BIT(DPU_DSC_NATIVE_42x_EN),
> .sblk = &dsc_sblk_1,
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index cc17b20a7d4c15b0cd9c5dc8b9a4b78d4cb78315..01430ff90ab0988bdaa91b85458dd649aab543b3 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -176,13 +176,11 @@ enum {
> * DSC sub-blocks/features
> * @DPU_DSC_OUTPUT_CTRL Configure which PINGPONG block gets
> * the pixel output from this DSC.
> - * @DPU_DSC_HW_REV_1_2 DSC block supports DSC 1.1 and 1.2
> * @DPU_DSC_NATIVE_42x_EN Supports NATIVE_422_EN and NATIVE_420_EN encoding
> * @DPU_DSC_MAX
> */
> enum {
> DPU_DSC_OUTPUT_CTRL = 0x1,
> - DPU_DSC_HW_REV_1_2,
> DPU_DSC_NATIVE_42x_EN,
> DPU_DSC_MAX
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> index 80ffd46cbfe69fc90afcdc1a144fc5de7bb6af42..d478a7bce7568ab000d73467bcad91e29f049abc 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> @@ -1043,7 +1043,7 @@ static void dpu_kms_mdp_snapshot(struct msm_disp_state *disp_state, struct msm_k
> msm_disp_snapshot_add_block(disp_state, cat->dsc[i].len, base,
> "%s", cat->dsc[i].name);
>
> - if (cat->dsc[i].features & BIT(DPU_DSC_HW_REV_1_2)) {
> + if (cat->mdss_ver->core_major_ver >= 7) {
> struct dpu_dsc_blk enc = cat->dsc[i].sblk->enc;
> struct dpu_dsc_blk ctl = cat->dsc[i].sblk->ctl;
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> index 7bcb1e057b143a5512aafbd640199c8f3b436527..c2a659512cb747e1dd5ed9e28534286ff8d67f4f 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> @@ -168,7 +168,7 @@ int dpu_rm_init(struct drm_device *dev,
> struct dpu_hw_dsc *hw;
> const struct dpu_dsc_cfg *dsc = &cat->dsc[i];
>
> - if (test_bit(DPU_DSC_HW_REV_1_2, &dsc->features))
> + if (cat->mdss_ver->core_major_ver >= 7)
> hw = dpu_hw_dsc_init_1_2(dev, dsc, mmio);
> else
> hw = dpu_hw_dsc_init(dev, dsc, mmio);
>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH v4 24/30] drm/msm/dpu: get rid of DPU_DSC_OUTPUT_CTRL
2025-05-19 16:04 [PATCH v4 00/30] drm/msm/dpu: rework HW block feature handling Dmitry Baryshkov
` (22 preceding siblings ...)
2025-05-19 16:04 ` [PATCH v4 23/30] drm/msm/dpu: get rid of DPU_DSC_HW_REV_1_2 Dmitry Baryshkov
@ 2025-05-19 16:04 ` Dmitry Baryshkov
2025-05-20 8:04 ` neil.armstrong
2025-05-19 16:04 ` [PATCH v4 25/30] drm/msm/dpu: get rid of DPU_WB_INPUT_CTRL Dmitry Baryshkov
` (5 subsequent siblings)
29 siblings, 1 reply; 64+ messages in thread
From: Dmitry Baryshkov @ 2025-05-19 16:04 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Sean Paul, Marijn Suijten, David Airlie,
Simona Vetter, Vinod Koul, Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel,
Dmitry Baryshkov
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Continue migration to the MDSS-revision based checks and replace
DPU_DSC_OUTPUT_CTRL feature bit with the core_major_ver >= 5 check.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 4 ----
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 6 ------
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h | 2 --
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 4 ----
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 5 +----
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 6 ++++--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h | 3 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 2 +-
10 files changed, 8 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
index 8e37c40620b62aacdcb47c7a04bcfce944ab0b4c..5d3b864d28a86fb86fc4576210c9418604afd844 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
@@ -259,19 +259,15 @@ static const struct dpu_dsc_cfg sm8150_dsc[] = {
{
.name = "dsc_0", .id = DSC_0,
.base = 0x80000, .len = 0x140,
- .features = BIT(DPU_DSC_OUTPUT_CTRL),
}, {
.name = "dsc_1", .id = DSC_1,
.base = 0x80400, .len = 0x140,
- .features = BIT(DPU_DSC_OUTPUT_CTRL),
}, {
.name = "dsc_2", .id = DSC_2,
.base = 0x80800, .len = 0x140,
- .features = BIT(DPU_DSC_OUTPUT_CTRL),
}, {
.name = "dsc_3", .id = DSC_3,
.base = 0x80c00, .len = 0x140,
- .features = BIT(DPU_DSC_OUTPUT_CTRL),
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
index a05d2ef8fc9d217898b8c12d4639563b28b4477b..a6e9dfc583f283d752545b3f700c3d509e2a2965 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
@@ -259,27 +259,21 @@ static const struct dpu_dsc_cfg sc8180x_dsc[] = {
{
.name = "dsc_0", .id = DSC_0,
.base = 0x80000, .len = 0x140,
- .features = BIT(DPU_DSC_OUTPUT_CTRL),
}, {
.name = "dsc_1", .id = DSC_1,
.base = 0x80400, .len = 0x140,
- .features = BIT(DPU_DSC_OUTPUT_CTRL),
}, {
.name = "dsc_2", .id = DSC_2,
.base = 0x80800, .len = 0x140,
- .features = BIT(DPU_DSC_OUTPUT_CTRL),
}, {
.name = "dsc_3", .id = DSC_3,
.base = 0x80c00, .len = 0x140,
- .features = BIT(DPU_DSC_OUTPUT_CTRL),
}, {
.name = "dsc_4", .id = DSC_4,
.base = 0x81000, .len = 0x140,
- .features = BIT(DPU_DSC_OUTPUT_CTRL),
}, {
.name = "dsc_5", .id = DSC_5,
.base = 0x81400, .len = 0x140,
- .features = BIT(DPU_DSC_OUTPUT_CTRL),
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
index cb0b5687b5239418f50c539447f9cfa56e81fcc6..fe9c9301e3d9d2d3a0a34ab9aed0f307d08c34ca 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
@@ -193,11 +193,9 @@ static const struct dpu_dsc_cfg sm7150_dsc[] = {
{
.name = "dsc_0", .id = DSC_0,
.base = 0x80000, .len = 0x140,
- .features = BIT(DPU_DSC_OUTPUT_CTRL),
}, {
.name = "dsc_1", .id = DSC_1,
.base = 0x80400, .len = 0x140,
- .features = BIT(DPU_DSC_OUTPUT_CTRL),
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
index 17fa0ef9ac03e4649a218cd837b296211ef4506c..9ceff398fd6f554085440f509b6f8398b4fbf304 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
@@ -258,19 +258,15 @@ static const struct dpu_dsc_cfg sm8250_dsc[] = {
{
.name = "dsc_0", .id = DSC_0,
.base = 0x80000, .len = 0x140,
- .features = BIT(DPU_DSC_OUTPUT_CTRL),
}, {
.name = "dsc_1", .id = DSC_1,
.base = 0x80400, .len = 0x140,
- .features = BIT(DPU_DSC_OUTPUT_CTRL),
}, {
.name = "dsc_2", .id = DSC_2,
.base = 0x80800, .len = 0x140,
- .features = BIT(DPU_DSC_OUTPUT_CTRL),
}, {
.name = "dsc_3", .id = DSC_3,
.base = 0x80c00, .len = 0x140,
- .features = BIT(DPU_DSC_OUTPUT_CTRL),
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
index 06bcaf4d8b0db74c349112af6884f7f3139a7ff8..a46e9e3ff565ba5ef233af76f1c6cebb1d0c318a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
@@ -135,7 +135,6 @@ static const struct dpu_dsc_cfg sm6350_dsc[] = {
{
.name = "dsc_0", .id = DSC_0,
.base = 0x80000, .len = 0x140,
- .features = BIT(DPU_DSC_OUTPUT_CTRL),
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
index 9c4e8450b67760c880d9bd2528c6a954a0282e08..98190ee7ec7aca6835376b030379a5a3d8b0859b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
@@ -87,7 +87,6 @@ static const struct dpu_dsc_cfg sm6375_dsc[] = {
{
.name = "dsc_0", .id = DSC_0,
.base = 0x80000, .len = 0x140,
- .features = BIT(DPU_DSC_OUTPUT_CTRL),
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 01430ff90ab0988bdaa91b85458dd649aab543b3..41906dadff5a8ef39b2e90f3e80bb699a5cf59b7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -174,14 +174,11 @@ enum {
/**
* DSC sub-blocks/features
- * @DPU_DSC_OUTPUT_CTRL Configure which PINGPONG block gets
- * the pixel output from this DSC.
* @DPU_DSC_NATIVE_42x_EN Supports NATIVE_422_EN and NATIVE_420_EN encoding
* @DPU_DSC_MAX
*/
enum {
- DPU_DSC_OUTPUT_CTRL = 0x1,
- DPU_DSC_NATIVE_42x_EN,
+ DPU_DSC_NATIVE_42x_EN = 0x1,
DPU_DSC_MAX
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
index c7db917afd27e3daf1e8aad2ad671246bf6c8fbf..3a149caa7ff4f20dc7a902033cf29a168268839e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
@@ -186,11 +186,13 @@ static void dpu_hw_dsc_bind_pingpong_blk(
* @dev: Corresponding device for devres management
* @cfg: DSC catalog entry for which driver object is required
* @addr: Mapped register io address of MDP
+ * @mdss_ver: dpu core's major and minor versions
* Return: Error code or allocated dpu_hw_dsc context
*/
struct dpu_hw_dsc *dpu_hw_dsc_init(struct drm_device *dev,
const struct dpu_dsc_cfg *cfg,
- void __iomem *addr)
+ void __iomem *addr,
+ const struct dpu_mdss_version *mdss_ver)
{
struct dpu_hw_dsc *c;
@@ -207,7 +209,7 @@ struct dpu_hw_dsc *dpu_hw_dsc_init(struct drm_device *dev,
c->ops.dsc_disable = dpu_hw_dsc_disable;
c->ops.dsc_config = dpu_hw_dsc_config;
c->ops.dsc_config_thresh = dpu_hw_dsc_config_thresh;
- if (c->caps->features & BIT(DPU_DSC_OUTPUT_CTRL))
+ if (mdss_ver->core_major_ver >= 5)
c->ops.dsc_bind_pingpong_blk = dpu_hw_dsc_bind_pingpong_blk;
return c;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h
index fc171bdeca488f6287cf2ba7362ed330ad55b28f..b7013c9822d23238eb5411a5e284bb072ecc3395 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h
@@ -64,7 +64,8 @@ struct dpu_hw_dsc {
struct dpu_hw_dsc *dpu_hw_dsc_init(struct drm_device *dev,
const struct dpu_dsc_cfg *cfg,
- void __iomem *addr);
+ void __iomem *addr,
+ const struct dpu_mdss_version *mdss_ver);
struct dpu_hw_dsc *dpu_hw_dsc_init_1_2(struct drm_device *dev,
const struct dpu_dsc_cfg *cfg,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index c2a659512cb747e1dd5ed9e28534286ff8d67f4f..a2219c4f55a45db894ff18c1fd0a810c1a3cf811 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -171,7 +171,7 @@ int dpu_rm_init(struct drm_device *dev,
if (cat->mdss_ver->core_major_ver >= 7)
hw = dpu_hw_dsc_init_1_2(dev, dsc, mmio);
else
- hw = dpu_hw_dsc_init(dev, dsc, mmio);
+ hw = dpu_hw_dsc_init(dev, dsc, mmio, cat->mdss_ver);
if (IS_ERR(hw)) {
rc = PTR_ERR(hw);
--
2.39.5
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH v4 24/30] drm/msm/dpu: get rid of DPU_DSC_OUTPUT_CTRL
2025-05-19 16:04 ` [PATCH v4 24/30] drm/msm/dpu: get rid of DPU_DSC_OUTPUT_CTRL Dmitry Baryshkov
@ 2025-05-20 8:04 ` neil.armstrong
0 siblings, 0 replies; 64+ messages in thread
From: neil.armstrong @ 2025-05-20 8:04 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Abhinav Kumar, Sean Paul,
Marijn Suijten, David Airlie, Simona Vetter, Vinod Koul,
Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel,
Dmitry Baryshkov
On 19/05/2025 18:04, Dmitry Baryshkov wrote:
> From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>
> Continue migration to the MDSS-revision based checks and replace
> DPU_DSC_OUTPUT_CTRL feature bit with the core_major_ver >= 5 check.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 4 ----
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 6 ------
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h | 2 --
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 4 ----
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 1 -
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 1 -
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 5 +----
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 6 ++++--
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h | 3 ++-
> drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 2 +-
> 10 files changed, 8 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> index 8e37c40620b62aacdcb47c7a04bcfce944ab0b4c..5d3b864d28a86fb86fc4576210c9418604afd844 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> @@ -259,19 +259,15 @@ static const struct dpu_dsc_cfg sm8150_dsc[] = {
> {
> .name = "dsc_0", .id = DSC_0,
> .base = 0x80000, .len = 0x140,
> - .features = BIT(DPU_DSC_OUTPUT_CTRL),
> }, {
> .name = "dsc_1", .id = DSC_1,
> .base = 0x80400, .len = 0x140,
> - .features = BIT(DPU_DSC_OUTPUT_CTRL),
> }, {
> .name = "dsc_2", .id = DSC_2,
> .base = 0x80800, .len = 0x140,
> - .features = BIT(DPU_DSC_OUTPUT_CTRL),
> }, {
> .name = "dsc_3", .id = DSC_3,
> .base = 0x80c00, .len = 0x140,
> - .features = BIT(DPU_DSC_OUTPUT_CTRL),
> },
> };
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> index a05d2ef8fc9d217898b8c12d4639563b28b4477b..a6e9dfc583f283d752545b3f700c3d509e2a2965 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> @@ -259,27 +259,21 @@ static const struct dpu_dsc_cfg sc8180x_dsc[] = {
> {
> .name = "dsc_0", .id = DSC_0,
> .base = 0x80000, .len = 0x140,
> - .features = BIT(DPU_DSC_OUTPUT_CTRL),
> }, {
> .name = "dsc_1", .id = DSC_1,
> .base = 0x80400, .len = 0x140,
> - .features = BIT(DPU_DSC_OUTPUT_CTRL),
> }, {
> .name = "dsc_2", .id = DSC_2,
> .base = 0x80800, .len = 0x140,
> - .features = BIT(DPU_DSC_OUTPUT_CTRL),
> }, {
> .name = "dsc_3", .id = DSC_3,
> .base = 0x80c00, .len = 0x140,
> - .features = BIT(DPU_DSC_OUTPUT_CTRL),
> }, {
> .name = "dsc_4", .id = DSC_4,
> .base = 0x81000, .len = 0x140,
> - .features = BIT(DPU_DSC_OUTPUT_CTRL),
> }, {
> .name = "dsc_5", .id = DSC_5,
> .base = 0x81400, .len = 0x140,
> - .features = BIT(DPU_DSC_OUTPUT_CTRL),
> },
> };
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
> index cb0b5687b5239418f50c539447f9cfa56e81fcc6..fe9c9301e3d9d2d3a0a34ab9aed0f307d08c34ca 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
> @@ -193,11 +193,9 @@ static const struct dpu_dsc_cfg sm7150_dsc[] = {
> {
> .name = "dsc_0", .id = DSC_0,
> .base = 0x80000, .len = 0x140,
> - .features = BIT(DPU_DSC_OUTPUT_CTRL),
> }, {
> .name = "dsc_1", .id = DSC_1,
> .base = 0x80400, .len = 0x140,
> - .features = BIT(DPU_DSC_OUTPUT_CTRL),
> },
> };
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> index 17fa0ef9ac03e4649a218cd837b296211ef4506c..9ceff398fd6f554085440f509b6f8398b4fbf304 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> @@ -258,19 +258,15 @@ static const struct dpu_dsc_cfg sm8250_dsc[] = {
> {
> .name = "dsc_0", .id = DSC_0,
> .base = 0x80000, .len = 0x140,
> - .features = BIT(DPU_DSC_OUTPUT_CTRL),
> }, {
> .name = "dsc_1", .id = DSC_1,
> .base = 0x80400, .len = 0x140,
> - .features = BIT(DPU_DSC_OUTPUT_CTRL),
> }, {
> .name = "dsc_2", .id = DSC_2,
> .base = 0x80800, .len = 0x140,
> - .features = BIT(DPU_DSC_OUTPUT_CTRL),
> }, {
> .name = "dsc_3", .id = DSC_3,
> .base = 0x80c00, .len = 0x140,
> - .features = BIT(DPU_DSC_OUTPUT_CTRL),
> },
> };
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> index 06bcaf4d8b0db74c349112af6884f7f3139a7ff8..a46e9e3ff565ba5ef233af76f1c6cebb1d0c318a 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> @@ -135,7 +135,6 @@ static const struct dpu_dsc_cfg sm6350_dsc[] = {
> {
> .name = "dsc_0", .id = DSC_0,
> .base = 0x80000, .len = 0x140,
> - .features = BIT(DPU_DSC_OUTPUT_CTRL),
> },
> };
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
> index 9c4e8450b67760c880d9bd2528c6a954a0282e08..98190ee7ec7aca6835376b030379a5a3d8b0859b 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
> @@ -87,7 +87,6 @@ static const struct dpu_dsc_cfg sm6375_dsc[] = {
> {
> .name = "dsc_0", .id = DSC_0,
> .base = 0x80000, .len = 0x140,
> - .features = BIT(DPU_DSC_OUTPUT_CTRL),
> },
> };
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index 01430ff90ab0988bdaa91b85458dd649aab543b3..41906dadff5a8ef39b2e90f3e80bb699a5cf59b7 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -174,14 +174,11 @@ enum {
>
> /**
> * DSC sub-blocks/features
> - * @DPU_DSC_OUTPUT_CTRL Configure which PINGPONG block gets
> - * the pixel output from this DSC.
> * @DPU_DSC_NATIVE_42x_EN Supports NATIVE_422_EN and NATIVE_420_EN encoding
> * @DPU_DSC_MAX
> */
> enum {
> - DPU_DSC_OUTPUT_CTRL = 0x1,
> - DPU_DSC_NATIVE_42x_EN,
> + DPU_DSC_NATIVE_42x_EN = 0x1,
> DPU_DSC_MAX
> };
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
> index c7db917afd27e3daf1e8aad2ad671246bf6c8fbf..3a149caa7ff4f20dc7a902033cf29a168268839e 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
> @@ -186,11 +186,13 @@ static void dpu_hw_dsc_bind_pingpong_blk(
> * @dev: Corresponding device for devres management
> * @cfg: DSC catalog entry for which driver object is required
> * @addr: Mapped register io address of MDP
> + * @mdss_ver: dpu core's major and minor versions
> * Return: Error code or allocated dpu_hw_dsc context
> */
> struct dpu_hw_dsc *dpu_hw_dsc_init(struct drm_device *dev,
> const struct dpu_dsc_cfg *cfg,
> - void __iomem *addr)
> + void __iomem *addr,
> + const struct dpu_mdss_version *mdss_ver)
> {
> struct dpu_hw_dsc *c;
>
> @@ -207,7 +209,7 @@ struct dpu_hw_dsc *dpu_hw_dsc_init(struct drm_device *dev,
> c->ops.dsc_disable = dpu_hw_dsc_disable;
> c->ops.dsc_config = dpu_hw_dsc_config;
> c->ops.dsc_config_thresh = dpu_hw_dsc_config_thresh;
> - if (c->caps->features & BIT(DPU_DSC_OUTPUT_CTRL))
> + if (mdss_ver->core_major_ver >= 5)
> c->ops.dsc_bind_pingpong_blk = dpu_hw_dsc_bind_pingpong_blk;
>
> return c;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h
> index fc171bdeca488f6287cf2ba7362ed330ad55b28f..b7013c9822d23238eb5411a5e284bb072ecc3395 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h
> @@ -64,7 +64,8 @@ struct dpu_hw_dsc {
>
> struct dpu_hw_dsc *dpu_hw_dsc_init(struct drm_device *dev,
> const struct dpu_dsc_cfg *cfg,
> - void __iomem *addr);
> + void __iomem *addr,
> + const struct dpu_mdss_version *mdss_ver);
>
> struct dpu_hw_dsc *dpu_hw_dsc_init_1_2(struct drm_device *dev,
> const struct dpu_dsc_cfg *cfg,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> index c2a659512cb747e1dd5ed9e28534286ff8d67f4f..a2219c4f55a45db894ff18c1fd0a810c1a3cf811 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> @@ -171,7 +171,7 @@ int dpu_rm_init(struct drm_device *dev,
> if (cat->mdss_ver->core_major_ver >= 7)
> hw = dpu_hw_dsc_init_1_2(dev, dsc, mmio);
> else
> - hw = dpu_hw_dsc_init(dev, dsc, mmio);
> + hw = dpu_hw_dsc_init(dev, dsc, mmio, cat->mdss_ver);
>
> if (IS_ERR(hw)) {
> rc = PTR_ERR(hw);
>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH v4 25/30] drm/msm/dpu: get rid of DPU_WB_INPUT_CTRL
2025-05-19 16:04 [PATCH v4 00/30] drm/msm/dpu: rework HW block feature handling Dmitry Baryshkov
` (23 preceding siblings ...)
2025-05-19 16:04 ` [PATCH v4 24/30] drm/msm/dpu: get rid of DPU_DSC_OUTPUT_CTRL Dmitry Baryshkov
@ 2025-05-19 16:04 ` Dmitry Baryshkov
2025-05-20 8:04 ` neil.armstrong
2025-05-19 16:04 ` [PATCH v4 26/30] drm/msm/dpu: get rid of DPU_SSPP_QOS_8LVL Dmitry Baryshkov
` (4 subsequent siblings)
29 siblings, 1 reply; 64+ messages in thread
From: Dmitry Baryshkov @ 2025-05-19 16:04 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Sean Paul, Marijn Suijten, David Airlie,
Simona Vetter, Vinod Koul, Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel,
Dmitry Baryshkov
Continue migration to the MDSS-revision based checks and replace
DPU_WB_INPUT_CTRL feature bit with the core_major_ver >= 5 check.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 ---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 3 ---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 2 +-
19 files changed, 17 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
index 013314b2e716a6d939393b77b0edc87170dba27b..56d3c38c87781edb438b277c77382848b679198f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
@@ -318,7 +318,7 @@ static const struct dpu_wb_cfg sm8650_wb[] = {
{
.name = "wb_2", .id = WB_2,
.base = 0x65000, .len = 0x2c8,
- .features = WB_SM8250_MASK,
+ .features = WB_SDM845_MASK,
.format_list = wb2_formats_rgb_yuv,
.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
.xin_id = 6,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
index 5d3b864d28a86fb86fc4576210c9418604afd844..ae1b2ed96e9f10a6e7a710fc8bb4e40dec665cf9 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
@@ -275,7 +275,7 @@ static const struct dpu_wb_cfg sm8150_wb[] = {
{
.name = "wb_2", .id = WB_2,
.base = 0x65000, .len = 0x2c8,
- .features = WB_SM8250_MASK,
+ .features = WB_SDM845_MASK,
.format_list = wb2_formats_rgb_yuv,
.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
.clk_ctrl = DPU_CLK_CTRL_WB2,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
index a6e9dfc583f283d752545b3f700c3d509e2a2965..fc80406759cd52f0d633927c8ba876feaff48e07 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
@@ -281,7 +281,7 @@ static const struct dpu_wb_cfg sc8180x_wb[] = {
{
.name = "wb_2", .id = WB_2,
.base = 0x65000, .len = 0x2c8,
- .features = WB_SM8250_MASK,
+ .features = WB_SDM845_MASK,
.format_list = wb2_formats_rgb_yuv,
.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
.clk_ctrl = DPU_CLK_CTRL_WB2,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
index fe9c9301e3d9d2d3a0a34ab9aed0f307d08c34ca..a56c288ac10cd3dfe8d49a6e476b9fff062f8003 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
@@ -241,7 +241,7 @@ static const struct dpu_wb_cfg sm7150_wb[] = {
{
.name = "wb_2", .id = WB_2,
.base = 0x65000, .len = 0x2c8,
- .features = WB_SM8250_MASK,
+ .features = WB_SDM845_MASK,
.format_list = wb2_formats_rgb_yuv,
.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
.clk_ctrl = DPU_CLK_CTRL_WB2,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
index 8fb926bff36d32fb4ce1036cb69513599dc7b6b7..a065f102ce592311376f1186add7a47dca7fd84f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
@@ -154,7 +154,7 @@ static const struct dpu_wb_cfg sm6150_wb[] = {
{
.name = "wb_2", .id = WB_2,
.base = 0x65000, .len = 0x2c8,
- .features = WB_SM8250_MASK,
+ .features = WB_SDM845_MASK,
.format_list = wb2_formats_rgb_yuv,
.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
.clk_ctrl = DPU_CLK_CTRL_WB2,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
index 5c2c8c5f812347970c534769d72f9699e6e7049a..2950245e7b3f5e38f3f501a7314bb97c66d05982 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
@@ -133,7 +133,7 @@ static const struct dpu_wb_cfg sm6125_wb[] = {
{
.name = "wb_2", .id = WB_2,
.base = 0x65000, .len = 0x2c8,
- .features = WB_SM8250_MASK,
+ .features = WB_SDM845_MASK,
.format_list = wb2_formats_rgb_yuv,
.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
.clk_ctrl = DPU_CLK_CTRL_WB2,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
index 9ceff398fd6f554085440f509b6f8398b4fbf304..7b8b7a1c2d767eafca7e7440098bb28e2e108902 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
@@ -312,7 +312,7 @@ static const struct dpu_wb_cfg sm8250_wb[] = {
{
.name = "wb_2", .id = WB_2,
.base = 0x65000, .len = 0x2c8,
- .features = WB_SM8250_MASK,
+ .features = WB_SDM845_MASK,
.format_list = wb2_formats_rgb_yuv,
.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
.clk_ctrl = DPU_CLK_CTRL_WB2,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
index f6a0f1a39dcc3c9e82c07889d71905434274cdf9..c990ba3b5db02d65934179d5ad42bd740f6944b2 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
@@ -148,7 +148,7 @@ static const struct dpu_wb_cfg sc7180_wb[] = {
{
.name = "wb_2", .id = WB_2,
.base = 0x65000, .len = 0x2c8,
- .features = WB_SM8250_MASK,
+ .features = WB_SDM845_MASK,
.format_list = wb2_formats_rgb_yuv,
.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
.clk_ctrl = DPU_CLK_CTRL_WB2,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
index a46e9e3ff565ba5ef233af76f1c6cebb1d0c318a..093d16bdc450af348da1775ff017d982236b11b0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
@@ -142,7 +142,7 @@ static const struct dpu_wb_cfg sm6350_wb[] = {
{
.name = "wb_2", .id = WB_2,
.base = 0x65000, .len = 0x2c8,
- .features = WB_SM8250_MASK,
+ .features = WB_SDM845_MASK,
.format_list = wb2_formats_rgb_yuv,
.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
.clk_ctrl = DPU_CLK_CTRL_WB2,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
index b4d41e2644349bdbdbdacbe1e9b3748f90df4f3b..85aae40c210f3aa1b29bf0b5ea81ee1f551a6ef6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
@@ -285,7 +285,7 @@ static const struct dpu_wb_cfg sm8350_wb[] = {
{
.name = "wb_2", .id = WB_2,
.base = 0x65000, .len = 0x2c8,
- .features = WB_SM8250_MASK,
+ .features = WB_SDM845_MASK,
.format_list = wb2_formats_rgb_yuv,
.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
.clk_ctrl = DPU_CLK_CTRL_WB2,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
index 5d88f0261d8320a78f8d64c9bb68b938f83160a0..8f978b9c345202d3ea1a7781e4ef2763b46c6f6e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
@@ -159,7 +159,7 @@ static const struct dpu_wb_cfg sc7280_wb[] = {
{
.name = "wb_2", .id = WB_2,
.base = 0x65000, .len = 0x2c8,
- .features = WB_SM8250_MASK,
+ .features = WB_SDM845_MASK,
.format_list = wb2_formats_rgb_yuv,
.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
.clk_ctrl = DPU_CLK_CTRL_WB2,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
index 3c0728a4b37ea6af25ab64315cfe63ba6f8d2774..b09a6af4c474aa9301c0ef6bc0ce71ba42cce3a2 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
@@ -298,7 +298,7 @@ static const struct dpu_wb_cfg sm8450_wb[] = {
{
.name = "wb_2", .id = WB_2,
.base = 0x65000, .len = 0x2c8,
- .features = WB_SM8250_MASK,
+ .features = WB_SDM845_MASK,
.format_list = wb2_formats_rgb_yuv,
.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
.clk_ctrl = DPU_CLK_CTRL_WB2,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
index b8a1646395916fde04b9750cf548edca5729d9c2..0f7b4a224e4c971f482c3778c92e8c170b44223f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
@@ -305,7 +305,7 @@ static const struct dpu_wb_cfg sa8775p_wb[] = {
{
.name = "wb_2", .id = WB_2,
.base = 0x65000, .len = 0x2c8,
- .features = WB_SM8250_MASK,
+ .features = WB_SDM845_MASK,
.format_list = wb2_formats_rgb_yuv,
.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
.clk_ctrl = DPU_CLK_CTRL_WB2,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
index ef22a9adf43ddc9d15be5f1359ea5f6690e9f27c..465b6460f8754df18bbcf4baac2f8a3ebdea3324 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
@@ -294,7 +294,7 @@ static const struct dpu_wb_cfg sm8550_wb[] = {
{
.name = "wb_2", .id = WB_2,
.base = 0x65000, .len = 0x2c8,
- .features = WB_SM8250_MASK,
+ .features = WB_SDM845_MASK,
.format_list = wb2_formats_rgb_yuv,
.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
.xin_id = 6,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
index 2e7d4403835353927bc85a5acd3e6c5967cac455..6caa7d40f368802793c8690544c1c82b49a617cd 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
@@ -294,7 +294,7 @@ static const struct dpu_wb_cfg sar2130p_wb[] = {
{
.name = "wb_2", .id = WB_2,
.base = 0x65000, .len = 0x2c8,
- .features = WB_SM8250_MASK,
+ .features = WB_SDM845_MASK,
.format_list = wb2_formats_rgb_yuv,
.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
.xin_id = 6,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
index ac95d46b3ecf2d95ec0d516a79567fe9c204b5f6..7243eebb85f36f2a8ae848f2c95d21b0bc3bebef 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
@@ -294,7 +294,7 @@ static const struct dpu_wb_cfg x1e80100_wb[] = {
{
.name = "wb_2", .id = WB_2,
.base = 0x65000, .len = 0x2c8,
- .features = WB_SM8250_MASK,
+ .features = WB_SDM845_MASK,
.format_list = wb2_formats_rgb_yuv,
.num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
.xin_id = 6,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index ad0460aa5b5ce5a373dab18c89e4159855da4d2b..6d7be74bafe326a1998a69ed9b3495c5acf6350f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -98,9 +98,6 @@
BIT(DPU_WB_QOS_8LVL) | \
BIT(DPU_WB_CDP))
-#define WB_SM8250_MASK (WB_SDM845_MASK | \
- BIT(DPU_WB_INPUT_CTRL))
-
#define DEFAULT_PIXEL_RAM_SIZE (50 * 1024)
#define DEFAULT_DPU_LINE_WIDTH 2048
#define DEFAULT_DPU_OUTPUT_LINE_WIDTH 2560
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 41906dadff5a8ef39b2e90f3e80bb699a5cf59b7..8c394e7d6496ca2d120c81c7776b4b979368be23 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -140,8 +140,6 @@ enum {
* @DPU_WB_QOS, Writeback supports QoS control, danger/safe/creq
* @DPU_WB_QOS_8LVL, Writeback supports 8-level QoS control
* @DPU_WB_CDP Writeback supports client driven prefetch
- * @DPU_WB_INPUT_CTRL Writeback supports from which pp block input pixel
- * data arrives.
* @DPU_WB_CROP CWB supports cropping
* @DPU_WB_MAX maximum value
*/
@@ -155,7 +153,6 @@ enum {
DPU_WB_QOS,
DPU_WB_QOS_8LVL,
DPU_WB_CDP,
- DPU_WB_INPUT_CTRL,
DPU_WB_CROP,
DPU_WB_MAX
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
index 4853e516c48733231de240b9c32ad51d4cf18f0d..478a091aeccfc7cf298798e1c119df56737e3dc4 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
@@ -208,7 +208,7 @@ static void _setup_wb_ops(struct dpu_hw_wb_ops *ops,
if (test_bit(DPU_WB_CDP, &features))
ops->setup_cdp = dpu_hw_wb_setup_cdp;
- if (test_bit(DPU_WB_INPUT_CTRL, &features))
+ if (mdss_rev->core_major_ver >= 5)
ops->bind_pingpong_blk = dpu_hw_wb_bind_pingpong_blk;
if (mdss_rev->core_major_ver >= 9)
--
2.39.5
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH v4 25/30] drm/msm/dpu: get rid of DPU_WB_INPUT_CTRL
2025-05-19 16:04 ` [PATCH v4 25/30] drm/msm/dpu: get rid of DPU_WB_INPUT_CTRL Dmitry Baryshkov
@ 2025-05-20 8:04 ` neil.armstrong
0 siblings, 0 replies; 64+ messages in thread
From: neil.armstrong @ 2025-05-20 8:04 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Abhinav Kumar, Sean Paul,
Marijn Suijten, David Airlie, Simona Vetter, Vinod Koul,
Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel,
Dmitry Baryshkov
On 19/05/2025 18:04, Dmitry Baryshkov wrote:
> Continue migration to the MDSS-revision based checks and replace
> DPU_WB_INPUT_CTRL feature bit with the core_major_ver >= 5 check.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 3 ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 2 +-
> 19 files changed, 17 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
> index 013314b2e716a6d939393b77b0edc87170dba27b..56d3c38c87781edb438b277c77382848b679198f 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
> @@ -318,7 +318,7 @@ static const struct dpu_wb_cfg sm8650_wb[] = {
> {
> .name = "wb_2", .id = WB_2,
> .base = 0x65000, .len = 0x2c8,
> - .features = WB_SM8250_MASK,
> + .features = WB_SDM845_MASK,
> .format_list = wb2_formats_rgb_yuv,
> .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
> .xin_id = 6,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> index 5d3b864d28a86fb86fc4576210c9418604afd844..ae1b2ed96e9f10a6e7a710fc8bb4e40dec665cf9 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> @@ -275,7 +275,7 @@ static const struct dpu_wb_cfg sm8150_wb[] = {
> {
> .name = "wb_2", .id = WB_2,
> .base = 0x65000, .len = 0x2c8,
> - .features = WB_SM8250_MASK,
> + .features = WB_SDM845_MASK,
> .format_list = wb2_formats_rgb_yuv,
> .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
> .clk_ctrl = DPU_CLK_CTRL_WB2,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> index a6e9dfc583f283d752545b3f700c3d509e2a2965..fc80406759cd52f0d633927c8ba876feaff48e07 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> @@ -281,7 +281,7 @@ static const struct dpu_wb_cfg sc8180x_wb[] = {
> {
> .name = "wb_2", .id = WB_2,
> .base = 0x65000, .len = 0x2c8,
> - .features = WB_SM8250_MASK,
> + .features = WB_SDM845_MASK,
> .format_list = wb2_formats_rgb_yuv,
> .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
> .clk_ctrl = DPU_CLK_CTRL_WB2,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
> index fe9c9301e3d9d2d3a0a34ab9aed0f307d08c34ca..a56c288ac10cd3dfe8d49a6e476b9fff062f8003 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
> @@ -241,7 +241,7 @@ static const struct dpu_wb_cfg sm7150_wb[] = {
> {
> .name = "wb_2", .id = WB_2,
> .base = 0x65000, .len = 0x2c8,
> - .features = WB_SM8250_MASK,
> + .features = WB_SDM845_MASK,
> .format_list = wb2_formats_rgb_yuv,
> .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
> .clk_ctrl = DPU_CLK_CTRL_WB2,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
> index 8fb926bff36d32fb4ce1036cb69513599dc7b6b7..a065f102ce592311376f1186add7a47dca7fd84f 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
> @@ -154,7 +154,7 @@ static const struct dpu_wb_cfg sm6150_wb[] = {
> {
> .name = "wb_2", .id = WB_2,
> .base = 0x65000, .len = 0x2c8,
> - .features = WB_SM8250_MASK,
> + .features = WB_SDM845_MASK,
> .format_list = wb2_formats_rgb_yuv,
> .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
> .clk_ctrl = DPU_CLK_CTRL_WB2,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
> index 5c2c8c5f812347970c534769d72f9699e6e7049a..2950245e7b3f5e38f3f501a7314bb97c66d05982 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
> @@ -133,7 +133,7 @@ static const struct dpu_wb_cfg sm6125_wb[] = {
> {
> .name = "wb_2", .id = WB_2,
> .base = 0x65000, .len = 0x2c8,
> - .features = WB_SM8250_MASK,
> + .features = WB_SDM845_MASK,
> .format_list = wb2_formats_rgb_yuv,
> .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
> .clk_ctrl = DPU_CLK_CTRL_WB2,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> index 9ceff398fd6f554085440f509b6f8398b4fbf304..7b8b7a1c2d767eafca7e7440098bb28e2e108902 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> @@ -312,7 +312,7 @@ static const struct dpu_wb_cfg sm8250_wb[] = {
> {
> .name = "wb_2", .id = WB_2,
> .base = 0x65000, .len = 0x2c8,
> - .features = WB_SM8250_MASK,
> + .features = WB_SDM845_MASK,
> .format_list = wb2_formats_rgb_yuv,
> .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
> .clk_ctrl = DPU_CLK_CTRL_WB2,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> index f6a0f1a39dcc3c9e82c07889d71905434274cdf9..c990ba3b5db02d65934179d5ad42bd740f6944b2 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> @@ -148,7 +148,7 @@ static const struct dpu_wb_cfg sc7180_wb[] = {
> {
> .name = "wb_2", .id = WB_2,
> .base = 0x65000, .len = 0x2c8,
> - .features = WB_SM8250_MASK,
> + .features = WB_SDM845_MASK,
> .format_list = wb2_formats_rgb_yuv,
> .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
> .clk_ctrl = DPU_CLK_CTRL_WB2,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> index a46e9e3ff565ba5ef233af76f1c6cebb1d0c318a..093d16bdc450af348da1775ff017d982236b11b0 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> @@ -142,7 +142,7 @@ static const struct dpu_wb_cfg sm6350_wb[] = {
> {
> .name = "wb_2", .id = WB_2,
> .base = 0x65000, .len = 0x2c8,
> - .features = WB_SM8250_MASK,
> + .features = WB_SDM845_MASK,
> .format_list = wb2_formats_rgb_yuv,
> .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
> .clk_ctrl = DPU_CLK_CTRL_WB2,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> index b4d41e2644349bdbdbdacbe1e9b3748f90df4f3b..85aae40c210f3aa1b29bf0b5ea81ee1f551a6ef6 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> @@ -285,7 +285,7 @@ static const struct dpu_wb_cfg sm8350_wb[] = {
> {
> .name = "wb_2", .id = WB_2,
> .base = 0x65000, .len = 0x2c8,
> - .features = WB_SM8250_MASK,
> + .features = WB_SDM845_MASK,
> .format_list = wb2_formats_rgb_yuv,
> .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
> .clk_ctrl = DPU_CLK_CTRL_WB2,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> index 5d88f0261d8320a78f8d64c9bb68b938f83160a0..8f978b9c345202d3ea1a7781e4ef2763b46c6f6e 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> @@ -159,7 +159,7 @@ static const struct dpu_wb_cfg sc7280_wb[] = {
> {
> .name = "wb_2", .id = WB_2,
> .base = 0x65000, .len = 0x2c8,
> - .features = WB_SM8250_MASK,
> + .features = WB_SDM845_MASK,
> .format_list = wb2_formats_rgb_yuv,
> .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
> .clk_ctrl = DPU_CLK_CTRL_WB2,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> index 3c0728a4b37ea6af25ab64315cfe63ba6f8d2774..b09a6af4c474aa9301c0ef6bc0ce71ba42cce3a2 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> @@ -298,7 +298,7 @@ static const struct dpu_wb_cfg sm8450_wb[] = {
> {
> .name = "wb_2", .id = WB_2,
> .base = 0x65000, .len = 0x2c8,
> - .features = WB_SM8250_MASK,
> + .features = WB_SDM845_MASK,
> .format_list = wb2_formats_rgb_yuv,
> .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
> .clk_ctrl = DPU_CLK_CTRL_WB2,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
> index b8a1646395916fde04b9750cf548edca5729d9c2..0f7b4a224e4c971f482c3778c92e8c170b44223f 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
> @@ -305,7 +305,7 @@ static const struct dpu_wb_cfg sa8775p_wb[] = {
> {
> .name = "wb_2", .id = WB_2,
> .base = 0x65000, .len = 0x2c8,
> - .features = WB_SM8250_MASK,
> + .features = WB_SDM845_MASK,
> .format_list = wb2_formats_rgb_yuv,
> .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
> .clk_ctrl = DPU_CLK_CTRL_WB2,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> index ef22a9adf43ddc9d15be5f1359ea5f6690e9f27c..465b6460f8754df18bbcf4baac2f8a3ebdea3324 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> @@ -294,7 +294,7 @@ static const struct dpu_wb_cfg sm8550_wb[] = {
> {
> .name = "wb_2", .id = WB_2,
> .base = 0x65000, .len = 0x2c8,
> - .features = WB_SM8250_MASK,
> + .features = WB_SDM845_MASK,
> .format_list = wb2_formats_rgb_yuv,
> .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
> .xin_id = 6,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
> index 2e7d4403835353927bc85a5acd3e6c5967cac455..6caa7d40f368802793c8690544c1c82b49a617cd 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
> @@ -294,7 +294,7 @@ static const struct dpu_wb_cfg sar2130p_wb[] = {
> {
> .name = "wb_2", .id = WB_2,
> .base = 0x65000, .len = 0x2c8,
> - .features = WB_SM8250_MASK,
> + .features = WB_SDM845_MASK,
> .format_list = wb2_formats_rgb_yuv,
> .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
> .xin_id = 6,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
> index ac95d46b3ecf2d95ec0d516a79567fe9c204b5f6..7243eebb85f36f2a8ae848f2c95d21b0bc3bebef 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
> @@ -294,7 +294,7 @@ static const struct dpu_wb_cfg x1e80100_wb[] = {
> {
> .name = "wb_2", .id = WB_2,
> .base = 0x65000, .len = 0x2c8,
> - .features = WB_SM8250_MASK,
> + .features = WB_SDM845_MASK,
> .format_list = wb2_formats_rgb_yuv,
> .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
> .xin_id = 6,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index ad0460aa5b5ce5a373dab18c89e4159855da4d2b..6d7be74bafe326a1998a69ed9b3495c5acf6350f 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -98,9 +98,6 @@
> BIT(DPU_WB_QOS_8LVL) | \
> BIT(DPU_WB_CDP))
>
> -#define WB_SM8250_MASK (WB_SDM845_MASK | \
> - BIT(DPU_WB_INPUT_CTRL))
> -
> #define DEFAULT_PIXEL_RAM_SIZE (50 * 1024)
> #define DEFAULT_DPU_LINE_WIDTH 2048
> #define DEFAULT_DPU_OUTPUT_LINE_WIDTH 2560
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index 41906dadff5a8ef39b2e90f3e80bb699a5cf59b7..8c394e7d6496ca2d120c81c7776b4b979368be23 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -140,8 +140,6 @@ enum {
> * @DPU_WB_QOS, Writeback supports QoS control, danger/safe/creq
> * @DPU_WB_QOS_8LVL, Writeback supports 8-level QoS control
> * @DPU_WB_CDP Writeback supports client driven prefetch
> - * @DPU_WB_INPUT_CTRL Writeback supports from which pp block input pixel
> - * data arrives.
> * @DPU_WB_CROP CWB supports cropping
> * @DPU_WB_MAX maximum value
> */
> @@ -155,7 +153,6 @@ enum {
> DPU_WB_QOS,
> DPU_WB_QOS_8LVL,
> DPU_WB_CDP,
> - DPU_WB_INPUT_CTRL,
> DPU_WB_CROP,
> DPU_WB_MAX
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
> index 4853e516c48733231de240b9c32ad51d4cf18f0d..478a091aeccfc7cf298798e1c119df56737e3dc4 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
> @@ -208,7 +208,7 @@ static void _setup_wb_ops(struct dpu_hw_wb_ops *ops,
> if (test_bit(DPU_WB_CDP, &features))
> ops->setup_cdp = dpu_hw_wb_setup_cdp;
>
> - if (test_bit(DPU_WB_INPUT_CTRL, &features))
> + if (mdss_rev->core_major_ver >= 5)
> ops->bind_pingpong_blk = dpu_hw_wb_bind_pingpong_blk;
>
> if (mdss_rev->core_major_ver >= 9)
>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH v4 26/30] drm/msm/dpu: get rid of DPU_SSPP_QOS_8LVL
2025-05-19 16:04 [PATCH v4 00/30] drm/msm/dpu: rework HW block feature handling Dmitry Baryshkov
` (24 preceding siblings ...)
2025-05-19 16:04 ` [PATCH v4 25/30] drm/msm/dpu: get rid of DPU_WB_INPUT_CTRL Dmitry Baryshkov
@ 2025-05-19 16:04 ` Dmitry Baryshkov
2025-05-20 8:04 ` neil.armstrong
2025-05-19 16:04 ` [PATCH v4 27/30] drm/msm/dpu: drop unused MDP TOP features Dmitry Baryshkov
` (3 subsequent siblings)
29 siblings, 1 reply; 64+ messages in thread
From: Dmitry Baryshkov @ 2025-05-19 16:04 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Sean Paul, Marijn Suijten, David Airlie,
Simona Vetter, Vinod Koul, Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel,
Dmitry Baryshkov
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Continue migration to the MDSS-revision based checks and replace
DPU_SSPP_QOS_8LVL feature bit with the core_major_ver >= 4 check.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 6 +++---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 --
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 5 ++++-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 2 ++
4 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 6d7be74bafe326a1998a69ed9b3495c5acf6350f..a276a1beaf95d183f6119452e5516fa8ee60cef6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -35,12 +35,12 @@
(VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3_COMPATIBLE))
#define VIG_SDM845_MASK_NO_SDMA \
- (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3_COMPATIBLE))
+ (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3_COMPATIBLE))
#define VIG_SDM845_MASK_SDMA \
(VIG_SDM845_MASK_NO_SDMA | BIT(DPU_SSPP_SMART_DMA_V2))
-#define VIG_QCM2290_MASK (VIG_BASE_MASK | BIT(DPU_SSPP_QOS_8LVL))
+#define VIG_QCM2290_MASK (VIG_BASE_MASK)
#define DMA_MSM8953_MASK \
(BIT(DPU_SSPP_QOS))
@@ -60,7 +60,7 @@
(VIG_SC7280_MASK | BIT(DPU_SSPP_SMART_DMA_V2))
#define DMA_SDM845_MASK_NO_SDMA \
- (BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\
+ (BIT(DPU_SSPP_QOS) | \
BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\
BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT))
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 8c394e7d6496ca2d120c81c7776b4b979368be23..c582ef1ffe022f2e92b1b80cbab97ff41a2acfe9 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -50,7 +50,6 @@ enum {
* @DPU_SSPP_CSC_10BIT, Support of 10-bit Color space conversion
* @DPU_SSPP_CURSOR, SSPP can be used as a cursor layer
* @DPU_SSPP_QOS, SSPP support QoS control, danger/safe/creq
- * @DPU_SSPP_QOS_8LVL, SSPP support 8-level QoS control
* @DPU_SSPP_EXCL_RECT, SSPP supports exclusion rect
* @DPU_SSPP_SMART_DMA_V1, SmartDMA 1.0 support
* @DPU_SSPP_SMART_DMA_V2, SmartDMA 2.0 support
@@ -68,7 +67,6 @@ enum {
DPU_SSPP_CSC_10BIT,
DPU_SSPP_CURSOR,
DPU_SSPP_QOS,
- DPU_SSPP_QOS_8LVL,
DPU_SSPP_EXCL_RECT,
DPU_SSPP_SMART_DMA_V1,
DPU_SSPP_SMART_DMA_V2,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
index 32c7c80845533d720683dbcde3978d98f4972cce..7dfd0e0a779535e1f6b003f48188bc90d29d6853 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
@@ -543,7 +543,7 @@ static void dpu_hw_sspp_setup_qos_lut(struct dpu_hw_sspp *ctx,
return;
_dpu_hw_setup_qos_lut(&ctx->hw, SSPP_DANGER_LUT,
- test_bit(DPU_SSPP_QOS_8LVL, &ctx->cap->features),
+ ctx->mdss_ver->core_major_ver >= 4,
cfg);
}
@@ -703,6 +703,9 @@ struct dpu_hw_sspp *dpu_hw_sspp_init(struct drm_device *dev,
hw_pipe->ubwc = mdss_data;
hw_pipe->idx = cfg->id;
hw_pipe->cap = cfg;
+
+ hw_pipe->mdss_ver = mdss_rev;
+
_setup_layer_ops(hw_pipe, hw_pipe->cap->features, mdss_rev);
return hw_pipe;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
index 56a0edf2a57c6dcef7cddf4a1bcd6f6df5ad60f6..ed90e78d178a497ae7e2dc12b09a37c8a3f79621 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
@@ -314,6 +314,8 @@ struct dpu_hw_sspp {
enum dpu_sspp idx;
const struct dpu_sspp_cfg *cap;
+ const struct dpu_mdss_version *mdss_ver;
+
/* Ops */
struct dpu_hw_sspp_ops ops;
};
--
2.39.5
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH v4 26/30] drm/msm/dpu: get rid of DPU_SSPP_QOS_8LVL
2025-05-19 16:04 ` [PATCH v4 26/30] drm/msm/dpu: get rid of DPU_SSPP_QOS_8LVL Dmitry Baryshkov
@ 2025-05-20 8:04 ` neil.armstrong
0 siblings, 0 replies; 64+ messages in thread
From: neil.armstrong @ 2025-05-20 8:04 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Abhinav Kumar, Sean Paul,
Marijn Suijten, David Airlie, Simona Vetter, Vinod Koul,
Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel,
Dmitry Baryshkov
On 19/05/2025 18:04, Dmitry Baryshkov wrote:
> From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>
> Continue migration to the MDSS-revision based checks and replace
> DPU_SSPP_QOS_8LVL feature bit with the core_major_ver >= 4 check.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 6 +++---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 --
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 5 ++++-
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 2 ++
> 4 files changed, 9 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index 6d7be74bafe326a1998a69ed9b3495c5acf6350f..a276a1beaf95d183f6119452e5516fa8ee60cef6 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -35,12 +35,12 @@
> (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3_COMPATIBLE))
>
> #define VIG_SDM845_MASK_NO_SDMA \
> - (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3_COMPATIBLE))
> + (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3_COMPATIBLE))
>
> #define VIG_SDM845_MASK_SDMA \
> (VIG_SDM845_MASK_NO_SDMA | BIT(DPU_SSPP_SMART_DMA_V2))
>
> -#define VIG_QCM2290_MASK (VIG_BASE_MASK | BIT(DPU_SSPP_QOS_8LVL))
> +#define VIG_QCM2290_MASK (VIG_BASE_MASK)
>
> #define DMA_MSM8953_MASK \
> (BIT(DPU_SSPP_QOS))
> @@ -60,7 +60,7 @@
> (VIG_SC7280_MASK | BIT(DPU_SSPP_SMART_DMA_V2))
>
> #define DMA_SDM845_MASK_NO_SDMA \
> - (BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\
> + (BIT(DPU_SSPP_QOS) | \
> BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\
> BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT))
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index 8c394e7d6496ca2d120c81c7776b4b979368be23..c582ef1ffe022f2e92b1b80cbab97ff41a2acfe9 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -50,7 +50,6 @@ enum {
> * @DPU_SSPP_CSC_10BIT, Support of 10-bit Color space conversion
> * @DPU_SSPP_CURSOR, SSPP can be used as a cursor layer
> * @DPU_SSPP_QOS, SSPP support QoS control, danger/safe/creq
> - * @DPU_SSPP_QOS_8LVL, SSPP support 8-level QoS control
> * @DPU_SSPP_EXCL_RECT, SSPP supports exclusion rect
> * @DPU_SSPP_SMART_DMA_V1, SmartDMA 1.0 support
> * @DPU_SSPP_SMART_DMA_V2, SmartDMA 2.0 support
> @@ -68,7 +67,6 @@ enum {
> DPU_SSPP_CSC_10BIT,
> DPU_SSPP_CURSOR,
> DPU_SSPP_QOS,
> - DPU_SSPP_QOS_8LVL,
> DPU_SSPP_EXCL_RECT,
> DPU_SSPP_SMART_DMA_V1,
> DPU_SSPP_SMART_DMA_V2,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> index 32c7c80845533d720683dbcde3978d98f4972cce..7dfd0e0a779535e1f6b003f48188bc90d29d6853 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> @@ -543,7 +543,7 @@ static void dpu_hw_sspp_setup_qos_lut(struct dpu_hw_sspp *ctx,
> return;
>
> _dpu_hw_setup_qos_lut(&ctx->hw, SSPP_DANGER_LUT,
> - test_bit(DPU_SSPP_QOS_8LVL, &ctx->cap->features),
> + ctx->mdss_ver->core_major_ver >= 4,
> cfg);
> }
>
> @@ -703,6 +703,9 @@ struct dpu_hw_sspp *dpu_hw_sspp_init(struct drm_device *dev,
> hw_pipe->ubwc = mdss_data;
> hw_pipe->idx = cfg->id;
> hw_pipe->cap = cfg;
> +
> + hw_pipe->mdss_ver = mdss_rev;
> +
> _setup_layer_ops(hw_pipe, hw_pipe->cap->features, mdss_rev);
>
> return hw_pipe;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
> index 56a0edf2a57c6dcef7cddf4a1bcd6f6df5ad60f6..ed90e78d178a497ae7e2dc12b09a37c8a3f79621 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
> @@ -314,6 +314,8 @@ struct dpu_hw_sspp {
> enum dpu_sspp idx;
> const struct dpu_sspp_cfg *cap;
>
> + const struct dpu_mdss_version *mdss_ver;
> +
> /* Ops */
> struct dpu_hw_sspp_ops ops;
> };
>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH v4 27/30] drm/msm/dpu: drop unused MDP TOP features
2025-05-19 16:04 [PATCH v4 00/30] drm/msm/dpu: rework HW block feature handling Dmitry Baryshkov
` (25 preceding siblings ...)
2025-05-19 16:04 ` [PATCH v4 26/30] drm/msm/dpu: get rid of DPU_SSPP_QOS_8LVL Dmitry Baryshkov
@ 2025-05-19 16:04 ` Dmitry Baryshkov
2025-05-20 8:05 ` neil.armstrong
2025-05-19 16:04 ` [PATCH v4 28/30] drm/msm/dpu: drop ununused PINGPONG features Dmitry Baryshkov
` (2 subsequent siblings)
29 siblings, 1 reply; 64+ messages in thread
From: Dmitry Baryshkov @ 2025-05-19 16:04 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Sean Paul, Marijn Suijten, David Airlie,
Simona Vetter, Vinod Koul, Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel,
Dmitry Baryshkov
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Drop unused MDP TOP features from the current codebase.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 13 -------------
1 file changed, 13 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index c582ef1ffe022f2e92b1b80cbab97ff41a2acfe9..9658561c4cb653ca86094d67f7b5dc92d36d38cd 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -28,19 +28,6 @@
#define MAX_XIN_COUNT 16
-/**
- * MDP TOP BLOCK features
- * @DPU_MDP_PANIC_PER_PIPE Panic configuration needs to be done per pipe
- * @DPU_MDP_10BIT_SUPPORT, Chipset supports 10 bit pixel formats
- * @DPU_MDP_MAX Maximum value
-
- */
-enum {
- DPU_MDP_PANIC_PER_PIPE = 0x1,
- DPU_MDP_10BIT_SUPPORT,
- DPU_MDP_MAX
-};
-
/**
* SSPP sub-blocks/features
* @DPU_SSPP_SCALER_QSEED2, QSEED2 algorithm support
--
2.39.5
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH v4 27/30] drm/msm/dpu: drop unused MDP TOP features
2025-05-19 16:04 ` [PATCH v4 27/30] drm/msm/dpu: drop unused MDP TOP features Dmitry Baryshkov
@ 2025-05-20 8:05 ` neil.armstrong
0 siblings, 0 replies; 64+ messages in thread
From: neil.armstrong @ 2025-05-20 8:05 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Abhinav Kumar, Sean Paul,
Marijn Suijten, David Airlie, Simona Vetter, Vinod Koul,
Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel,
Dmitry Baryshkov
On 19/05/2025 18:04, Dmitry Baryshkov wrote:
> From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>
> Drop unused MDP TOP features from the current codebase.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 13 -------------
> 1 file changed, 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index c582ef1ffe022f2e92b1b80cbab97ff41a2acfe9..9658561c4cb653ca86094d67f7b5dc92d36d38cd 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -28,19 +28,6 @@
>
> #define MAX_XIN_COUNT 16
>
> -/**
> - * MDP TOP BLOCK features
> - * @DPU_MDP_PANIC_PER_PIPE Panic configuration needs to be done per pipe
> - * @DPU_MDP_10BIT_SUPPORT, Chipset supports 10 bit pixel formats
> - * @DPU_MDP_MAX Maximum value
> -
> - */
> -enum {
> - DPU_MDP_PANIC_PER_PIPE = 0x1,
> - DPU_MDP_10BIT_SUPPORT,
> - DPU_MDP_MAX
> -};
> -
> /**
> * SSPP sub-blocks/features
> * @DPU_SSPP_SCALER_QSEED2, QSEED2 algorithm support
>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH v4 28/30] drm/msm/dpu: drop ununused PINGPONG features
2025-05-19 16:04 [PATCH v4 00/30] drm/msm/dpu: rework HW block feature handling Dmitry Baryshkov
` (26 preceding siblings ...)
2025-05-19 16:04 ` [PATCH v4 27/30] drm/msm/dpu: drop unused MDP TOP features Dmitry Baryshkov
@ 2025-05-19 16:04 ` Dmitry Baryshkov
2025-05-20 8:05 ` neil.armstrong
2025-05-19 16:04 ` [PATCH v4 29/30] drm/msm/dpu: drop ununused MIXER features Dmitry Baryshkov
2025-05-19 16:04 ` [PATCH v4 30/30] drm/msm/dpu: move features out of the DPU_HW_BLK_INFO Dmitry Baryshkov
29 siblings, 1 reply; 64+ messages in thread
From: Dmitry Baryshkov @ 2025-05-19 16:04 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Sean Paul, Marijn Suijten, David Airlie,
Simona Vetter, Vinod Koul, Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel,
Dmitry Baryshkov
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
All existing PINGPONG feature bits are completely unused. Drop them from
the current codebase.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 12 ------------
1 file changed, 12 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 9658561c4cb653ca86094d67f7b5dc92d36d38cd..c1488a2c160b0e2ab08243a6e2bd099329ae759b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -87,18 +87,6 @@ enum {
DPU_DSPP_MAX
};
-/**
- * PINGPONG sub-blocks
- * @DPU_PINGPONG_SPLIT PP block supports split fifo
- * @DPU_PINGPONG_SLAVE PP block is a suitable slave for split fifo
- * @DPU_PINGPONG_MAX
- */
-enum {
- DPU_PINGPONG_SPLIT = 0x1,
- DPU_PINGPONG_SLAVE,
- DPU_PINGPONG_MAX
-};
-
/**
* CTL sub-blocks
* @DPU_CTL_SPLIT_DISPLAY: CTL supports video mode split display
--
2.39.5
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH v4 28/30] drm/msm/dpu: drop ununused PINGPONG features
2025-05-19 16:04 ` [PATCH v4 28/30] drm/msm/dpu: drop ununused PINGPONG features Dmitry Baryshkov
@ 2025-05-20 8:05 ` neil.armstrong
0 siblings, 0 replies; 64+ messages in thread
From: neil.armstrong @ 2025-05-20 8:05 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Abhinav Kumar, Sean Paul,
Marijn Suijten, David Airlie, Simona Vetter, Vinod Koul,
Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel,
Dmitry Baryshkov
On 19/05/2025 18:04, Dmitry Baryshkov wrote:
> From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>
> All existing PINGPONG feature bits are completely unused. Drop them from
> the current codebase.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 12 ------------
> 1 file changed, 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index 9658561c4cb653ca86094d67f7b5dc92d36d38cd..c1488a2c160b0e2ab08243a6e2bd099329ae759b 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -87,18 +87,6 @@ enum {
> DPU_DSPP_MAX
> };
>
> -/**
> - * PINGPONG sub-blocks
> - * @DPU_PINGPONG_SPLIT PP block supports split fifo
> - * @DPU_PINGPONG_SLAVE PP block is a suitable slave for split fifo
> - * @DPU_PINGPONG_MAX
> - */
> -enum {
> - DPU_PINGPONG_SPLIT = 0x1,
> - DPU_PINGPONG_SLAVE,
> - DPU_PINGPONG_MAX
> -};
> -
> /**
> * CTL sub-blocks
> * @DPU_CTL_SPLIT_DISPLAY: CTL supports video mode split display
>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH v4 29/30] drm/msm/dpu: drop ununused MIXER features
2025-05-19 16:04 [PATCH v4 00/30] drm/msm/dpu: rework HW block feature handling Dmitry Baryshkov
` (27 preceding siblings ...)
2025-05-19 16:04 ` [PATCH v4 28/30] drm/msm/dpu: drop ununused PINGPONG features Dmitry Baryshkov
@ 2025-05-19 16:04 ` Dmitry Baryshkov
2025-05-20 8:05 ` neil.armstrong
2025-05-19 16:04 ` [PATCH v4 30/30] drm/msm/dpu: move features out of the DPU_HW_BLK_INFO Dmitry Baryshkov
29 siblings, 1 reply; 64+ messages in thread
From: Dmitry Baryshkov @ 2025-05-19 16:04 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Sean Paul, Marijn Suijten, David Airlie,
Simona Vetter, Vinod Koul, Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel,
Dmitry Baryshkov
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Drop unused LM features from the current codebase.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index c1488a2c160b0e2ab08243a6e2bd099329ae759b..d51f6c5cdf62f3c00829167172ef6fd61f069986 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -66,16 +66,12 @@ enum {
/*
* MIXER sub-blocks/features
- * @DPU_MIXER_LAYER Layer mixer layer blend configuration,
* @DPU_MIXER_SOURCESPLIT Layer mixer supports source-split configuration
- * @DPU_MIXER_GC Gamma correction block
* @DPU_MIXER_MAX maximum value
*/
enum {
- DPU_MIXER_LAYER = 0x1,
- DPU_MIXER_SOURCESPLIT,
- DPU_MIXER_GC,
- DPU_MIXER_MAX
+ DPU_MIXER_SOURCESPLIT = 0x1,
+ DPU_MIXER_MAX,
};
/**
--
2.39.5
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH v4 29/30] drm/msm/dpu: drop ununused MIXER features
2025-05-19 16:04 ` [PATCH v4 29/30] drm/msm/dpu: drop ununused MIXER features Dmitry Baryshkov
@ 2025-05-20 8:05 ` neil.armstrong
0 siblings, 0 replies; 64+ messages in thread
From: neil.armstrong @ 2025-05-20 8:05 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Abhinav Kumar, Sean Paul,
Marijn Suijten, David Airlie, Simona Vetter, Vinod Koul,
Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel,
Dmitry Baryshkov
On 19/05/2025 18:04, Dmitry Baryshkov wrote:
> From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>
> Drop unused LM features from the current codebase.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 8 ++------
> 1 file changed, 2 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index c1488a2c160b0e2ab08243a6e2bd099329ae759b..d51f6c5cdf62f3c00829167172ef6fd61f069986 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -66,16 +66,12 @@ enum {
>
> /*
> * MIXER sub-blocks/features
> - * @DPU_MIXER_LAYER Layer mixer layer blend configuration,
> * @DPU_MIXER_SOURCESPLIT Layer mixer supports source-split configuration
> - * @DPU_MIXER_GC Gamma correction block
> * @DPU_MIXER_MAX maximum value
> */
> enum {
> - DPU_MIXER_LAYER = 0x1,
> - DPU_MIXER_SOURCESPLIT,
> - DPU_MIXER_GC,
> - DPU_MIXER_MAX
> + DPU_MIXER_SOURCESPLIT = 0x1,
> + DPU_MIXER_MAX,
> };
>
> /**
>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH v4 30/30] drm/msm/dpu: move features out of the DPU_HW_BLK_INFO
2025-05-19 16:04 [PATCH v4 00/30] drm/msm/dpu: rework HW block feature handling Dmitry Baryshkov
` (28 preceding siblings ...)
2025-05-19 16:04 ` [PATCH v4 29/30] drm/msm/dpu: drop ununused MIXER features Dmitry Baryshkov
@ 2025-05-19 16:04 ` Dmitry Baryshkov
2025-05-20 8:05 ` neil.armstrong
29 siblings, 1 reply; 64+ messages in thread
From: Dmitry Baryshkov @ 2025-05-19 16:04 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Sean Paul, Marijn Suijten, David Airlie,
Simona Vetter, Vinod Koul, Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel,
Dmitry Baryshkov
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
As features bits are now unused by some of the hardware block
configuration structures, remove the 'features' from the DPU_HW_BLK_INFO
so that it doesn't get included into hw info structures by default and
only include it when necessary.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 1 -
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 17 +++++++----------
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c | 5 ++---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c | 5 ++---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 4 ++--
6 files changed, 13 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
index a065f102ce592311376f1186add7a47dca7fd84f..26883f6b66b3e506d14eeb1c0bd64f556d19fef8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
@@ -20,7 +20,6 @@ static const struct dpu_caps sm6150_dpu_caps = {
static const struct dpu_mdp_cfg sm6150_mdp = {
.name = "top_0",
.base = 0x0, .len = 0x45c,
- .features = 0,
.clk_ctrls = {
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
index 2950245e7b3f5e38f3f501a7314bb97c66d05982..fbf50f279e6628cb0f92b0188e1fbdf156a899e2 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
@@ -22,7 +22,6 @@ static const struct dpu_caps sm6125_dpu_caps = {
static const struct dpu_mdp_cfg sm6125_mdp = {
.name = "top_0",
.base = 0x0, .len = 0x45c,
- .features = 0,
.clk_ctrls = {
[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index d51f6c5cdf62f3c00829167172ef6fd61f069986..47d82b83ac5378cb0001b3ea6605dc0f98aec5ef 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -154,14 +154,12 @@ enum {
* @id: enum identifying this block
* @base: register base offset to mdss
* @len: length of hardware block
- * @features bit mask identifying sub-blocks/features
*/
#define DPU_HW_BLK_INFO \
char name[DPU_HW_BLK_NAME_LEN]; \
u32 id; \
u32 base; \
- u32 len; \
- unsigned long features
+ u32 len
/**
* struct dpu_scaler_blk: Scaler information
@@ -376,7 +374,6 @@ struct dpu_clk_ctrl_reg {
/* struct dpu_mdp_cfg : MDP TOP-BLK instance info
* @id: index identifying this block
* @base: register base offset to mdss
- * @features bit mask identifying sub-blocks/features
* @clk_ctrls clock control register definition
*/
struct dpu_mdp_cfg {
@@ -392,6 +389,7 @@ struct dpu_mdp_cfg {
*/
struct dpu_ctl_cfg {
DPU_HW_BLK_INFO;
+ unsigned long features;
unsigned int intr_start;
};
@@ -407,6 +405,7 @@ struct dpu_ctl_cfg {
*/
struct dpu_sspp_cfg {
DPU_HW_BLK_INFO;
+ unsigned long features;
const struct dpu_sspp_sub_blks *sblk;
u32 xin_id;
enum dpu_clk_ctrl_type clk_ctrl;
@@ -424,6 +423,7 @@ struct dpu_sspp_cfg {
*/
struct dpu_lm_cfg {
DPU_HW_BLK_INFO;
+ unsigned long features;
const struct dpu_lm_sub_blks *sblk;
u32 pingpong;
u32 dspp;
@@ -434,7 +434,6 @@ struct dpu_lm_cfg {
* struct dpu_dspp_cfg - information of DSPP blocks
* @id enum identifying this block
* @base register offset of this block
- * @features bit mask identifying sub-blocks/features
* supported by this block
* @sblk sub-blocks information
*/
@@ -447,7 +446,6 @@ struct dpu_dspp_cfg {
* struct dpu_pingpong_cfg - information of PING-PONG blocks
* @id enum identifying this block
* @base register offset of this block
- * @features bit mask identifying sub-blocks/features
* @intr_done: index for PINGPONG done interrupt
* @intr_rdptr: index for PINGPONG readpointer done interrupt
* @sblk sub-blocks information
@@ -464,8 +462,6 @@ struct dpu_pingpong_cfg {
* struct dpu_merge_3d_cfg - information of DSPP blocks
* @id enum identifying this block
* @base register offset of this block
- * @features bit mask identifying sub-blocks/features
- * supported by this block
* @sblk sub-blocks information
*/
struct dpu_merge_3d_cfg {
@@ -483,6 +479,7 @@ struct dpu_merge_3d_cfg {
*/
struct dpu_dsc_cfg {
DPU_HW_BLK_INFO;
+ unsigned long features;
const struct dpu_dsc_sub_blks *sblk;
};
@@ -490,7 +487,6 @@ struct dpu_dsc_cfg {
* struct dpu_intf_cfg - information of timing engine blocks
* @id enum identifying this block
* @base register offset of this block
- * @features bit mask identifying sub-blocks/features
* @type: Interface type(DSI, DP, HDMI)
* @controller_id: Controller Instance ID in case of multiple of intf type
* @prog_fetch_lines_worst_case Worst case latency num lines needed to prefetch
@@ -521,6 +517,7 @@ struct dpu_intf_cfg {
*/
struct dpu_wb_cfg {
DPU_HW_BLK_INFO;
+ unsigned long features;
u8 vbif_idx;
u32 maxlinewidth;
u32 xin_id;
@@ -589,6 +586,7 @@ struct dpu_vbif_qos_tbl {
*/
struct dpu_vbif_cfg {
DPU_HW_BLK_INFO;
+ unsigned long features;
u32 default_ot_rd_limit;
u32 default_ot_wr_limit;
u32 xin_halt_timeout;
@@ -606,7 +604,6 @@ struct dpu_vbif_cfg {
* @name string name for debug purposes
* @id enum identifying this block
* @base register offset of this block
- * @features bit mask identifying sub-blocks/features
*/
struct dpu_cdm_cfg {
DPU_HW_BLK_INFO;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c
index b9c433567262a954b7f02233f6670ee6a8476846..b3395e9c34a19363019ec0ccfb0c87943553b4c9 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c
@@ -360,8 +360,7 @@ static void dpu_hw_dsc_bind_pingpong_blk_1_2(struct dpu_hw_dsc *hw_dsc,
DPU_REG_WRITE(hw, sblk->ctl.base + DSC_CTL, mux_cfg);
}
-static void _setup_dcs_ops_1_2(struct dpu_hw_dsc_ops *ops,
- const unsigned long features)
+static void _setup_dcs_ops_1_2(struct dpu_hw_dsc_ops *ops)
{
ops->dsc_disable = dpu_hw_dsc_disable_1_2;
ops->dsc_config = dpu_hw_dsc_config_1_2;
@@ -391,7 +390,7 @@ struct dpu_hw_dsc *dpu_hw_dsc_init_1_2(struct drm_device *dev,
c->idx = cfg->id;
c->caps = cfg;
- _setup_dcs_ops_1_2(&c->ops, c->caps->features);
+ _setup_dcs_ops_1_2(&c->ops);
return c;
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c
index 0b3325f9c8705999e1003e5c88872562e880229b..83b1dbecddd2b30402f47155fa2f9a148ead02c1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c
@@ -33,8 +33,7 @@ static void dpu_hw_merge_3d_setup_3d_mode(struct dpu_hw_merge_3d *merge_3d,
}
}
-static void _setup_merge_3d_ops(struct dpu_hw_merge_3d *c,
- unsigned long features)
+static void _setup_merge_3d_ops(struct dpu_hw_merge_3d *c)
{
c->ops.setup_3d_mode = dpu_hw_merge_3d_setup_3d_mode;
};
@@ -62,7 +61,7 @@ struct dpu_hw_merge_3d *dpu_hw_merge_3d_init(struct drm_device *dev,
c->idx = cfg->id;
c->caps = cfg;
- _setup_merge_3d_ops(c, c->caps->features);
+ _setup_merge_3d_ops(c);
return c;
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
index 5c811f0142d5e2a012d7e9b3a918818f22ec11cf..96dc10589bee6cf144eabaecf9f8ec5777431ac3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
@@ -264,7 +264,7 @@ static void dpu_hw_dp_phy_intf_sel(struct dpu_hw_mdp *mdp,
}
static void _setup_mdp_ops(struct dpu_hw_mdp_ops *ops,
- unsigned long cap, const struct dpu_mdss_version *mdss_rev)
+ const struct dpu_mdss_version *mdss_rev)
{
ops->setup_split_pipe = dpu_hw_setup_split_pipe;
ops->setup_clk_force_ctrl = dpu_hw_setup_clk_force_ctrl;
@@ -313,7 +313,7 @@ struct dpu_hw_mdp *dpu_hw_mdptop_init(struct drm_device *dev,
* Assign ops
*/
mdp->caps = cfg;
- _setup_mdp_ops(&mdp->ops, mdp->caps->features, mdss_rev);
+ _setup_mdp_ops(&mdp->ops, mdss_rev);
return mdp;
}
--
2.39.5
^ permalink raw reply related [flat|nested] 64+ messages in thread* Re: [PATCH v4 30/30] drm/msm/dpu: move features out of the DPU_HW_BLK_INFO
2025-05-19 16:04 ` [PATCH v4 30/30] drm/msm/dpu: move features out of the DPU_HW_BLK_INFO Dmitry Baryshkov
@ 2025-05-20 8:05 ` neil.armstrong
0 siblings, 0 replies; 64+ messages in thread
From: neil.armstrong @ 2025-05-20 8:05 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Abhinav Kumar, Sean Paul,
Marijn Suijten, David Airlie, Simona Vetter, Vinod Koul,
Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel,
Dmitry Baryshkov
On 19/05/2025 18:04, Dmitry Baryshkov wrote:
> From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>
> As features bits are now unused by some of the hardware block
> configuration structures, remove the 'features' from the DPU_HW_BLK_INFO
> so that it doesn't get included into hw info structures by default and
> only include it when necessary.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h | 1 -
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 1 -
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 17 +++++++----------
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c | 5 ++---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c | 5 ++---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 4 ++--
> 6 files changed, 13 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
> index a065f102ce592311376f1186add7a47dca7fd84f..26883f6b66b3e506d14eeb1c0bd64f556d19fef8 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
> @@ -20,7 +20,6 @@ static const struct dpu_caps sm6150_dpu_caps = {
> static const struct dpu_mdp_cfg sm6150_mdp = {
> .name = "top_0",
> .base = 0x0, .len = 0x45c,
> - .features = 0,
> .clk_ctrls = {
> [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
> [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
> index 2950245e7b3f5e38f3f501a7314bb97c66d05982..fbf50f279e6628cb0f92b0188e1fbdf156a899e2 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
> @@ -22,7 +22,6 @@ static const struct dpu_caps sm6125_dpu_caps = {
> static const struct dpu_mdp_cfg sm6125_mdp = {
> .name = "top_0",
> .base = 0x0, .len = 0x45c,
> - .features = 0,
> .clk_ctrls = {
> [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
> [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index d51f6c5cdf62f3c00829167172ef6fd61f069986..47d82b83ac5378cb0001b3ea6605dc0f98aec5ef 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -154,14 +154,12 @@ enum {
> * @id: enum identifying this block
> * @base: register base offset to mdss
> * @len: length of hardware block
> - * @features bit mask identifying sub-blocks/features
> */
> #define DPU_HW_BLK_INFO \
> char name[DPU_HW_BLK_NAME_LEN]; \
> u32 id; \
> u32 base; \
> - u32 len; \
> - unsigned long features
> + u32 len
>
> /**
> * struct dpu_scaler_blk: Scaler information
> @@ -376,7 +374,6 @@ struct dpu_clk_ctrl_reg {
> /* struct dpu_mdp_cfg : MDP TOP-BLK instance info
> * @id: index identifying this block
> * @base: register base offset to mdss
> - * @features bit mask identifying sub-blocks/features
> * @clk_ctrls clock control register definition
> */
> struct dpu_mdp_cfg {
> @@ -392,6 +389,7 @@ struct dpu_mdp_cfg {
> */
> struct dpu_ctl_cfg {
> DPU_HW_BLK_INFO;
> + unsigned long features;
> unsigned int intr_start;
> };
>
> @@ -407,6 +405,7 @@ struct dpu_ctl_cfg {
> */
> struct dpu_sspp_cfg {
> DPU_HW_BLK_INFO;
> + unsigned long features;
> const struct dpu_sspp_sub_blks *sblk;
> u32 xin_id;
> enum dpu_clk_ctrl_type clk_ctrl;
> @@ -424,6 +423,7 @@ struct dpu_sspp_cfg {
> */
> struct dpu_lm_cfg {
> DPU_HW_BLK_INFO;
> + unsigned long features;
> const struct dpu_lm_sub_blks *sblk;
> u32 pingpong;
> u32 dspp;
> @@ -434,7 +434,6 @@ struct dpu_lm_cfg {
> * struct dpu_dspp_cfg - information of DSPP blocks
> * @id enum identifying this block
> * @base register offset of this block
> - * @features bit mask identifying sub-blocks/features
> * supported by this block
> * @sblk sub-blocks information
> */
> @@ -447,7 +446,6 @@ struct dpu_dspp_cfg {
> * struct dpu_pingpong_cfg - information of PING-PONG blocks
> * @id enum identifying this block
> * @base register offset of this block
> - * @features bit mask identifying sub-blocks/features
> * @intr_done: index for PINGPONG done interrupt
> * @intr_rdptr: index for PINGPONG readpointer done interrupt
> * @sblk sub-blocks information
> @@ -464,8 +462,6 @@ struct dpu_pingpong_cfg {
> * struct dpu_merge_3d_cfg - information of DSPP blocks
> * @id enum identifying this block
> * @base register offset of this block
> - * @features bit mask identifying sub-blocks/features
> - * supported by this block
> * @sblk sub-blocks information
> */
> struct dpu_merge_3d_cfg {
> @@ -483,6 +479,7 @@ struct dpu_merge_3d_cfg {
> */
> struct dpu_dsc_cfg {
> DPU_HW_BLK_INFO;
> + unsigned long features;
> const struct dpu_dsc_sub_blks *sblk;
> };
>
> @@ -490,7 +487,6 @@ struct dpu_dsc_cfg {
> * struct dpu_intf_cfg - information of timing engine blocks
> * @id enum identifying this block
> * @base register offset of this block
> - * @features bit mask identifying sub-blocks/features
> * @type: Interface type(DSI, DP, HDMI)
> * @controller_id: Controller Instance ID in case of multiple of intf type
> * @prog_fetch_lines_worst_case Worst case latency num lines needed to prefetch
> @@ -521,6 +517,7 @@ struct dpu_intf_cfg {
> */
> struct dpu_wb_cfg {
> DPU_HW_BLK_INFO;
> + unsigned long features;
> u8 vbif_idx;
> u32 maxlinewidth;
> u32 xin_id;
> @@ -589,6 +586,7 @@ struct dpu_vbif_qos_tbl {
> */
> struct dpu_vbif_cfg {
> DPU_HW_BLK_INFO;
> + unsigned long features;
> u32 default_ot_rd_limit;
> u32 default_ot_wr_limit;
> u32 xin_halt_timeout;
> @@ -606,7 +604,6 @@ struct dpu_vbif_cfg {
> * @name string name for debug purposes
> * @id enum identifying this block
> * @base register offset of this block
> - * @features bit mask identifying sub-blocks/features
> */
> struct dpu_cdm_cfg {
> DPU_HW_BLK_INFO;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c
> index b9c433567262a954b7f02233f6670ee6a8476846..b3395e9c34a19363019ec0ccfb0c87943553b4c9 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c
> @@ -360,8 +360,7 @@ static void dpu_hw_dsc_bind_pingpong_blk_1_2(struct dpu_hw_dsc *hw_dsc,
> DPU_REG_WRITE(hw, sblk->ctl.base + DSC_CTL, mux_cfg);
> }
>
> -static void _setup_dcs_ops_1_2(struct dpu_hw_dsc_ops *ops,
> - const unsigned long features)
> +static void _setup_dcs_ops_1_2(struct dpu_hw_dsc_ops *ops)
> {
> ops->dsc_disable = dpu_hw_dsc_disable_1_2;
> ops->dsc_config = dpu_hw_dsc_config_1_2;
> @@ -391,7 +390,7 @@ struct dpu_hw_dsc *dpu_hw_dsc_init_1_2(struct drm_device *dev,
>
> c->idx = cfg->id;
> c->caps = cfg;
> - _setup_dcs_ops_1_2(&c->ops, c->caps->features);
> + _setup_dcs_ops_1_2(&c->ops);
>
> return c;
> }
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c
> index 0b3325f9c8705999e1003e5c88872562e880229b..83b1dbecddd2b30402f47155fa2f9a148ead02c1 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c
> @@ -33,8 +33,7 @@ static void dpu_hw_merge_3d_setup_3d_mode(struct dpu_hw_merge_3d *merge_3d,
> }
> }
>
> -static void _setup_merge_3d_ops(struct dpu_hw_merge_3d *c,
> - unsigned long features)
> +static void _setup_merge_3d_ops(struct dpu_hw_merge_3d *c)
> {
> c->ops.setup_3d_mode = dpu_hw_merge_3d_setup_3d_mode;
> };
> @@ -62,7 +61,7 @@ struct dpu_hw_merge_3d *dpu_hw_merge_3d_init(struct drm_device *dev,
>
> c->idx = cfg->id;
> c->caps = cfg;
> - _setup_merge_3d_ops(c, c->caps->features);
> + _setup_merge_3d_ops(c);
>
> return c;
> }
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
> index 5c811f0142d5e2a012d7e9b3a918818f22ec11cf..96dc10589bee6cf144eabaecf9f8ec5777431ac3 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
> @@ -264,7 +264,7 @@ static void dpu_hw_dp_phy_intf_sel(struct dpu_hw_mdp *mdp,
> }
>
> static void _setup_mdp_ops(struct dpu_hw_mdp_ops *ops,
> - unsigned long cap, const struct dpu_mdss_version *mdss_rev)
> + const struct dpu_mdss_version *mdss_rev)
> {
> ops->setup_split_pipe = dpu_hw_setup_split_pipe;
> ops->setup_clk_force_ctrl = dpu_hw_setup_clk_force_ctrl;
> @@ -313,7 +313,7 @@ struct dpu_hw_mdp *dpu_hw_mdptop_init(struct drm_device *dev,
> * Assign ops
> */
> mdp->caps = cfg;
> - _setup_mdp_ops(&mdp->ops, mdp->caps->features, mdss_rev);
> + _setup_mdp_ops(&mdp->ops, mdss_rev);
>
> return mdp;
> }
>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
^ permalink raw reply [flat|nested] 64+ messages in thread