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Mon, 14 Apr 2025 12:27:30 +0200 (CEST) Message-ID: Date: Mon, 14 Apr 2025 12:27:30 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC 5/5] arm64: dts: mediatek: mt7988: Add xsphy for ssusb0/pcie2 To: Frank Wunderlich , Chunfeng Yun , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger Cc: Frank Wunderlich , Daniel Golle , Sam Shih , MandyJH Liu , linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250413085806.8544-1-linux@fw-web.de> <20250413085806.8544-6-linux@fw-web.de> From: AngeloGioacchino Del Regno Content-Language: en-US In-Reply-To: <20250413085806.8544-6-linux@fw-web.de> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Il 13/04/25 10:58, Frank Wunderlich ha scritto: > From: Frank Wunderlich > > First usb and third pcie controller on mt7988 need a xs-phy to work > properly. > > Signed-off-by: Frank Wunderlich > --- > arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 39 +++++++++++++++++++++++ > 1 file changed, 39 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi > index 88b56a24efca..10525d977007 100644 > --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi > @@ -334,6 +334,8 @@ usb@11190000 { > <&infracfg CLK_INFRA_133M_USB_HCK>, > <&infracfg CLK_INFRA_USB_XHCI>; > clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; > + phys = <&xphyu2port0 PHY_TYPE_USB2>, > + <&xphyu3port0 PHY_TYPE_USB3>; > status = "disabled"; > }; > > @@ -398,6 +400,9 @@ pcie2: pcie@11280000 { > pinctrl-0 = <&pcie2_pins>; > status = "disabled"; > > + phys = <&xphyu3port0 PHY_TYPE_PCIE>; > + phy-names = "pcie-phy"; > + > #interrupt-cells = <1>; > interrupt-map-mask = <0 0 0 0x7>; > interrupt-map = <0 0 0 1 &pcie_intc2 0>, > @@ -548,6 +553,40 @@ tphyu3port0: usb-phy@11c50700 { > }; > }; > > + topmisc: power-controller@11d10000 { > + compatible = "mediatek,mt7988-topmisc", "syscon", > + "mediatek,mt7988-power-controller"; > + reg = <0 0x11d10000 0 0x10000>; > + #clock-cells = <1>; > + #power-domain-cells = <1>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + xs-phy@11e10000 { That shall be just "phy@addr" > + compatible = "mediatek,mt7988-xsphy", > + "mediatek,xsphy"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + status = "disabled"; > + > + xphyu2port0: usb-phy@11e10000 { Perhaps just u2port0/u3port0 like done on the other MediaTek SoC DTs is better for consistency :-) Cheers! > + reg = <0 0x11e10000 0 0x400>; > + clocks = <&infracfg CLK_INFRA_USB_UTMI>; > + clock-names = "ref"; > + #phy-cells = <1>; > + }; > + > + xphyu3port0: usb-phy@11e13000 { > + reg = <0 0x11e13400 0 0x500>; > + clocks = <&infracfg CLK_INFRA_USB_PIPE>; > + clock-names = "ref"; > + #phy-cells = <1>; > + mediatek,syscon-type = <&topmisc 0x218 0>; > + }; > + }; > + > clock-controller@11f40000 { > compatible = "mediatek,mt7988-xfi-pll"; > reg = <0 0x11f40000 0 0x1000>;