From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 269F81D89F1; Tue, 26 Nov 2024 15:57:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732636672; cv=none; b=ZEMiLMWmPmVcsDQDOcmNyqRkAWm325+vHfRN3SwID0FFTH+chvgGEk0jrtO/w1gs8IjvN4golOz7kkc1LnN9XtTqOOoForQTU8g5tU9ltuxU12dslNapmVhuYhaPh0VgiUqUiZYXAOV5k+JQBe2eHXJq4Xv/n2bjmMsDzV4LP5o= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732636672; c=relaxed/simple; bh=ZcRRe+aPriZPzBE2pe1SDdmVBe9BC1ro/wbA3TDf3dw=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=QtinqQrwcUjBGsKu+REaCrDdz/oZxiUyYKkDm5GynJzDiS7MMAXmeqYs3NLUqamaW8pnCzy7tNOUBgY8OzxLIo+ScuLji7pqvfQECVQOkrBqOb0XrKRqmIyqCrCnc4la9V1JQ9CABNkcLy530Ms9ZXpb0ETfxCKovafX3gkvn6I= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=KiEpM04z; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="KiEpM04z" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D1906C4CECF; Tue, 26 Nov 2024 15:57:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1732636671; bh=ZcRRe+aPriZPzBE2pe1SDdmVBe9BC1ro/wbA3TDf3dw=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=KiEpM04zndVgqXbKC6cHK7B25Wl/3glFJwedSDv8TtNgW051VomjEa/HcmIi5S+cz 1UCvOs72EYUhITwbBTTy19o6jS+13VKy19Hdr0sdXWVTJaI5wplvz0Qndg5A1x3DS3 xCRBfojeoj199cI5aRSccrB1LVMLVR+QN8Fo/CtmhTfpnS0Je8Z+oD4Ml/KFDodm+o SdfmuSjHc+VMce3qYVAvtmqPmEnlrHRPsmvWdmszWqF+gq2k6s5pdKlarifX6BgtR5 oQFVd10XjYlt9b1vId/df0+GTnZK7WOEQYSL8lVjXt0sp3HbLPDWQGIgFICRVkYx5R vrNfAbIW24dXQ== Message-ID: Date: Tue, 26 Nov 2024 16:57:43 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/3] dt-bindings: display/msm: gpu: Document A612 GPU To: Akhil P Oommen , Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20241126-qcs615-gpu-dt-v1-0-a87782976dad@quicinc.com> <20241126-qcs615-gpu-dt-v1-1-a87782976dad@quicinc.com> <680a9f92-1d29-410b-bc63-a998d2d64e9e@kernel.org> <56b6f58e-e100-4dfd-b764-a9c3f5aad887@quicinc.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 26/11/2024 16:24, Akhil P Oommen wrote: >> No, this makes everything total mess. Why xo now is allowed to be first >> clock? >> >> Drop and explain in commit msg why other devices now get smmu clock. > > I thought it was okay to make this list a bit flexible. Btw, the other > existing clock-names list for a5x and older gpus uses "anyOf". > > I suppose the suggestion is to add a separate clock-names list for A612 > with strict ordering. Is that correct? Yes Best regards, Krzysztof