* [PATCH 1/3] dt-bindings: display/msm: gpu: Document A612 GPU
2024-11-26 14:06 [PATCH 0/3] Devicetree changes for QCS615's GPU Akhil P Oommen
@ 2024-11-26 14:06 ` Akhil P Oommen
2024-11-26 14:12 ` Krzysztof Kozlowski
2024-11-26 14:32 ` Akhil P Oommen
2024-11-26 14:06 ` [PATCH 2/3] arm64: dts: qcom: qcs615: Add gpu and gmu nodes Akhil P Oommen
2024-11-26 14:06 ` [PATCH 3/3] arm64: dts: qcom: qcs615-ride: Enable Adreno 612 GPU Akhil P Oommen
2 siblings, 2 replies; 12+ messages in thread
From: Akhil P Oommen @ 2024-11-26 14:06 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Konrad Dybcio, Abhinav Kumar,
Dmitry Baryshkov, Marijn Suijten, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, David Airlie, Simona Vetter,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
Akhil P Oommen
A612 GPU requires an additional smmu_vote clock. Update the bindings to
reflect this.
Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
---
.../devicetree/bindings/display/msm/gpu.yaml | 28 ++++++++++++----------
1 file changed, 16 insertions(+), 12 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml
index 6ddc72fd85b04537ea270754a897b4e7eb269641..201150d3151b55c26c95832d36f4e02f66060a25 100644
--- a/Documentation/devicetree/bindings/display/msm/gpu.yaml
+++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml
@@ -187,6 +187,7 @@ allOf:
enum:
- qcom,adreno-610.0
- qcom,adreno-619.1
+ - qcom,adreno-612.0
then:
properties:
clocks:
@@ -195,18 +196,21 @@ allOf:
clock-names:
items:
- - const: core
- description: GPU Core clock
- - const: iface
- description: GPU Interface clock
- - const: mem_iface
- description: GPU Memory Interface clock
- - const: alt_mem_iface
- description: GPU Alternative Memory Interface clock
- - const: gmu
- description: CX GMU clock
- - const: xo
- description: GPUCC clocksource clock
+ anyOf:
+ - const: core
+ description: GPU Core clock
+ - const: iface
+ description: GPU Interface clock
+ - const: mem_iface
+ description: GPU Memory Interface clock
+ - const: alt_mem_iface
+ description: GPU Alternative Memory Interface clock
+ - const: gmu
+ description: CX GMU clock
+ - const: xo
+ description: GPUCC clocksource clock
+ - const: smmu_vote
+ description: GPUCC clocksource clock
reg-names:
minItems: 1
--
2.45.2
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH 1/3] dt-bindings: display/msm: gpu: Document A612 GPU
2024-11-26 14:06 ` [PATCH 1/3] dt-bindings: display/msm: gpu: Document A612 GPU Akhil P Oommen
@ 2024-11-26 14:12 ` Krzysztof Kozlowski
2024-11-26 15:24 ` Akhil P Oommen
2024-11-26 14:32 ` Akhil P Oommen
1 sibling, 1 reply; 12+ messages in thread
From: Krzysztof Kozlowski @ 2024-11-26 14:12 UTC (permalink / raw)
To: Akhil P Oommen, Rob Clark, Sean Paul, Konrad Dybcio,
Abhinav Kumar, Dmitry Baryshkov, Marijn Suijten,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel
On 26/11/2024 15:06, Akhil P Oommen wrote:
> A612 GPU requires an additional smmu_vote clock. Update the bindings to
> reflect this.
>
> Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
> ---
> .../devicetree/bindings/display/msm/gpu.yaml | 28 ++++++++++++----------
> 1 file changed, 16 insertions(+), 12 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml
> index 6ddc72fd85b04537ea270754a897b4e7eb269641..201150d3151b55c26c95832d36f4e02f66060a25 100644
> --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml
> +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml
> @@ -187,6 +187,7 @@ allOf:
> enum:
> - qcom,adreno-610.0
> - qcom,adreno-619.1
> + - qcom,adreno-612.0
Keep things ordered.
> then:
> properties:
> clocks:
> @@ -195,18 +196,21 @@ allOf:
>
> clock-names:
> items:
> - - const: core
> - description: GPU Core clock
> - - const: iface
> - description: GPU Interface clock
> - - const: mem_iface
> - description: GPU Memory Interface clock
> - - const: alt_mem_iface
> - description: GPU Alternative Memory Interface clock
> - - const: gmu
> - description: CX GMU clock
> - - const: xo
> - description: GPUCC clocksource clock
> + anyOf:
No, this makes everything total mess. Why xo now is allowed to be first
clock?
Drop and explain in commit msg why other devices now get smmu clock.
BTW, I am pretty sure this breaks existing platforms.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/3] dt-bindings: display/msm: gpu: Document A612 GPU
2024-11-26 14:12 ` Krzysztof Kozlowski
@ 2024-11-26 15:24 ` Akhil P Oommen
2024-11-26 15:57 ` Krzysztof Kozlowski
0 siblings, 1 reply; 12+ messages in thread
From: Akhil P Oommen @ 2024-11-26 15:24 UTC (permalink / raw)
To: Krzysztof Kozlowski, Rob Clark, Sean Paul, Konrad Dybcio,
Abhinav Kumar, Dmitry Baryshkov, Marijn Suijten,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel
On 11/26/2024 7:42 PM, Krzysztof Kozlowski wrote:
> On 26/11/2024 15:06, Akhil P Oommen wrote:
>> A612 GPU requires an additional smmu_vote clock. Update the bindings to
>> reflect this.
>>
>> Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
>> ---
>> .../devicetree/bindings/display/msm/gpu.yaml | 28 ++++++++++++----------
>> 1 file changed, 16 insertions(+), 12 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml
>> index 6ddc72fd85b04537ea270754a897b4e7eb269641..201150d3151b55c26c95832d36f4e02f66060a25 100644
>> --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml
>> +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml
>> @@ -187,6 +187,7 @@ allOf:
>> enum:
>> - qcom,adreno-610.0
>> - qcom,adreno-619.1
>> + - qcom,adreno-612.0
>
> Keep things ordered.
Ack.
>
>> then:
>> properties:
>> clocks:
>> @@ -195,18 +196,21 @@ allOf:
>>
>> clock-names:
>> items:
>> - - const: core
>> - description: GPU Core clock
>> - - const: iface
>> - description: GPU Interface clock
>> - - const: mem_iface
>> - description: GPU Memory Interface clock
>> - - const: alt_mem_iface
>> - description: GPU Alternative Memory Interface clock
>> - - const: gmu
>> - description: CX GMU clock
>> - - const: xo
>> - description: GPUCC clocksource clock
>> + anyOf:
>
> No, this makes everything total mess. Why xo now is allowed to be first
> clock?
>
> Drop and explain in commit msg why other devices now get smmu clock.
I thought it was okay to make this list a bit flexible. Btw, the other
existing clock-names list for a5x and older gpus uses "anyOf".
I suppose the suggestion is to add a separate clock-names list for A612
with strict ordering. Is that correct?
-Akhil
>
> BTW, I am pretty sure this breaks existing platforms.
>
> Best regards,
> Krzysztof
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/3] dt-bindings: display/msm: gpu: Document A612 GPU
2024-11-26 15:24 ` Akhil P Oommen
@ 2024-11-26 15:57 ` Krzysztof Kozlowski
0 siblings, 0 replies; 12+ messages in thread
From: Krzysztof Kozlowski @ 2024-11-26 15:57 UTC (permalink / raw)
To: Akhil P Oommen, Rob Clark, Sean Paul, Konrad Dybcio,
Abhinav Kumar, Dmitry Baryshkov, Marijn Suijten,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel
On 26/11/2024 16:24, Akhil P Oommen wrote:
>> No, this makes everything total mess. Why xo now is allowed to be first
>> clock?
>>
>> Drop and explain in commit msg why other devices now get smmu clock.
>
> I thought it was okay to make this list a bit flexible. Btw, the other
> existing clock-names list for a5x and older gpus uses "anyOf".
>
> I suppose the suggestion is to add a separate clock-names list for A612
> with strict ordering. Is that correct?
Yes
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/3] dt-bindings: display/msm: gpu: Document A612 GPU
2024-11-26 14:06 ` [PATCH 1/3] dt-bindings: display/msm: gpu: Document A612 GPU Akhil P Oommen
2024-11-26 14:12 ` Krzysztof Kozlowski
@ 2024-11-26 14:32 ` Akhil P Oommen
1 sibling, 0 replies; 12+ messages in thread
From: Akhil P Oommen @ 2024-11-26 14:32 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Konrad Dybcio, Abhinav Kumar,
Dmitry Baryshkov, Marijn Suijten, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, David Airlie, Simona Vetter,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel
On 11/26/2024 7:36 PM, Akhil P Oommen wrote:
> A612 GPU requires an additional smmu_vote clock. Update the bindings to
> reflect this.
>
> Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
> ---
> .../devicetree/bindings/display/msm/gpu.yaml | 28 ++++++++++++----------
> 1 file changed, 16 insertions(+), 12 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml
> index 6ddc72fd85b04537ea270754a897b4e7eb269641..201150d3151b55c26c95832d36f4e02f66060a25 100644
> --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml
> +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml
> @@ -187,6 +187,7 @@ allOf:
> enum:
> - qcom,adreno-610.0
> - qcom,adreno-619.1
> + - qcom,adreno-612.0
> then:
> properties:
> clocks:
> @@ -195,18 +196,21 @@ allOf:
>
> clock-names:
> items:
> - - const: core
> - description: GPU Core clock
> - - const: iface
> - description: GPU Interface clock
> - - const: mem_iface
> - description: GPU Memory Interface clock
> - - const: alt_mem_iface
> - description: GPU Alternative Memory Interface clock
> - - const: gmu
> - description: CX GMU clock
> - - const: xo
> - description: GPUCC clocksource clock
> + anyOf:
> + - const: core
> + description: GPU Core clock
> + - const: iface
> + description: GPU Interface clock
> + - const: mem_iface
> + description: GPU Memory Interface clock
> + - const: alt_mem_iface
> + description: GPU Alternative Memory Interface clock
> + - const: gmu
> + description: CX GMU clock
> + - const: xo
> + description: GPUCC clocksource clock
> + - const: smmu_vote
> + description: GPUCC clocksource clock
Forgot to update the description. will fix.
-Akhil
>
> reg-names:
> minItems: 1
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 2/3] arm64: dts: qcom: qcs615: Add gpu and gmu nodes
2024-11-26 14:06 [PATCH 0/3] Devicetree changes for QCS615's GPU Akhil P Oommen
2024-11-26 14:06 ` [PATCH 1/3] dt-bindings: display/msm: gpu: Document A612 GPU Akhil P Oommen
@ 2024-11-26 14:06 ` Akhil P Oommen
2024-11-26 14:22 ` Dmitry Baryshkov
2024-12-05 19:46 ` Konrad Dybcio
2024-11-26 14:06 ` [PATCH 3/3] arm64: dts: qcom: qcs615-ride: Enable Adreno 612 GPU Akhil P Oommen
2 siblings, 2 replies; 12+ messages in thread
From: Akhil P Oommen @ 2024-11-26 14:06 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Konrad Dybcio, Abhinav Kumar,
Dmitry Baryshkov, Marijn Suijten, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, David Airlie, Simona Vetter,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
Akhil P Oommen, Jie Zhang
From: Jie Zhang <quic_jiezh@quicinc.com>
Add gpu and gmu nodes for qcs615 chipset.
Signed-off-by: Jie Zhang <quic_jiezh@quicinc.com>
Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
---
arch/arm64/boot/dts/qcom/qcs615.dtsi | 86 ++++++++++++++++++++++++++++++++++++
1 file changed, 86 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
index 8df26efde3fd6c0f85b9bcddb461fae33687dc75..f6a3fbbda962f01d6cf2d5c156ea1d1d846f310a 100644
--- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
@@ -387,6 +387,11 @@ smem_region: smem@86000000 {
no-map;
hwlocks = <&tcsr_mutex 3>;
};
+
+ pil_gpu_mem: pil-gpu@97715000 {
+ reg = <0x0 0x97715000 0x0 0x2000>;
+ no-map;
+ };
};
soc: soc@0 {
@@ -508,6 +513,87 @@ qup_uart0_rx: qup-uart0-rx-state {
};
};
+ gpu: gpu@5000000 {
+ compatible = "qcom,adreno-612.0", "qcom,adreno";
+ reg = <0x0 0x05000000 0x0 0x90000>;
+ reg-names = "kgsl_3d0_reg_memory";
+
+ clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>,
+ <&gcc GCC_DDRSS_GPU_AXI_CLK>,
+ <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gpucc GPU_CC_CX_GMU_CLK>,
+ <&gpucc GPU_CC_CXO_CLK>,
+ <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
+ clock-names = "core",
+ "mem_iface",
+ "alt_mem_iface",
+ "gmu",
+ "xo",
+ "smmu_vote";
+
+ interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+
+ interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "gfx-mem";
+
+ iommus = <&adreno_smmu 0x0 0x401>;
+ operating-points-v2 = <&gpu_opp_table>;
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ qcom,gmu = <&gmu_wrapper>;
+
+ #cooling-cells = <2>;
+
+ status = "disabled";
+
+ gpu_zap_shader: zap-shader {
+ memory-region = <&pil_gpu_mem>;
+ };
+
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-435000000 {
+ opp-hz = /bits/ 64 <435000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ opp-peak-kBps = <3000000>;
+ };
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ opp-peak-kBps = <3975000>;
+ };
+
+ opp-650000000 {
+ opp-hz = /bits/ 64 <650000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ opp-peak-kBps = <5287500>;
+ };
+
+ opp-745000000 {
+ opp-hz = /bits/ 64 <745000000>;
+ required-opps = <&rpmhpd_opp_nom_l1>;
+ opp-peak-kBps = <6075000>;
+ };
+
+ opp-845000000 {
+ opp-hz = /bits/ 64 <845000000>;
+ required-opps = <&rpmhpd_opp_turbo>;
+ opp-peak-kBps = <7050000>;
+ };
+ };
+ };
+
+ gmu_wrapper: gmu@506a000 {
+ compatible = "qcom,adreno-gmu-wrapper";
+ reg = <0x0 0x0506a000 0x0 0x34000>;
+ reg-names = "gmu";
+ power-domains = <&gpucc CX_GDSC>,
+ <&gpucc GX_GDSC>;
+ power-domain-names = "cx", "gx";
+ };
+
gpucc: clock-controller@5090000 {
compatible = "qcom,qcs615-gpucc";
reg = <0 0x5090000 0 0x9000>;
--
2.45.2
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH 2/3] arm64: dts: qcom: qcs615: Add gpu and gmu nodes
2024-11-26 14:06 ` [PATCH 2/3] arm64: dts: qcom: qcs615: Add gpu and gmu nodes Akhil P Oommen
@ 2024-11-26 14:22 ` Dmitry Baryshkov
2024-12-05 19:46 ` Konrad Dybcio
1 sibling, 0 replies; 12+ messages in thread
From: Dmitry Baryshkov @ 2024-11-26 14:22 UTC (permalink / raw)
To: Akhil P Oommen
Cc: Rob Clark, Sean Paul, Konrad Dybcio, Abhinav Kumar,
Marijn Suijten, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, linux-arm-msm,
dri-devel, freedreno, devicetree, linux-kernel, Jie Zhang
On Tue, Nov 26, 2024 at 07:36:48PM +0530, Akhil P Oommen wrote:
> From: Jie Zhang <quic_jiezh@quicinc.com>
>
> Add gpu and gmu nodes for qcs615 chipset.
>
> Signed-off-by: Jie Zhang <quic_jiezh@quicinc.com>
> Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/qcs615.dtsi | 86 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 86 insertions(+)
>
Clocks might need changing to follow the schema changes. Otherwise:
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 2/3] arm64: dts: qcom: qcs615: Add gpu and gmu nodes
2024-11-26 14:06 ` [PATCH 2/3] arm64: dts: qcom: qcs615: Add gpu and gmu nodes Akhil P Oommen
2024-11-26 14:22 ` Dmitry Baryshkov
@ 2024-12-05 19:46 ` Konrad Dybcio
2024-12-11 20:30 ` Akhil P Oommen
1 sibling, 1 reply; 12+ messages in thread
From: Konrad Dybcio @ 2024-12-05 19:46 UTC (permalink / raw)
To: Akhil P Oommen, Rob Clark, Sean Paul, Konrad Dybcio,
Abhinav Kumar, Dmitry Baryshkov, Marijn Suijten,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
Jie Zhang
On 26.11.2024 3:06 PM, Akhil P Oommen wrote:
> From: Jie Zhang <quic_jiezh@quicinc.com>
>
> Add gpu and gmu nodes for qcs615 chipset.
>
> Signed-off-by: Jie Zhang <quic_jiezh@quicinc.com>
> Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/qcs615.dtsi | 86 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 86 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> index 8df26efde3fd6c0f85b9bcddb461fae33687dc75..f6a3fbbda962f01d6cf2d5c156ea1d1d846f310a 100644
> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> @@ -387,6 +387,11 @@ smem_region: smem@86000000 {
> no-map;
> hwlocks = <&tcsr_mutex 3>;
> };
> +
> + pil_gpu_mem: pil-gpu@97715000 {
> + reg = <0x0 0x97715000 0x0 0x2000>;
> + no-map;
> + };
> };
>
> soc: soc@0 {
> @@ -508,6 +513,87 @@ qup_uart0_rx: qup-uart0-rx-state {
> };
> };
>
> + gpu: gpu@5000000 {
> + compatible = "qcom,adreno-612.0", "qcom,adreno";
> + reg = <0x0 0x05000000 0x0 0x90000>;
> + reg-names = "kgsl_3d0_reg_memory";
> +
> + clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>,
> + <&gcc GCC_DDRSS_GPU_AXI_CLK>,
> + <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
> + <&gpucc GPU_CC_CX_GMU_CLK>,
> + <&gpucc GPU_CC_CXO_CLK>,
> + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
This one belongs under the adreno_smmu node
Konrad
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH 2/3] arm64: dts: qcom: qcs615: Add gpu and gmu nodes
2024-12-05 19:46 ` Konrad Dybcio
@ 2024-12-11 20:30 ` Akhil P Oommen
0 siblings, 0 replies; 12+ messages in thread
From: Akhil P Oommen @ 2024-12-11 20:30 UTC (permalink / raw)
To: Konrad Dybcio, Rob Clark, Sean Paul, Konrad Dybcio, Abhinav Kumar,
Dmitry Baryshkov, Marijn Suijten, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, David Airlie, Simona Vetter,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
Jie Zhang
On 12/6/2024 1:16 AM, Konrad Dybcio wrote:
> On 26.11.2024 3:06 PM, Akhil P Oommen wrote:
>> From: Jie Zhang <quic_jiezh@quicinc.com>
>>
>> Add gpu and gmu nodes for qcs615 chipset.
>>
>> Signed-off-by: Jie Zhang <quic_jiezh@quicinc.com>
>> Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
>> ---
>> arch/arm64/boot/dts/qcom/qcs615.dtsi | 86 ++++++++++++++++++++++++++++++++++++
>> 1 file changed, 86 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
>> index 8df26efde3fd6c0f85b9bcddb461fae33687dc75..f6a3fbbda962f01d6cf2d5c156ea1d1d846f310a 100644
>> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
>> @@ -387,6 +387,11 @@ smem_region: smem@86000000 {
>> no-map;
>> hwlocks = <&tcsr_mutex 3>;
>> };
>> +
>> + pil_gpu_mem: pil-gpu@97715000 {
>> + reg = <0x0 0x97715000 0x0 0x2000>;
>> + no-map;
>> + };
>> };
>>
>> soc: soc@0 {
>> @@ -508,6 +513,87 @@ qup_uart0_rx: qup-uart0-rx-state {
>> };
>> };
>>
>> + gpu: gpu@5000000 {
>> + compatible = "qcom,adreno-612.0", "qcom,adreno";
>> + reg = <0x0 0x05000000 0x0 0x90000>;
>> + reg-names = "kgsl_3d0_reg_memory";
>> +
>> + clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>,
>> + <&gcc GCC_DDRSS_GPU_AXI_CLK>,
>> + <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
>> + <&gpucc GPU_CC_CX_GMU_CLK>,
>> + <&gpucc GPU_CC_CXO_CLK>,
>> + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
>
> This one belongs under the adreno_smmu node
Yeah, right. Unlike downstream, smmu is a supplier of gpu here.
-Akhil
>
> Konrad
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 3/3] arm64: dts: qcom: qcs615-ride: Enable Adreno 612 GPU
2024-11-26 14:06 [PATCH 0/3] Devicetree changes for QCS615's GPU Akhil P Oommen
2024-11-26 14:06 ` [PATCH 1/3] dt-bindings: display/msm: gpu: Document A612 GPU Akhil P Oommen
2024-11-26 14:06 ` [PATCH 2/3] arm64: dts: qcom: qcs615: Add gpu and gmu nodes Akhil P Oommen
@ 2024-11-26 14:06 ` Akhil P Oommen
2024-11-26 14:21 ` Dmitry Baryshkov
2 siblings, 1 reply; 12+ messages in thread
From: Akhil P Oommen @ 2024-11-26 14:06 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Konrad Dybcio, Abhinav Kumar,
Dmitry Baryshkov, Marijn Suijten, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, David Airlie, Simona Vetter,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
Akhil P Oommen, Jie Zhang
From: Jie Zhang <quic_jiezh@quicinc.com>
Enable GPU for qcs615-ride platform and provide path for zap
shader.
Signed-off-by: Jie Zhang <quic_jiezh@quicinc.com>
Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
---
arch/arm64/boot/dts/qcom/qcs615-ride.dts | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
index ee6cab3924a6d71f29934a8debba3a832882abdd..860a0db1908cfe32a250b14aac14065923c5a575 100644
--- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts
+++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
@@ -202,6 +202,14 @@ &gcc {
<&sleep_clk>;
};
+&gpu {
+ status = "okay";
+};
+
+&gpu_zap_shader {
+ firmware-name = "qcom/qcs615/a612_zap.mbn";
+};
+
&qupv3_id_0 {
status = "okay";
};
--
2.45.2
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH 3/3] arm64: dts: qcom: qcs615-ride: Enable Adreno 612 GPU
2024-11-26 14:06 ` [PATCH 3/3] arm64: dts: qcom: qcs615-ride: Enable Adreno 612 GPU Akhil P Oommen
@ 2024-11-26 14:21 ` Dmitry Baryshkov
0 siblings, 0 replies; 12+ messages in thread
From: Dmitry Baryshkov @ 2024-11-26 14:21 UTC (permalink / raw)
To: Akhil P Oommen
Cc: Rob Clark, Sean Paul, Konrad Dybcio, Abhinav Kumar,
Marijn Suijten, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, linux-arm-msm,
dri-devel, freedreno, devicetree, linux-kernel, Jie Zhang
On Tue, Nov 26, 2024 at 07:36:49PM +0530, Akhil P Oommen wrote:
> From: Jie Zhang <quic_jiezh@quicinc.com>
>
> Enable GPU for qcs615-ride platform and provide path for zap
> shader.
>
> Signed-off-by: Jie Zhang <quic_jiezh@quicinc.com>
> Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/qcs615-ride.dts | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 12+ messages in thread