RE: [PATCH v2 2/3] cxl/edac: Fix wrong dpa checking for PPR operation

[Shiju Jose <shiju.jose@huawei.com>]

>-----Original Message-----
>From: Li Ming <ming.li@zohomail.com>
>Sent: 02 July 2025 08:20
>To: akpm@linux-foundation.org; andriy.shevchenko@linux.intel.com;
>bhelgaas@google.com; ilpo.jarvinen@linux.intel.com; dave@stgolabs.net;
>Jonathan Cameron <jonathan.cameron@huawei.com>; dave.jiang@intel.com;
>alison.schofield@intel.com; vishal.l.verma@intel.com; ira.weiny@intel.com;
>dan.j.williams@intel.com; Shiju Jose <shiju.jose@huawei.com>
>Cc: linux-cxl@vger.kernel.org; linux-kernel@vger.kernel.org; Li Ming
><ming.li@zohomail.com>
>Subject: [PATCH v2 2/3] cxl/edac: Fix wrong dpa checking for PPR operation
>
>DPA 0 is considered invalid in cxl_do_ppr(), but per Table 8-143. "Get Partition
>Info Output Payload" in CXL r3.2 section 8.2.10.9.2.1 "Get Partition Info(Opcode
>4100h)", it mentions that DPA 0 is a valid address of a CXL device. So the correct
>implementation should be checking if the DPA is in the DPA range of the CXL
>device rather than checking if the DPA is equal to 0.
>
>Fixes: be9b359e056a ("cxl/edac: Add CXL memory device soft PPR control
>feature")
>Signed-off-by: Li Ming <ming.li@zohomail.com>
Hi Ming,
Thanks for the fix. 

Just found that, along with Table 8-143,  CXL spec 3.2 Device Decode Logic (Page 576) describes as
"The DPA mappings for a device typically start at 'DPA 0' for Decoder[0] and 
are sequentially accumulated with each additional decoder used"

Tested-by: Shiju Jose <shiju.jose@huawei.com>
Reviewed-by: Shiju Jose <shiju.jose@huawei.com>
>---
> drivers/cxl/core/edac.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
>diff --git a/drivers/cxl/core/edac.c b/drivers/cxl/core/edac.c index
>623aaa4439c4..1cf65b1538b9 100644
>--- a/drivers/cxl/core/edac.c
>+++ b/drivers/cxl/core/edac.c
>@@ -1923,8 +1923,11 @@ static int cxl_ppr_set_nibble_mask(struct device
>*dev, void *drv_data,  static int cxl_do_ppr(struct device *dev, void *drv_data,
>u32 val)  {
> 	struct cxl_ppr_context *cxl_ppr_ctx = drv_data;
>+	struct cxl_memdev *cxlmd = cxl_ppr_ctx->cxlmd;
>+	struct cxl_dev_state *cxlds = cxlmd->cxlds;
>
>-	if (!cxl_ppr_ctx->dpa || val != EDAC_DO_MEM_REPAIR)
>+	if (!resource_contains_addr(&cxlds->dpa_res, cxl_ppr_ctx->dpa) ||
>+	    val != EDAC_DO_MEM_REPAIR)
> 		return -EINVAL;
>
> 	return cxl_mem_perform_ppr(cxl_ppr_ctx);
>--
>2.34.1


Thanks,
Shiju