From: David Laight <David.Laight@ACULAB.COM>
To: 'Dave Hansen' <dave.hansen@intel.com>,
Jiaxun Yang <jiaxun.yang@flygoat.com>,
"x86@kernel.org" <x86@kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, "bp@alien8.de" <bp@alien8.de>,
"dave.hansen@linux.intel.com" <dave.hansen@linux.intel.com>,
"hpa@zytor.com" <hpa@zytor.com>,
"chang.seok.bae@intel.com" <chang.seok.bae@intel.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: RE: [RFC PATCH 00/10] x86: Allocate AVX512 xstate ondemand
Date: Fri, 3 Dec 2021 09:20:01 +0000 [thread overview]
Message-ID: <e332573f03ec441d9b357c7cfb6852ba@AcuMS.aculab.com> (raw)
In-Reply-To: <d7be6ef4-f73e-923e-93b7-ef254bf347c0@intel.com>
From: Dave Hansen
> Sent: 03 December 2021 00:59
>
> On 12/2/21 4:45 PM, Jiaxun Yang wrote:
> > 在2021年12月3日十二月 上午12:40，Dave Hansen写道：
> >> On 12/2/21 4:36 PM, Jiaxun Yang wrote:
> >>> Also we are going to have heterogeneous processors that
> >>> only some cores support AVX512, it can be helpful when
> >>> dealing with such processors.
> >> Really? Which x86 vendor is doing that?
> > Clear lower two bits of MSR 0xAF on Alder Lake give me some suprise :-)
>
> I honestly don't know what you're talking about. Does poking that MSR
> allowing AVX512 instructions to be executed on cores where it was
> otherwise disabled? That's entertaining, but it's far from "supported"
> or even support*able* in Linux.
I can also imagine chips being tested and tested and marked
differently depending on what works.
So a part with faulty AVX512 will be marked as BIG+little with AVX512 disabled.
A part with working AVX512 will have the 'little' cpu disabled.
A lot of this is actually setup by the BIOS code.
Cheating will cause grief.
David
-
Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK
Registration No: 1397386 (Wales)
next prev parent reply other threads:[~2021-12-03 9:20 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-03 0:36 [RFC PATCH 00/10] x86: Allocate AVX512 xstate ondemand Jiaxun Yang
2021-12-03 0:36 ` [RFC PATCH 01/10] x86/fpu: Remove duplicated declaration of __fpu_state_size_dynamic Jiaxun Yang
2021-12-03 0:36 ` [RFC PATCH 02/10] x86/fpu: Split fpu_xfd_enabled from fpu_state_size_dynamic Jiaxun Yang
2021-12-03 0:36 ` [RFC PATCH 03/10] x86/fpu: Calculate xsave state addr on fly Jiaxun Yang
2021-12-03 0:36 ` [RFC PATCH 04/10] x86/fpu: Remove xstate_comp_offsets cache Jiaxun Yang
2021-12-03 0:36 ` [RFC PATCH 05/10] x86/fpu: Cache xstate_is_aligned Jiaxun Yang
2021-12-03 0:36 ` [RFC PATCH 06/10] x86/fpu/xcr: Return all enabled xfeature if CPU doesn't support Jiaxun Yang
2021-12-03 0:36 ` [RFC PATCH 07/10] x86/fpu: Rellocate fpstate on save_fpregs_to_fpstate Jiaxun Yang
2021-12-03 0:44 ` Dave Hansen
2021-12-03 11:39 ` Jiaxun Yang
2021-12-03 15:18 ` Dave Hansen
2021-12-03 15:51 ` Jiaxun Yang
2021-12-03 0:36 ` [RFC PATCH 08/10] x86/fpu: Don't keep state_size in perm struct Jiaxun Yang
2021-12-03 0:36 ` [RFC PATCH 09/10] x86/fpu: Split out XFEATURE_MASK_KERNEL_DYNAMIC Jiaxun Yang
2021-12-03 0:36 ` [RFC PATCH 10/10] x86/fpu: Mark AVX512 xfeatures as kernel dynamic Jiaxun Yang
2021-12-03 0:40 ` [RFC PATCH 00/10] x86: Allocate AVX512 xstate ondemand Dave Hansen
2021-12-03 0:45 ` Jiaxun Yang
2021-12-03 0:58 ` Dave Hansen
2021-12-03 9:20 ` David Laight [this message]
2021-12-03 11:42 ` Jiaxun Yang
2021-12-03 11:51 ` Borislav Petkov
2021-12-03 11:55 ` Jiaxun Yang
2021-12-04 11:55 ` Peter Zijlstra
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