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By invoking an Indirect Branch Prediction Barrier > (IBPB) on VMRUN, old indirect branch predictions are prevented > from influencing indirect branches within the guest. > > SNP guests may choose to enable IBPB-on-Entry by setting > SEV_FEATURES bit 21 (IbpbOnEntry). > > Host support for IBPB on Entry is indicated by CPUID > Fn8000_001F[IbpbOnEntry], bit 31. > > If supported, indicate support for IBPB on Entry in > sev_supported_vmsa_features bit 23 (IbpbOnEntry). > > For more info, refer to page 615, Section 15.36.17 "Side-Channel > Protection", AMD64 Architecture Programmer's Manual Volume 2: System > Programming Part 2, Pub. 24593 Rev. 3.42 - March 2024 (see Link). > > Link: https://bugzilla.kernel.org/attachment.cgi?id=306250 > Signed-off-by: Kim Phillips Reviewed-by: Tom Lendacky > --- > arch/x86/include/asm/cpufeatures.h | 1 + > arch/x86/include/asm/svm.h | 1 + > arch/x86/kvm/svm/sev.c | 9 ++++++++- > 3 files changed, 10 insertions(+), 1 deletion(-) > > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h > index c01fdde465de..3ce5dff36f78 100644 > --- a/arch/x86/include/asm/cpufeatures.h > +++ b/arch/x86/include/asm/cpufeatures.h > @@ -459,6 +459,7 @@ > #define X86_FEATURE_ALLOWED_SEV_FEATURES (19*32+27) /* Allowed SEV Features */ > #define X86_FEATURE_SVSM (19*32+28) /* "svsm" SVSM present */ > #define X86_FEATURE_HV_INUSE_WR_ALLOWED (19*32+30) /* Allow Write to in-use hypervisor-owned pages */ > +#define X86_FEATURE_IBPB_ON_ENTRY (19*32+31) /* SEV-SNP IBPB on VM Entry */ > > /* AMD-defined Extended Feature 2 EAX, CPUID level 0x80000021 (EAX), word 20 */ > #define X86_FEATURE_NO_NESTED_DATA_BP (20*32+ 0) /* No Nested Data Breakpoints */ > diff --git a/arch/x86/include/asm/svm.h b/arch/x86/include/asm/svm.h > index edde36097ddc..eebc65ec948f 100644 > --- a/arch/x86/include/asm/svm.h > +++ b/arch/x86/include/asm/svm.h > @@ -306,6 +306,7 @@ static_assert((X2AVIC_4K_MAX_PHYSICAL_ID & AVIC_PHYSICAL_MAX_INDEX_MASK) == X2AV > #define SVM_SEV_FEAT_ALTERNATE_INJECTION BIT(4) > #define SVM_SEV_FEAT_DEBUG_SWAP BIT(5) > #define SVM_SEV_FEAT_SECURE_TSC BIT(9) > +#define SVM_SEV_FEAT_IBPB_ON_ENTRY BIT(21) > > #define VMCB_ALLOWED_SEV_FEATURES_VALID BIT_ULL(63) > > diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c > index ea515cf41168..8a6d25db0c00 100644 > --- a/arch/x86/kvm/svm/sev.c > +++ b/arch/x86/kvm/svm/sev.c > @@ -3165,8 +3165,15 @@ void __init sev_hardware_setup(void) > cpu_feature_enabled(X86_FEATURE_NO_NESTED_DATA_BP)) > sev_supported_vmsa_features |= SVM_SEV_FEAT_DEBUG_SWAP; > > - if (sev_snp_enabled && tsc_khz && cpu_feature_enabled(X86_FEATURE_SNP_SECURE_TSC)) > + if (!sev_snp_enabled) > + return; > + /* the following feature bit checks are SNP specific */ > + > + if (tsc_khz && cpu_feature_enabled(X86_FEATURE_SNP_SECURE_TSC)) > sev_supported_vmsa_features |= SVM_SEV_FEAT_SECURE_TSC; > + > + if (cpu_feature_enabled(X86_FEATURE_IBPB_ON_ENTRY)) > + sev_supported_vmsa_features |= SVM_SEV_FEAT_IBPB_ON_ENTRY; > } > > void sev_hardware_unsetup(void)