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From: Philipp Zabel <p.zabel@pengutronix.de>
To: Jacky Chou <jacky_chou@aspeedtech.com>,
	bhelgaas@google.com,  lpieralisi@kernel.org,
	kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org,
	 krzk+dt@kernel.org, conor+dt@kernel.org, joel@jms.id.au,
	 andrew@codeconstruct.com.au, linux-aspeed@lists.ozlabs.org,
	 linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
	 linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Cc: openbmc@lists.ozlabs.org, linux-gpio@vger.kernel.org,
	 linus.walleij@linaro.org, BMC-SW@aspeedtech.com
Subject: Re: [PATCH v2 09/10] PCI: aspeed: Add ASPEED PCIe RC driver
Date: Tue, 15 Jul 2025 15:51:48 +0200	[thread overview]
Message-ID: <e52bd959eea8a4284404f701d0519c4631a31238.camel@pengutronix.de> (raw)
In-Reply-To: <20250715034320.2553837-10-jacky_chou@aspeedtech.com>

On Di, 2025-07-15 at 11:43 +0800, Jacky Chou wrote:
> Introduce PCIe Root Complex driver for ASPEED SoCs. Support RC
> initialization, reset, clock, IRQ domain, and MSI domain setup.
> Implement platform-specific setup and register configuration for
> ASPEED. And provide PCI config space read/write and INTx/MSI
> interrupt handling.
> 
> Signed-off-by: Jacky Chou <jacky_chou@aspeedtech.com>
> ---
>  drivers/pci/controller/Kconfig       |   13 +
>  drivers/pci/controller/Makefile      |    1 +
>  drivers/pci/controller/pcie-aspeed.c | 1137 ++++++++++++++++++++++++++
>  3 files changed, 1151 insertions(+)
>  create mode 100644 drivers/pci/controller/pcie-aspeed.c
> 
[...]
> diff --git a/drivers/pci/controller/pcie-aspeed.c b/drivers/pci/controller/pcie-aspeed.c
> new file mode 100644
> index 000000000000..a7e679d5fb42
> --- /dev/null
> +++ b/drivers/pci/controller/pcie-aspeed.c
> @@ -0,0 +1,1137 @@
[...]
> +static int aspeed_pcie_parse_port(struct aspeed_pcie *pcie,
> +				  struct device_node *node,
> +				  int slot)
> +{
> +	struct aspeed_pcie_port *port;
> +	struct device *dev = pcie->dev;
> +
> +	port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
> +	if (!port)
> +		return -ENOMEM;
> +
> +	port->pciephy = syscon_regmap_lookup_by_phandle(node, "aspeed,pciephy");
> +	if (IS_ERR(port->pciephy))
> +		return dev_err_probe(dev, PTR_ERR(port->pciephy),
> +				     "Failed to map pcie%d pciephy base\n", slot);
> +
> +	port->clk = devm_get_clk_from_child(dev, node, NULL);
> +	if (IS_ERR(port->clk))
> +		return dev_err_probe(dev, PTR_ERR(port->clk),
> +				     "Failed to get pcie%d clock\n", slot);
> +
> +	port->perst = of_reset_control_get_exclusive(node, "perst");
> +	if (IS_ERR(port->perst))
> +		return dev_err_probe(dev, PTR_ERR(port->perst),
> +				     "Failed to get pcie%d reset control\n", slot);

How about registering a reset_control_put() via
devm_add_action_or_reset()?
Otherwise these reset controls are not released on .remove.

[...]
> +static int aspeed_pcie_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct pci_host_bridge *host;
> +	struct aspeed_pcie *pcie;
> +	struct aspeed_pcie_port *port;
> +	struct device_node *node = dev->of_node;
> +	const struct aspeed_pcie_rc_platform *md = of_device_get_match_data(dev);
> +	int irq, ret;
> +
> +	if (!md)
> +		return -ENODEV;
> +
> +	host = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
> +	if (!host)
> +		return -ENOMEM;
> +
> +	pcie = pci_host_bridge_priv(host);
> +	pcie->dev = dev;
> +	pcie->tx_tag = 0;
> +	platform_set_drvdata(pdev, pcie);
> +
> +	pcie->platform = md;
> +	pcie->host = host;
> +	INIT_LIST_HEAD(&pcie->ports);
> +
> +	pcie->reg = devm_platform_ioremap_resource(pdev, 0);
> +	if (IS_ERR(pcie->reg))
> +		return PTR_ERR(pcie->reg);
> +
> +	of_property_read_u32(node, "linux,pci-domain", &pcie->domain);
> +
> +	pcie->cfg = syscon_regmap_lookup_by_phandle(dev->of_node, "aspeed,pciecfg");
> +	if (IS_ERR(pcie->cfg))
> +		return dev_err_probe(dev, PTR_ERR(pcie->cfg), "Failed to map pciecfg base\n");
> +
> +	pcie->h2xrst = devm_reset_control_get_exclusive(dev, "h2x");
> +	if (IS_ERR(pcie->h2xrst))
> +		return dev_err_probe(dev, PTR_ERR(pcie->h2xrst), "Failed to get h2x reset\n");
> +
> +	ret = devm_mutex_init(dev, &pcie->lock);
> +	if (ret)
> +		return dev_err_probe(dev, ret, "Failed to init mutex\n");
> +
> +	ret = pcie->platform->setup(pdev);
> +	if (ret)
> +		return dev_err_probe(dev, ret, "Failed to setup PCIe RC\n");
> +
> +	ret = aspeed_pcie_parse_dt(pcie);
> +	if (ret)
> +		return ret;
> +
> +	ret = aspeed_pcie_init_ports(pcie);
> +	if (ret)
> +		goto err_remove_resets;
> +
> +	host->sysdata = pcie;
> +
> +	ret = aspeed_pcie_init_irq_domain(pcie);
> +	if (ret)
> +		goto err_irq_init;
> +
> +	irq = platform_get_irq(pdev, 0);
> +	if (irq < 0) {
> +		ret = irq;
> +		goto err_irq;
> +	}
> +
> +	ret = devm_request_irq(dev, irq, aspeed_pcie_intr_handler, IRQF_SHARED, dev_name(dev),
> +			       pcie);
> +	if (ret)
> +		goto err_irq;
> +
> +	ret = pci_host_probe(host);
> +	if (ret)
> +		goto err_irq;
> +
> +	return 0;
> +err_irq:
> +	aspeed_pcie_irq_domain_free(pcie);

If pci_host_probe() fails, aspeed_pcie_irq_domain_free() will be called
before the IRQ requested with devm_request_irq() above is released.
Also, this is never called on .remove. You can fix both with
devm_add_action_or_reset().

> +err_irq_init:
> +err_remove_resets:
> +	list_for_each_entry(port, &pcie->ports, list)
> +		reset_control_put(port->perst);

I suggest to let devres handle this (see above).

regards
Philipp


  reply	other threads:[~2025-07-15 13:52 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-07-15  3:43 [PATCH v2 00/10] Add ASPEED PCIe Root Complex support Jacky Chou
2025-07-15  3:43 ` [PATCH v2 01/10] dt-bindings: soc: aspeed: Add ASPEED PCIe Config support Jacky Chou
2025-07-16  8:24   ` Krzysztof Kozlowski
2025-07-21  3:47     ` 回覆: " Jacky Chou
2025-07-15  3:43 ` [PATCH v2 02/10] dt-bindings: soc: aspeed: Add ASPEED PCIe PHY support Jacky Chou
2025-07-16  8:23   ` Krzysztof Kozlowski
2025-07-15  3:43 ` [PATCH v2 03/10] dt-bindings: PCI: Add ASPEED PCIe RC support Jacky Chou
2025-07-16  8:27   ` Krzysztof Kozlowski
2025-07-21  3:44     ` 回覆: " Jacky Chou
2025-07-21  7:00       ` Krzysztof Kozlowski
2025-07-22  5:29         ` Jacky Chou
2025-07-15  3:43 ` [PATCH v2 04/10] dt-bindings: pinctrl: aspeed,ast2600-pinctrl: Add PCIe RC PERST# group Jacky Chou
2025-07-16  8:27   ` Krzysztof Kozlowski
2025-07-21  3:32     ` 回覆: " Jacky Chou
2025-07-15  3:43 ` [PATCH v2 05/10] ARM: dts: aspeed-g6: Add AST2600 PCIe RC PERST# Jacky Chou
2025-07-15  3:43 ` [PATCH v2 06/10] ARM: dts: aspeed-g6: Add PCIe RC node Jacky Chou
2025-07-15 15:25   ` Rob Herring
2025-07-16  3:51     ` Jacky Chou
2025-07-20 22:22       ` Rob Herring
2025-07-21  3:21         ` 回覆: " Jacky Chou
2025-07-15  3:43 ` [PATCH v2 07/10] pinctrl: aspeed-g6: Add PCIe RC PERST pin group Jacky Chou
2025-07-23 11:23   ` Linus Walleij
2025-08-27  3:08     ` Jacky Chou
2025-08-28 20:46       ` Linus Walleij
2025-08-29  5:44         ` Jacky Chou
2025-07-15  3:43 ` [PATCH v2 08/10] PCI: Add FMT and TYPE definition for TLP header Jacky Chou
2025-07-15 15:41   ` Bjorn Helgaas
2025-08-27  1:22     ` Jacky Chou
2025-07-15 20:13   ` kernel test robot
2025-07-15  3:43 ` [PATCH v2 09/10] PCI: aspeed: Add ASPEED PCIe RC driver Jacky Chou
2025-07-15 13:51   ` Philipp Zabel [this message]
2025-08-21  7:22     ` Jacky Chou
2025-07-15 16:22   ` Bjorn Helgaas
2025-08-22  7:00     ` 回覆: " Jacky Chou
2025-08-22 15:36       ` Bjorn Helgaas
2025-08-27  3:35         ` Jacky Chou
2025-07-15 17:00   ` Markus Elfring
2025-08-27  3:45     ` Jacky Chou
2025-07-15 22:28   ` kernel test robot
2025-07-15  3:43 ` [PATCH v2 10/10] MAINTAINERS: " Jacky Chou

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