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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: cj1xtb57ncyODJtLX+mdqSZWwe154WeJSXP41qJbpYRU1zCOqp+a3wHekS0i2P07hualajZ9tFefRUeA/N6rCY8NwfaGQuUca+TPqIlF6YjFvcA8lDnj57hOXrPQcMZu1AmwvFTWnJgB4ZI4GhOprIA4wr9JT2OzO4clSwDeYDued/8/xqeM+q8Cvq/PfgvCKhPFGM8Olhf3L/TR/MIu/iy8RjdJRd0rn0c3WH8vXHdOSBp7YFQMxsmOb+vCDQYxC/yMAXUDcuuvrlkn7IoxUNsHmqSCCA2UN/aEEyU9vCd+eNL1t9gBpdOveizxqreYAYNeSyenzWa2PIqSxkDQd7Tr643WgDy/P/YrgDdbz6tizN1asfWISNnBmbmXS64RHTfiKqp4et8fTVnPo/cAT3aDWj4m5y/P4pzHZWDu/Ztzrx0A42K0Awwqk6PtS81g X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Apr 2026 05:42:51.9559 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7f2b9aad-154e-4873-ee60-08dea1c45392 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001C8.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4428 Hello Andrea, On 4/23/2026 1:06 PM, Andrea Righi wrote: > On systems with asymmetric CPU capacity (e.g., ACPI/CPPC reporting > different per-core frequencies), the wakeup path uses > select_idle_capacity() and prioritizes idle CPUs with higher capacity > for better task placement. However, when those CPUs belong to SMT cores, > their effective capacity can be much lower than the nominal capacity > when the sibling thread is busy: SMT siblings compete for shared > resources, so a "high capacity" CPU that is idle but whose sibling is > busy does not deliver its full capacity. This effective capacity > reduction cannot be modeled by the static capacity value alone. > > Introduce SMT awareness in the asym-capacity idle selection policy: when > SMT is active, always prefer fully-idle SMT cores over partially-idle > ones. > > Prioritizing fully-idle SMT cores yields better task placement because > the effective capacity of partially-idle SMT cores is reduced; always > preferring them when available leads to more accurate capacity usage on > task wakeup. > > On an SMT system with asymmetric CPU capacities, SMT-aware idle > selection has been shown to improve throughput by around 15-18% for > CPU-bound workloads, running an amount of tasks equal to the amount of > SMT cores. > > Cc: Vincent Guittot > Cc: Dietmar Eggemann > Cc: Christian Loehle > Cc: Koba Ko > Reported-by: Felix Abecassis > Signed-off-by: Andrea Righi Thank you for chasing and cleaning this up. After squashing in changes from Patch 5, feel free to include: Reviewed-by: K Prateek Nayak -- Thanks and Regards, Prateek