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Thu, 25 Sep 2025 01:57:36 -0700 (PDT) Message-ID: Subject: Re: [PATCH] [v2] i3c: fix big-endian FIFO transfers From: Nuno =?ISO-8859-1?Q?S=E1?= To: "Guntupalli, Manikanta" , Jorge Marques , Arnd Bergmann Cc: Alexandre Belloni , Jorge Marques , Wolfram Sang , Frank Li , Arnd Bergmann , "linux-i3c@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "git (AMD-Xilinx)" , "Simek, Michal" Date: Thu, 25 Sep 2025 09:58:04 +0100 In-Reply-To: References: <20250924201837.3691486-1-arnd@kernel.org> <2wtpklapw5ogsevuvk2l4ngvw7hymer2y4cc454h47u2d7tq44@4mknmpk5yzil> <37d47af4f4d5220764efc5870630fdfc1e9be2c9.camel@gmail.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.58.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Thu, 2025-09-25 at 08:47 +0000, Guntupalli, Manikanta wrote: > [Public] >=20 > Hi, >=20 > > -----Original Message----- > > From: Nuno S=C3=A1 > > Sent: Thursday, September 25, 2025 1:22 PM > > To: Guntupalli, Manikanta ; Jorge Marques > > ; Arnd Bergmann > > Cc: Alexandre Belloni ; Jorge Marques > > ; Wolfram Sang > engineering.com>; Frank Li ; Arnd Bergmann > > ; linux-i3c@lists.infradead.org; > > linux-kernel@vger.kernel.org; git > > (AMD-Xilinx) ; Simek, Michal > > Subject: Re: [PATCH] [v2] i3c: fix big-endian FIFO transfers > >=20 > > On Thu, 2025-09-25 at 07:37 +0000, Guntupalli, Manikanta wrote: > > > [Public] > > >=20 > > > Hi, > > >=20 > > > > -----Original Message----- > > > > From: Jorge Marques > > > > Sent: Thursday, September 25, 2025 12:47 PM > > > > To: Arnd Bergmann > > > > Cc: Alexandre Belloni ; Jorge Marque= s > > > > ; Wolfram Sang > > > engineering.com>; Frank Li ; Arnd Bergmann > > > > ; Guntupalli, Manikanta > > > > ; > > > > linux- > > > > i3c@lists.infradead.org; linux-kernel@vger.kernel.org > > > > Subject: Re: [PATCH] [v2] i3c: fix big-endian FIFO transfers > > > >=20 > > > > On Wed, Sep 24, 2025 at 10:18:33PM +0200, Arnd Bergmann wrote: > > > > > From: Arnd Bergmann > > > > >=20 > > > > > Short MMIO transfers that are not a multiple of four bytes in siz= e > > > > > need a special case for the final bytes, however the existing > > > > > implementation is not endian-safe and introduces an incorrect > > > > > byteswap on big-endian kernels. > > > > >=20 > > > > > This usually does not cause problems because most systems are > > > > > little-endian and most transfers are multiple of four bytes long, > > > > > but still needs to be fixed to avoid the extra byteswap. > > > > >=20 > > > > > Change the special case for both i3c_writel_fifo() and > > > > > i3c_readl_fifo() to use non-byteswapping writesl() and readsl() > > > > > with a single element instead of the byteswapping writel()/readl(= ) > > > > > that are meant for individual MMIO registers. As data is copied > > > > > between a FIFO and a memory buffer, the writesl()/readsl() loops > > > > > are typically based on __raw_readl()/ __raw_writel(), resulting i= n > > > > > the order of bytes in the FIFO to match the order in the buffer, > > > > > regardless of the CPU endianess. > > > > >=20 > > > > > The earlier versions in the dw-i3c and i3c-master-cdns had a > > > > > correct implementation, but the generic version that was recently > > > > > added broke > > it. > > > > >=20 > > > > > Fixes: 733b439375b4 ("i3c: master: Add inline i3c_readl_fifo() an= d > > > > > i3c_writel_fifo()") > > > > > Cc: Manikanta Guntupalli > > > > > Signed-off-by: Arnd Bergmann > > > > > --- > > > > > This was a recent regression, the version in 6.16 still works, bu= t > > > > > 6.17-rc is broken. > > > > >=20 > > > > > v2 changes: > > > > > =C2=A0- add code comments > > > > > =C2=A0- write correct data buffer > > > > > --- > > > > > =C2=A0drivers/i3c/internals.h | 12 ++++++++++-- > > > > > =C2=A01 file changed, 10 insertions(+), 2 deletions(-) > > > > >=20 > > > > > diff --git a/drivers/i3c/internals.h b/drivers/i3c/internals.h > > > > > index 0d857cc68cc5..79ceaa5f5afd 100644 > > > > > --- a/drivers/i3c/internals.h > > > > > +++ b/drivers/i3c/internals.h > > > > > @@ -38,7 +38,11 @@ static inline void i3c_writel_fifo(void __iome= m > > > > > *addr, const > > > > void *buf, > > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 u32 tmp =3D 0; > > > > >=20 > > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 memcpy(&tmp, buf + (nbytes & ~3), nbytes & 3); > > > > > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 wri= tel(tmp, addr); > > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 /* > > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 * writesl() instead of writel() to keep FIFO > > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 * byteorder on big-endian targets > > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 */ > > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 wri= tesl(addr, &tmp, 1); > > > > > =C2=A0=C2=A0=C2=A0 } > > > > > =C2=A0} > > > > >=20 > > > > > @@ -55,7 +59,11 @@ static inline void i3c_readl_fifo(const void > > > > > __iomem *addr, > > > > void *buf, > > > > > =C2=A0=C2=A0=C2=A0 if (nbytes & 3) { > > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 u32 tmp; > > > > >=20 > > > > > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 tmp= =3D readl(addr); > > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 /* > > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 * readsl() instead of readl() to keep FIFO > > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 * byteorder on big-endian targets > > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 */ > > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 rea= dsl(addr, &tmp, 1); > > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 memcpy(buf + (nbytes & ~3), &tmp, nbytes & 3); > > > > > =C2=A0=C2=A0=C2=A0 } > > > > > =C2=A0} > > > > Reviewed-by: Jorge Marques > > > > > -- > > > > > 2.39.5 > > > > >=20 > > >=20 > > > This patch fixes the sub-word transfer case on big-endian kernels, bu= t > > > it still does not address the scenario of little-endian kernels > > > accessing big- endian FIFOs. > > >=20 > >=20 > > I would argue that's something for callers of these functions to care a= bout. > If each I3C driver has to handle FIFO endianness individually, it introdu= ces > unnecessary duplication and overhead across drivers. Centralizing this in= the > FIFO access helpers keeps the logic consistent, avoids repeated boilerpla= te, > and reduces the chance of subtle bugs. I mean, that's what spi and i2c drivers do already.=C2=A0With enum i3c_fifo= _endian you're already forcing users to care (or know) about endianism so they migh= t as well just pass the data in the proper order already (not sure if it's such = a big 'burden'). That said, I'm not really in the loop for i3c so not sure what the expectat= ions are. IOW, have no strong feeling about this at all :) - Nuno S=C3=A1 > >=20 > > > With the current version, i3c_writel_fifo() and i3c_readl_fifo() only > > > work when the FIFO has the same endianness as the CPU. On platforms > > > such as the > > > ZCU102 (Zynq UltraScale+ MPSoC, Cortex-A53, little-endian), the I3C > > > FIFOs are big-endian, and this patch alone is not sufficient - > > > transfers fail in that configuration. > > >=20 > > > We have validated this on ZCU102, and the mismatch between LE kernel > > > and BE FIFO is still an issue. > > >=20 > > > On top of this fix, explicit FIFO endianness support is required, as > > > proposed in [PATCH v7 3/4] "i3c: master: Add endianness support for > > > i3c_readl_fifo() and i3c_writel_fifo()". That approach adds an endian > > > argument and uses > > > writesl_be()/readsl_be() where necessary, e.g.: > > >=20 > > > static inline void i3c_writel_fifo(void __iomem *addr, const void > > > *buf, > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 int nbytes, en= um i3c_fifo_endian > > > endian) { > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if (endian) > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 writesl_be(addr, buf, nbytes / 4); > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 else > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 writesl(addr, buf, nbytes / 4); > > >=20 > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if (nbytes & 3) { > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 u32 tmp =3D 0; > > >=20 > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 memcpy(&tmp, buf + (nbytes & ~3), nbytes & 3); > > >=20 > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 if (endian) > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 write= sl_be(addr, &tmp, 1); > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 else > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 write= sl(addr, &tmp, 1); > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 } > > > } > > >=20 > > >=20 > Thanks, > Manikanta.