From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A2E71286D7E for ; Fri, 12 Dec 2025 12:30:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765542633; cv=none; b=SyAXmuChXdItye2FRKwGXOdMga6/zX/iS8mRaAzf3L4/ukHRSIcIZMSEvek+LUO6lyJ8+GXKLqXpFC0wnC8gWqpHexto2gdf/aJkadJsSIdvhIxfJpltiYH4pPAneDGzhi3XR3Eow7nfPx9+kKrM3zTf4Yj+AN7FwE5Z+c1dI7k= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765542633; c=relaxed/simple; bh=AFORBwPevguXtx/L3VaaR9qF0EpLmAr9R5Uu9rp7oCU=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=qi2m6XmbyBi3vKskCaxUuOZ5vFl+AVu2N1CgLM2tbBN8JREXtwgTp1RqwBr9asU/rYnkpkioG6NPgfR8eieKNgh+CJPBJBmaRcevCupen8gTv8msSOPzzQQT4YmWzwrPU4Qx/GyScKudq4d0kKwKlAsUeyvy0NCVvyIeRbTKgCo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 90D60FEC; Fri, 12 Dec 2025 04:30:23 -0800 (PST) Received: from [10.1.196.46] (e134344.arm.com [10.1.196.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7C1E63F762; Fri, 12 Dec 2025 04:30:27 -0800 (PST) Message-ID: Date: Fri, 12 Dec 2025 12:30:26 +0000 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH 01/38] arm64: mpam: Context switch the MPAM registers To: James Morse , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Jonathan Cameron , Gavin Shan , rohit.mathew@arm.com, reinette.chatre@intel.com, Punit Agrawal References: <20251205215901.17772-1-james.morse@arm.com> <20251205215901.17772-2-james.morse@arm.com> From: Ben Horgan Content-Language: en-US In-Reply-To: <20251205215901.17772-2-james.morse@arm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Hi James, On 12/5/25 21:58, James Morse wrote: > MPAM allows traffic in the SoC to be labeled by the OS, these labels > are used to apply policy in caches and bandwidth regulators, and to > monitor traffic in the SoC. The label is made up of a PARTID and PMG > value. The x86 equivalent calls these CLOSID and RMID, but they don't > map precisely. > > MPAM has two CPU system registers that is used to hold the PARTID and PMG > values that traffic generated at each exception level will use. These can be > set per-task by the resctrl file system. (resctrl is the defacto interface > for controlling this stuff). > > Add a helper to switch this. > > struct task_struct's separate CLOSID and RMID fields are insufficient > to implement resctrl using MPAM, as resctrl can change the PARTID (CLOSID) > and PMG (sort of like the RMID) separately. On x86, the rmid is an > independent number, so a race that writes a mismatched closid and rmid > into hardware is benign. On arm64, the pmg bits extend the partid. > (i.e. partid-5 has a pmg-0 that is not the same as partid-6's pmg-0). > In this case, mismatching the values will 'dirty' a pmg value that > resctrl believes is clean, and is not tracking with its 'limbo' code. > > To avoid this, the partid and pmg are always read and written as a pair. > Instead of making struct task_struct's closid and rmid fields an > endian-unsafe union, add the value to struct thread_info and always use > READ_ONCE()/WRITE_ONCE() when accessing this field. > > Resctrl allows a per-cpu 'default' value to be set, this overrides the > values when scheduling a task in the default control-group, which has > PARTID 0. The way 'code data prioritisation' gets emulated means the > register value for the default group needs to be a variable. > > The current system register value is kept in a per-cpu variable to > avoid writing to the system register if the value isn't going to change. > Writes to this register may reset the hardware state for regulating > bandwidth. > > Finally, there is no reason to context switch these registers unless > there is a driver changing the values in struct task_struct. Hide > the whole thing behind a static key. This also allows the driver to > disable MPAM in response to errors reported by hardware. Move the > existing static key to belong to the arch code, as in the future > the MPAM driver may become a loadable module. > > All this should depend on whether there is an MPAM driver, hide > it behind CONFIG_MPAM. > > CC: Amit Singh Tomar > Signed-off-by: James Morse [...] > + > +static inline void mpam_thread_switch(struct task_struct *tsk) > +{ > + u64 oldregval; > + int cpu = smp_processor_id(); > + u64 regval = mpam_get_regval(tsk); > + > + if (!IS_ENABLED(CONFIG_ARM64_MPAM) || > + !static_branch_likely(&mpam_enabled)) > + return; > + > + if (regval == READ_ONCE(arm64_mpam_global_default)) > + regval = READ_ONCE(per_cpu(arm64_mpam_default, cpu)); > + > + oldregval = READ_ONCE(per_cpu(arm64_mpam_current, cpu)); > + if (oldregval == regval) > + return; > + > + write_sysreg_s(regval, SYS_MPAM1_EL1); > + isb(); > + > + /* Synchronising the EL0 write is left until the ERET to EL0 */ > + write_sysreg_s(regval, SYS_MPAM0_EL1); SYS_MPAMSM_EL1 needs to be written here too to account for accesses generated by SME loads. Also, when in streaming mode, SVE and FP loads, stores and SVE prefetches. SYS_MPAMSM_EL1 should also be considered in initialisation code too. > + > + WRITE_ONCE(per_cpu(arm64_mpam_current, cpu), regval); > +} Thanks, Ben