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Sun, 02 Feb 2025 15:17:24 -0800 (PST) X-Google-Smtp-Source: AGHT+IEDd7NX+s9VmJsk4Gu/C5cdF+xO9wYV1JktzYhBU9uRWjBep69A7UQIF0gV3XEciNO6G3kkpg== X-Received: by 2002:a05:6a00:80a:b0:727:d55e:4be3 with SMTP id d2e1a72fcca58-72fd0beabb1mr27783675b3a.7.1738538243767; Sun, 02 Feb 2025 15:17:23 -0800 (PST) Received: from [192.168.68.55] ([180.233.125.64]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-72fe6429a98sm7393173b3a.67.2025.02.02.15.17.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 02 Feb 2025 15:17:23 -0800 (PST) Message-ID: Date: Mon, 3 Feb 2025 09:17:15 +1000 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 34/43] arm64: RME: Propagate number of breakpoints and watchpoints to userspace From: Gavin Shan To: Steven Price , kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: Jean-Philippe Brucker , Catalin Marinas , Marc Zyngier , Will Deacon , James Morse , Oliver Upton , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Gouly , Alexandru Elisei , Christoffer Dall , Fuad Tabba , linux-coco@lists.linux.dev, Ganapatrao Kulkarni , Shanker Donthineni , Alper Gun , "Aneesh Kumar K . V" References: <20241212155610.76522-1-steven.price@arm.com> <20241212155610.76522-35-steven.price@arm.com> <34990c4f-b65e-4af2-8348-87ea078afc16@redhat.com> Content-Language: en-US In-Reply-To: <34990c4f-b65e-4af2-8348-87ea078afc16@redhat.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 2/3/25 9:15 AM, Gavin Shan wrote: > On 12/13/24 1:55 AM, Steven Price wrote: >> From: Jean-Philippe Brucker >> >> The RMM describes the maximum number of BPs/WPs available to the guest >> in the Feature Register 0. Propagate those numbers into ID_AA64DFR0_EL1, >> which is visible to userspace. A VMM needs this information in order to >> set up realm parameters. >> >> Signed-off-by: Jean-Philippe Brucker >> Signed-off-by: Steven Price >> --- >>   arch/arm64/include/asm/kvm_rme.h |  2 ++ >>   arch/arm64/kvm/rme.c             | 22 ++++++++++++++++++++++ >>   arch/arm64/kvm/sys_regs.c        |  2 +- >>   3 files changed, 25 insertions(+), 1 deletion(-) >> >> diff --git a/arch/arm64/include/asm/kvm_rme.h b/arch/arm64/include/asm/kvm_rme.h >> index 0d89ab1645c1..f8e37907e2d5 100644 >> --- a/arch/arm64/include/asm/kvm_rme.h >> +++ b/arch/arm64/include/asm/kvm_rme.h >> @@ -85,6 +85,8 @@ void kvm_init_rme(void); >>   u32 kvm_realm_ipa_limit(void); >>   u32 kvm_realm_vgic_nr_lr(void); >> +u64 kvm_realm_reset_id_aa64dfr0_el1(const struct kvm_vcpu *vcpu, u64 val); >> + >>   bool kvm_rme_supports_sve(void); >>   int kvm_realm_enable_cap(struct kvm *kvm, struct kvm_enable_cap *cap); >> diff --git a/arch/arm64/kvm/rme.c b/arch/arm64/kvm/rme.c >> index e562e77c1f94..d21042d5ec9a 100644 >> --- a/arch/arm64/kvm/rme.c >> +++ b/arch/arm64/kvm/rme.c >> @@ -63,6 +63,28 @@ u32 kvm_realm_vgic_nr_lr(void) >>       return u64_get_bits(rmm_feat_reg0, RMI_FEATURE_REGISTER_0_GICV3_NUM_LRS); >>   } >> +u64 kvm_realm_reset_id_aa64dfr0_el1(const struct kvm_vcpu *vcpu, u64 val) >> +{ >> +    u32 bps = u64_get_bits(rmm_feat_reg0, RMI_FEATURE_REGISTER_0_NUM_BPS); >> +    u32 wps = u64_get_bits(rmm_feat_reg0, RMI_FEATURE_REGISTER_0_NUM_WPS); >> +    u32 ctx_cmps; >> + >> +    if (!kvm_is_realm(vcpu->kvm)) >> +        return val; >> + >> +    /* Ensure CTX_CMPs is still valid */ >> +    ctx_cmps = FIELD_GET(ID_AA64DFR0_EL1_CTX_CMPs, val); >> +    ctx_cmps = min(bps, ctx_cmps); >> + >> +    val &= ~(ID_AA64DFR0_EL1_BRPs_MASK | ID_AA64DFR0_EL1_WRPs_MASK | >> +         ID_AA64DFR0_EL1_CTX_CMPs); >> +    val |= FIELD_PREP(ID_AA64DFR0_EL1_BRPs_MASK, bps) | >> +           FIELD_PREP(ID_AA64DFR0_EL1_WRPs_MASK, wps) | >> +           FIELD_PREP(ID_AA64DFR0_EL1_CTX_CMPs, ctx_cmps); >> + >> +    return val; >> +} >> + > > The the filed ID_AA64DFR0_EL1_WRPs_MASK of the system register ID_AA64DFR0_EL1 is > writtable, as declared in sys_reg.c. We need to consolidate the field when the > system register is written. > >         ID_FILTERED(ID_AA64DFR0_EL1, id_aa64dfr0_el1, >                     ID_AA64DFR0_EL1_DoubleLock_MASK | >                     ID_AA64DFR0_EL1_WRPs_MASK | >                     ID_AA64DFR0_EL1_PMUVer_MASK | >                     ID_AA64DFR0_EL1_DebugVer_MASK), > Please ignore this comment. The consolidation when the system register is written has been covered by PATCH[35/43]. >>   static int get_start_level(struct realm *realm) >>   { >>       return 4 - stage2_pgtable_levels(realm->ia_bits); >> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c >> index a4713609e230..55cde43b36b9 100644 >> --- a/arch/arm64/kvm/sys_regs.c >> +++ b/arch/arm64/kvm/sys_regs.c >> @@ -1806,7 +1806,7 @@ static u64 sanitise_id_aa64dfr0_el1(const struct kvm_vcpu *vcpu, u64 val) >>       /* Hide SPE from guests */ >>       val &= ~ID_AA64DFR0_EL1_PMSVer_MASK; >> -    return val; >> +    return kvm_realm_reset_id_aa64dfr0_el1(vcpu, val); >>   } >>   static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, Thanks, Gavin