From: Abhinav Kumar <quic_abhinavk@quicinc.com>
To: Marijn Suijten <marijn.suijten@somainline.org>
Cc: Kuogee Hsieh <quic_khsieh@quicinc.com>, <robdclark@gmail.com>,
<sean@poorly.run>, <swboyd@chromium.org>, <dianders@chromium.org>,
<vkoul@kernel.org>, <daniel@ffwll.ch>, <airlied@gmail.com>,
<agross@kernel.org>, <dmitry.baryshkov@linaro.org>,
<andersson@kernel.org>, <quic_sbillaka@quicinc.com>,
<freedreno@lists.freedesktop.org>,
<dri-devel@lists.freedesktop.org>,
<linux-arm-msm@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH] drm/msm/dpu: always program dsc active bits
Date: Wed, 12 Apr 2023 10:33:15 -0700 [thread overview]
Message-ID: <e78e576a-2a04-e7ca-f6c4-701d508541ad@quicinc.com> (raw)
In-Reply-To: <feedv4isliterjtwyicqfarwuvzhtov3jkmvjcwqvt7itkyh7y@e2jq5t6r3lxc>
On 4/12/2023 12:24 AM, Marijn Suijten wrote:
> On 2023-04-11 16:45:34, Abhinav Kumar wrote:
> [..]
>>> Does this flush all DSCs programmed in CTL_DSC_FLUSH as set above? That
>>> is currently still in `if (cfg->dsc)` and never overwritten if all DSCs
>>> are disabled, should it be taken out of the `if` to make sure no DSCs
>>> are inadvertently flushed, or otherwise cache the "previous mask" to
>>> make sure we flush exactly the right DSC blocks?
>>>
>>
>> Yes, DSC flush is hierarchical. This is the main DSC flush which will
>> enforce the flush of the DSC's we are trying to flush in the
>> CTL_DSC_FLUSH register.
>
> That's what I was thinking, thanks for confirming.
>
>> So if DSC was active, the CTL_FLUSH will only enforce the flush of the
>> DSC's programmed in CTL_DSC_FLUSH
>>
>> If DSC is not active, we still need to flush that as well (that was the
>> missing bit).
>>
>> No need to cache previous mask. That programming should be accurate in
>> cfg->dsc already.
>
> This kind of implicit dependency warrants a comment at the very least.
>
Sure.
> What happens if a device boots without DSC panel connected? Will
> CTL_DSC_FLUSH be zero and not (unnecessarily, I assume) flush any of the
> DSC blocks? Or could this flush uninitialized state to the block?
>
If we bootup without DSC panel connected, the kernel's cfg->dsc will be
0 and default register value of CTL_DSC_FLUSH will be 0 so it wont flush
any DSC blocks. Sure, as I wrote in the other response, we can move this
to reset_intf_cfg later when the other pieces are fixed. And leave a
FIXME here.
> - Marijn
next prev parent reply other threads:[~2023-04-12 17:33 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-11 21:04 [PATCH] drm/msm/dpu: always program dsc active bits Kuogee Hsieh
2023-04-11 21:39 ` Abhinav Kumar
2023-04-11 22:14 ` Marijn Suijten
2023-04-11 23:45 ` Abhinav Kumar
2023-04-12 7:24 ` Marijn Suijten
2023-04-12 17:33 ` Abhinav Kumar [this message]
2023-04-14 7:35 ` Marijn Suijten
2023-04-14 15:48 ` Abhinav Kumar
2023-04-14 17:34 ` Marijn Suijten
2023-04-14 17:57 ` [Freedreno] " Abhinav Kumar
2023-04-14 23:11 ` Marijn Suijten
2023-04-14 23:51 ` Abhinav Kumar
2023-04-27 20:32 ` Marijn Suijten
2023-04-11 22:17 ` Dmitry Baryshkov
2023-04-11 23:32 ` Abhinav Kumar
2023-04-11 23:36 ` Dmitry Baryshkov
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