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Wed, 13 May 2026 06:53:56 -0700 (PDT) X-Received: by 2002:a17:903:8c6:b0:2bd:907:2cf0 with SMTP id d9443c01a7336-2bd276f20f8mr41795905ad.32.1778680435955; Wed, 13 May 2026 06:53:55 -0700 (PDT) Received: from [10.219.49.212] ([202.46.23.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2baf1d405efsm179171335ad.23.2026.05.13.06.53.53 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 13 May 2026 06:53:55 -0700 (PDT) Message-ID: Date: Wed, 13 May 2026 19:23:52 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 2/2] pinctrl: qcom: lpass-lpi: Switch to PM clock framework for runtime PM To: Dmitry Baryshkov Cc: Bjorn Andersson , Linus Walleij , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, mohammad.rafi.shaik@oss.qualcomm.com References: <20260508113636.3561383-1-ajay.nandam@oss.qualcomm.com> <20260513122542.3726319-2-ajay.nandam@oss.qualcomm.com> Content-Language: en-US From: Ajay Kumar Nandam In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTEzMDE0MiBTYWx0ZWRfX5GKglV5L224r UN1d9dlQp1IOcfd5pBibT5RAzzT5wrFYhYPvZ+x6tyEhPkmvPUfFeYw0aa58puWskflRyHaKUi7 SyYLiNXNQTdhjJNLTYmpMixjJLdk10H7tBZldYp8R+WVQwNnwlBjm3sM8WDAUhVxnD0KjYuv9ok jZ/09z6Wcz1pmNSrlRVBPbyX06bw/wdknxs3Q6UZHE2fOVb0EWcuK6JZbsef4Yu367rs5jZHmE9 uMYOdWqfM1VGAC4HQoRxDIquttYeqbQispeE82EcXTJIwHP5whyHfGXi/BVZQFPy0VZSUoLQkoD UaOb5dVr94RVWkJxpWN/mpkTAH4yMgea2UL0het5Id3Hj0J0p/oO8XpGWKgg3QzqOXVi7d2Lc6P f1cLRmxqxmfagVbVqnPZ8bjgH2TYR3OAwazgcLHZ8DCn4dvm/vZXswW5lZmlt6eboK6I1MT/GTT Dmc6sMabbNWDUJdaAkA== X-Proofpoint-GUID: ifHQJ_iFffPR_0XL9xg5e2Mn0HNBxjJJ X-Authority-Analysis: v=2.4 cv=L68theT8 c=1 sm=1 tr=0 ts=6a048275 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=j4ogTh8yFefVWWEFDRgCtg==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=3XSISe0faenqoDDrUQoA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-ORIG-GUID: ifHQJ_iFffPR_0XL9xg5e2Mn0HNBxjJJ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-13_01,2026-05-08_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 impostorscore=0 adultscore=0 priorityscore=1501 suspectscore=0 clxscore=1015 malwarescore=0 lowpriorityscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605050000 definitions=main-2605130142 On 5/13/2026 6:22 PM, Dmitry Baryshkov wrote: > On Wed, May 13, 2026 at 05:55:26PM +0530, Ajay Kumar Nandam wrote: >> Convert the LPASS LPI pinctrl driver to use the PM clock framework for >> runtime power management. >> >> This allows the LPASS LPI pinctrl driver to drop clock votes when idle, >> improves power efficiency on platforms using LPASS LPI island mode, and >> aligns the driver with common runtime PM patterns used across Qualcomm >> LPASS subsystems. >> >> Guard GPIO register read/write helpers and slew-rate register programming >> with synchronous runtime PM calls so the device is active during MMIO >> operations whenever autosuspend is enabled. >> >> Signed-off-by: Ajay Kumar Nandam >> --- >> drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 118 ++++++++++++------ >> .../pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c | 7 ++ >> 2 files changed, 88 insertions(+), 37 deletions(-) >> >> diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c >> index 15ced5027579..d95e28926d38 100644 >> --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c >> +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c >> @@ -15,6 +15,9 @@ >> #include >> #include >> #include >> +#include >> +#include >> +#include >> >> #include "../pinctrl-utils.h" >> >> @@ -22,7 +25,6 @@ >> >> #define MAX_NR_GPIO 32 >> #define GPIO_FUNC 0 >> -#define MAX_LPI_NUM_CLKS 2 >> >> struct lpi_pinctrl { >> struct device *dev; >> @@ -31,7 +33,6 @@ struct lpi_pinctrl { >> struct pinctrl_desc desc; >> char __iomem *tlmm_base; >> char __iomem *slew_base; >> - struct clk_bulk_data clks[MAX_LPI_NUM_CLKS]; >> /* Protects from concurrent register updates */ >> struct mutex lock; >> DECLARE_BITMAP(ever_gpio, MAX_NR_GPIO); >> @@ -39,29 +40,47 @@ struct lpi_pinctrl { >> }; >> >> static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin, >> - unsigned int addr) >> + unsigned int addr, u32 *val) >> { >> u32 pin_offset; >> + int ret; >> >> if (state->data->flags & LPI_FLAG_USE_PREDEFINED_PIN_OFFSET) >> pin_offset = state->data->groups[pin].pin_offset; >> else >> pin_offset = LPI_TLMM_REG_OFFSET * pin; >> >> - return ioread32(state->tlmm_base + pin_offset + addr); >> + ret = pm_runtime_resume_and_get(state->dev); >> + if (ret < 0) >> + return ret; >> + >> + *val = ioread32(state->tlmm_base + pin_offset + addr); >> + ret = pm_runtime_put_autosuspend(state->dev); >> + if (ret < 0) >> + return ret; >> + >> + return 0; > > Just `return pm_runtime_put_autosuspend(state->dev)`, no need for extra > ifs. > ACK, Addressed in V5. Thanks Ajay Kumar >> } >> >