* [PATCH v2] drm/msm: adreno: a6xx: enable GMU bandwidth voting for x1e80100 GPU @ 2025-07-25 8:35 Neil Armstrong 2025-07-31 10:19 ` Konrad Dybcio 2025-08-18 7:13 ` Akhil P Oommen 0 siblings, 2 replies; 11+ messages in thread From: Neil Armstrong @ 2025-07-25 8:35 UTC (permalink / raw) To: Rob Clark, Sean Paul, Konrad Dybcio, Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang, Marijn Suijten, David Airlie, Simona Vetter Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel, Dmitry Baryshkov, Neil Armstrong The Adreno GPU Management Unit (GMU) can also scale DDR Bandwidth along the Frequency and Power Domain level, but by default we leave the OPP core scale the interconnect ddr path. Declare the Bus Control Modules (BCMs) and the corresponding parameters in the GPU info struct to allow the GMU to vote for the bandwidth. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> --- Changes in v2: - Used proper ACV perfmode bit/freq - Link to v1: https://lore.kernel.org/r/20250721-topic-x1e80100-gpu-bwvote-v1-1-946619b0f73a@linaro.org --- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c index 00e1afd46b81546eec03e22cda9e9a604f6f3b60..892f98b1f2ae582268adebd758437ff60456cdd5 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -1440,6 +1440,17 @@ static const struct adreno_info a7xx_gpus[] = { .pwrup_reglist = &a7xx_pwrup_reglist, .gmu_chipid = 0x7050001, .gmu_cgc_mode = 0x00020202, + .bcms = (const struct a6xx_bcm[]) { + { .name = "SH0", .buswidth = 16 }, + { .name = "MC0", .buswidth = 4 }, + { + .name = "ACV", + .fixed = true, + .perfmode = BIT(3), + .perfmode_bw = 16500000, + }, + { /* sentinel */ }, + }, }, .preempt_record_size = 4192 * SZ_1K, .speedbins = ADRENO_SPEEDBINS( --- base-commit: 97987520025658f30bb787a99ffbd9bbff9ffc9d change-id: 20250721-topic-x1e80100-gpu-bwvote-9fc4690fe5e3 Best regards, -- Neil Armstrong <neil.armstrong@linaro.org> ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH v2] drm/msm: adreno: a6xx: enable GMU bandwidth voting for x1e80100 GPU 2025-07-25 8:35 [PATCH v2] drm/msm: adreno: a6xx: enable GMU bandwidth voting for x1e80100 GPU Neil Armstrong @ 2025-07-31 10:19 ` Konrad Dybcio 2025-08-14 11:21 ` Konrad Dybcio 2025-08-18 7:13 ` Akhil P Oommen 1 sibling, 1 reply; 11+ messages in thread From: Konrad Dybcio @ 2025-07-31 10:19 UTC (permalink / raw) To: Neil Armstrong, Rob Clark, Sean Paul, Konrad Dybcio, Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang, Marijn Suijten, David Airlie, Simona Vetter Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel, Dmitry Baryshkov On 7/25/25 10:35 AM, Neil Armstrong wrote: > The Adreno GPU Management Unit (GMU) can also scale DDR Bandwidth along > the Frequency and Power Domain level, but by default we leave the > OPP core scale the interconnect ddr path. > > Declare the Bus Control Modules (BCMs) and the corresponding parameters > in the GPU info struct to allow the GMU to vote for the bandwidth. > > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> > Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> > --- > Changes in v2: > - Used proper ACV perfmode bit/freq > - Link to v1: https://lore.kernel.org/r/20250721-topic-x1e80100-gpu-bwvote-v1-1-946619b0f73a@linaro.org > --- > drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > index 00e1afd46b81546eec03e22cda9e9a604f6f3b60..892f98b1f2ae582268adebd758437ff60456cdd5 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > @@ -1440,6 +1440,17 @@ static const struct adreno_info a7xx_gpus[] = { > .pwrup_reglist = &a7xx_pwrup_reglist, > .gmu_chipid = 0x7050001, > .gmu_cgc_mode = 0x00020202, > + .bcms = (const struct a6xx_bcm[]) { > + { .name = "SH0", .buswidth = 16 }, > + { .name = "MC0", .buswidth = 4 }, > + { > + .name = "ACV", > + .fixed = true, > + .perfmode = BIT(3), > + .perfmode_bw = 16500000, Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Konrad ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2] drm/msm: adreno: a6xx: enable GMU bandwidth voting for x1e80100 GPU 2025-07-31 10:19 ` Konrad Dybcio @ 2025-08-14 11:21 ` Konrad Dybcio 2025-08-14 11:22 ` Konrad Dybcio 0 siblings, 1 reply; 11+ messages in thread From: Konrad Dybcio @ 2025-08-14 11:21 UTC (permalink / raw) To: Neil Armstrong, Rob Clark, Sean Paul, Konrad Dybcio, Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang, Marijn Suijten, David Airlie, Simona Vetter Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel, Dmitry Baryshkov On 7/31/25 12:19 PM, Konrad Dybcio wrote: > On 7/25/25 10:35 AM, Neil Armstrong wrote: >> The Adreno GPU Management Unit (GMU) can also scale DDR Bandwidth along >> the Frequency and Power Domain level, but by default we leave the >> OPP core scale the interconnect ddr path. >> >> Declare the Bus Control Modules (BCMs) and the corresponding parameters >> in the GPU info struct to allow the GMU to vote for the bandwidth. >> >> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> >> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> >> --- >> Changes in v2: >> - Used proper ACV perfmode bit/freq >> - Link to v1: https://lore.kernel.org/r/20250721-topic-x1e80100-gpu-bwvote-v1-1-946619b0f73a@linaro.org >> --- >> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 11 +++++++++++ >> 1 file changed, 11 insertions(+) >> >> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >> index 00e1afd46b81546eec03e22cda9e9a604f6f3b60..892f98b1f2ae582268adebd758437ff60456cdd5 100644 >> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >> @@ -1440,6 +1440,17 @@ static const struct adreno_info a7xx_gpus[] = { >> .pwrup_reglist = &a7xx_pwrup_reglist, >> .gmu_chipid = 0x7050001, >> .gmu_cgc_mode = 0x00020202, >> + .bcms = (const struct a6xx_bcm[]) { >> + { .name = "SH0", .buswidth = 16 }, >> + { .name = "MC0", .buswidth = 4 }, >> + { >> + .name = "ACV", >> + .fixed = true, >> + .perfmode = BIT(3), >> + .perfmode_bw = 16500000, > > Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Actually no, BIT(3) is for the CPU (OS), GPU should use BIT(2) Konrad ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2] drm/msm: adreno: a6xx: enable GMU bandwidth voting for x1e80100 GPU 2025-08-14 11:21 ` Konrad Dybcio @ 2025-08-14 11:22 ` Konrad Dybcio 2025-08-14 14:26 ` Neil Armstrong 0 siblings, 1 reply; 11+ messages in thread From: Konrad Dybcio @ 2025-08-14 11:22 UTC (permalink / raw) To: Neil Armstrong, Rob Clark, Sean Paul, Konrad Dybcio, Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang, Marijn Suijten, David Airlie, Simona Vetter Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel, Dmitry Baryshkov On 8/14/25 1:21 PM, Konrad Dybcio wrote: > On 7/31/25 12:19 PM, Konrad Dybcio wrote: >> On 7/25/25 10:35 AM, Neil Armstrong wrote: >>> The Adreno GPU Management Unit (GMU) can also scale DDR Bandwidth along >>> the Frequency and Power Domain level, but by default we leave the >>> OPP core scale the interconnect ddr path. >>> >>> Declare the Bus Control Modules (BCMs) and the corresponding parameters >>> in the GPU info struct to allow the GMU to vote for the bandwidth. >>> >>> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> >>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> >>> --- >>> Changes in v2: >>> - Used proper ACV perfmode bit/freq >>> - Link to v1: https://lore.kernel.org/r/20250721-topic-x1e80100-gpu-bwvote-v1-1-946619b0f73a@linaro.org >>> --- >>> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 11 +++++++++++ >>> 1 file changed, 11 insertions(+) >>> >>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >>> index 00e1afd46b81546eec03e22cda9e9a604f6f3b60..892f98b1f2ae582268adebd758437ff60456cdd5 100644 >>> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >>> @@ -1440,6 +1440,17 @@ static const struct adreno_info a7xx_gpus[] = { >>> .pwrup_reglist = &a7xx_pwrup_reglist, >>> .gmu_chipid = 0x7050001, >>> .gmu_cgc_mode = 0x00020202, >>> + .bcms = (const struct a6xx_bcm[]) { >>> + { .name = "SH0", .buswidth = 16 }, >>> + { .name = "MC0", .buswidth = 4 }, >>> + { >>> + .name = "ACV", >>> + .fixed = true, >>> + .perfmode = BIT(3), >>> + .perfmode_bw = 16500000, >> >> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> > > Actually no, BIT(3) is for the CPU (OS), GPU should use BIT(2) This is *very* platform-dependent, goes without saying.. I see BIT(2) is also valid for X1P4 Konrad ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2] drm/msm: adreno: a6xx: enable GMU bandwidth voting for x1e80100 GPU 2025-08-14 11:22 ` Konrad Dybcio @ 2025-08-14 14:26 ` Neil Armstrong 2025-08-14 16:38 ` Akhil P Oommen 0 siblings, 1 reply; 11+ messages in thread From: Neil Armstrong @ 2025-08-14 14:26 UTC (permalink / raw) To: Konrad Dybcio, Rob Clark, Sean Paul, Konrad Dybcio, Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang, Marijn Suijten, David Airlie, Simona Vetter, Akhil P Oommen Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel, Dmitry Baryshkov Hi, On 14/08/2025 13:22, Konrad Dybcio wrote: > On 8/14/25 1:21 PM, Konrad Dybcio wrote: >> On 7/31/25 12:19 PM, Konrad Dybcio wrote: >>> On 7/25/25 10:35 AM, Neil Armstrong wrote: >>>> The Adreno GPU Management Unit (GMU) can also scale DDR Bandwidth along >>>> the Frequency and Power Domain level, but by default we leave the >>>> OPP core scale the interconnect ddr path. >>>> >>>> Declare the Bus Control Modules (BCMs) and the corresponding parameters >>>> in the GPU info struct to allow the GMU to vote for the bandwidth. >>>> >>>> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> >>>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> >>>> --- >>>> Changes in v2: >>>> - Used proper ACV perfmode bit/freq >>>> - Link to v1: https://lore.kernel.org/r/20250721-topic-x1e80100-gpu-bwvote-v1-1-946619b0f73a@linaro.org >>>> --- >>>> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 11 +++++++++++ >>>> 1 file changed, 11 insertions(+) >>>> >>>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >>>> index 00e1afd46b81546eec03e22cda9e9a604f6f3b60..892f98b1f2ae582268adebd758437ff60456cdd5 100644 >>>> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >>>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >>>> @@ -1440,6 +1440,17 @@ static const struct adreno_info a7xx_gpus[] = { >>>> .pwrup_reglist = &a7xx_pwrup_reglist, >>>> .gmu_chipid = 0x7050001, >>>> .gmu_cgc_mode = 0x00020202, >>>> + .bcms = (const struct a6xx_bcm[]) { >>>> + { .name = "SH0", .buswidth = 16 }, >>>> + { .name = "MC0", .buswidth = 4 }, >>>> + { >>>> + .name = "ACV", >>>> + .fixed = true, >>>> + .perfmode = BIT(3), >>>> + .perfmode_bw = 16500000, >>> >>> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> >> >> Actually no, BIT(3) is for the CPU (OS), GPU should use BIT(2) > > This is *very* platform-dependent, goes without saying.. > > I see BIT(2) is also valid for X1P4 I'm confused, Akhil can you confirm ? Neil > > Konrad ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2] drm/msm: adreno: a6xx: enable GMU bandwidth voting for x1e80100 GPU 2025-08-14 14:26 ` Neil Armstrong @ 2025-08-14 16:38 ` Akhil P Oommen 2025-08-14 17:52 ` Konrad Dybcio 2025-08-15 22:15 ` Dmitry Baryshkov 0 siblings, 2 replies; 11+ messages in thread From: Akhil P Oommen @ 2025-08-14 16:38 UTC (permalink / raw) To: Neil Armstrong, Konrad Dybcio, Rob Clark, Sean Paul, Konrad Dybcio, Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang, Marijn Suijten, David Airlie, Simona Vetter Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel, Dmitry Baryshkov On 8/14/2025 7:56 PM, Neil Armstrong wrote: > Hi, > > On 14/08/2025 13:22, Konrad Dybcio wrote: >> On 8/14/25 1:21 PM, Konrad Dybcio wrote: >>> On 7/31/25 12:19 PM, Konrad Dybcio wrote: >>>> On 7/25/25 10:35 AM, Neil Armstrong wrote: >>>>> The Adreno GPU Management Unit (GMU) can also scale DDR Bandwidth >>>>> along >>>>> the Frequency and Power Domain level, but by default we leave the >>>>> OPP core scale the interconnect ddr path. >>>>> >>>>> Declare the Bus Control Modules (BCMs) and the corresponding >>>>> parameters >>>>> in the GPU info struct to allow the GMU to vote for the bandwidth. >>>>> >>>>> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> >>>>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> >>>>> --- >>>>> Changes in v2: >>>>> - Used proper ACV perfmode bit/freq >>>>> - Link to v1: https://lore.kernel.org/r/20250721-topic-x1e80100- >>>>> gpu-bwvote-v1-1-946619b0f73a@linaro.org >>>>> --- >>>>> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 11 +++++++++++ >>>>> 1 file changed, 11 insertions(+) >>>>> >>>>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/ >>>>> gpu/drm/msm/adreno/a6xx_catalog.c >>>>> index >>>>> 00e1afd46b81546eec03e22cda9e9a604f6f3b60..892f98b1f2ae582268adebd758437ff60456cdd5 100644 >>>>> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >>>>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >>>>> @@ -1440,6 +1440,17 @@ static const struct adreno_info a7xx_gpus[] = { >>>>> .pwrup_reglist = &a7xx_pwrup_reglist, >>>>> .gmu_chipid = 0x7050001, >>>>> .gmu_cgc_mode = 0x00020202, >>>>> + .bcms = (const struct a6xx_bcm[]) { >>>>> + { .name = "SH0", .buswidth = 16 }, >>>>> + { .name = "MC0", .buswidth = 4 }, >>>>> + { >>>>> + .name = "ACV", >>>>> + .fixed = true, >>>>> + .perfmode = BIT(3), >>>>> + .perfmode_bw = 16500000, >>>> >>>> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> >>> >>> Actually no, BIT(3) is for the CPU (OS), GPU should use BIT(2) You are right that BIT(2) is GPU specific, but that support was commercialized from A7XX_GEN3. Anyway, the Win KMD uses BIT(2), so lets use that in Linux too. I know some docs show BIT(2) support, but lets not bring in untested configurations. -Akhil. >> >> This is *very* platform-dependent, goes without saying.. >> >> I see BIT(2) is also valid for X1P4 > > > I'm confused, Akhil can you confirm ? > > Neil> >> >> Konrad > ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2] drm/msm: adreno: a6xx: enable GMU bandwidth voting for x1e80100 GPU 2025-08-14 16:38 ` Akhil P Oommen @ 2025-08-14 17:52 ` Konrad Dybcio 2025-08-15 22:15 ` Dmitry Baryshkov 2025-08-15 22:15 ` Dmitry Baryshkov 1 sibling, 1 reply; 11+ messages in thread From: Konrad Dybcio @ 2025-08-14 17:52 UTC (permalink / raw) To: Akhil P Oommen, Neil Armstrong, Rob Clark, Sean Paul, Konrad Dybcio, Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang, Marijn Suijten, David Airlie, Simona Vetter Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel, Dmitry Baryshkov On 8/14/25 6:38 PM, Akhil P Oommen wrote: > On 8/14/2025 7:56 PM, Neil Armstrong wrote: >> Hi, >> >> On 14/08/2025 13:22, Konrad Dybcio wrote: >>> On 8/14/25 1:21 PM, Konrad Dybcio wrote: >>>> On 7/31/25 12:19 PM, Konrad Dybcio wrote: >>>>> On 7/25/25 10:35 AM, Neil Armstrong wrote: >>>>>> The Adreno GPU Management Unit (GMU) can also scale DDR Bandwidth >>>>>> along >>>>>> the Frequency and Power Domain level, but by default we leave the >>>>>> OPP core scale the interconnect ddr path. >>>>>> >>>>>> Declare the Bus Control Modules (BCMs) and the corresponding >>>>>> parameters >>>>>> in the GPU info struct to allow the GMU to vote for the bandwidth. >>>>>> >>>>>> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> >>>>>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> >>>>>> --- >>>>>> Changes in v2: >>>>>> - Used proper ACV perfmode bit/freq >>>>>> - Link to v1: https://lore.kernel.org/r/20250721-topic-x1e80100- >>>>>> gpu-bwvote-v1-1-946619b0f73a@linaro.org >>>>>> --- >>>>>> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 11 +++++++++++ >>>>>> 1 file changed, 11 insertions(+) >>>>>> >>>>>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/ >>>>>> gpu/drm/msm/adreno/a6xx_catalog.c >>>>>> index >>>>>> 00e1afd46b81546eec03e22cda9e9a604f6f3b60..892f98b1f2ae582268adebd758437ff60456cdd5 100644 >>>>>> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >>>>>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >>>>>> @@ -1440,6 +1440,17 @@ static const struct adreno_info a7xx_gpus[] = { >>>>>> .pwrup_reglist = &a7xx_pwrup_reglist, >>>>>> .gmu_chipid = 0x7050001, >>>>>> .gmu_cgc_mode = 0x00020202, >>>>>> + .bcms = (const struct a6xx_bcm[]) { >>>>>> + { .name = "SH0", .buswidth = 16 }, >>>>>> + { .name = "MC0", .buswidth = 4 }, >>>>>> + { >>>>>> + .name = "ACV", >>>>>> + .fixed = true, >>>>>> + .perfmode = BIT(3), >>>>>> + .perfmode_bw = 16500000, >>>>> >>>>> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> >>>> >>>> Actually no, BIT(3) is for the CPU (OS), GPU should use BIT(2) > > You are right that BIT(2) is GPU specific, but that support was > commercialized from A7XX_GEN3. Anyway, the Win KMD uses BIT(2), so lets > use that in Linux too. > > I know some docs show BIT(2) support, but lets not bring in untested > configurations. Eh, then let's get the docs fixed if you don't trust them because we can't work like that.. FWIW this is information from per-platform RPMh cmd-db data Konrad ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2] drm/msm: adreno: a6xx: enable GMU bandwidth voting for x1e80100 GPU 2025-08-14 17:52 ` Konrad Dybcio @ 2025-08-15 22:15 ` Dmitry Baryshkov 2025-08-18 7:17 ` Akhil P Oommen 0 siblings, 1 reply; 11+ messages in thread From: Dmitry Baryshkov @ 2025-08-15 22:15 UTC (permalink / raw) To: Konrad Dybcio Cc: Akhil P Oommen, Neil Armstrong, Rob Clark, Sean Paul, Konrad Dybcio, Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang, Marijn Suijten, David Airlie, Simona Vetter, linux-arm-msm, dri-devel, freedreno, linux-kernel On Thu, Aug 14, 2025 at 07:52:13PM +0200, Konrad Dybcio wrote: > On 8/14/25 6:38 PM, Akhil P Oommen wrote: > > On 8/14/2025 7:56 PM, Neil Armstrong wrote: > >> Hi, > >> > >> On 14/08/2025 13:22, Konrad Dybcio wrote: > >>> On 8/14/25 1:21 PM, Konrad Dybcio wrote: > >>>> On 7/31/25 12:19 PM, Konrad Dybcio wrote: > >>>>> On 7/25/25 10:35 AM, Neil Armstrong wrote: > >>>>>> The Adreno GPU Management Unit (GMU) can also scale DDR Bandwidth > >>>>>> along > >>>>>> the Frequency and Power Domain level, but by default we leave the > >>>>>> OPP core scale the interconnect ddr path. > >>>>>> > >>>>>> Declare the Bus Control Modules (BCMs) and the corresponding > >>>>>> parameters > >>>>>> in the GPU info struct to allow the GMU to vote for the bandwidth. > >>>>>> > >>>>>> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> > >>>>>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> > >>>>>> --- > >>>>>> Changes in v2: > >>>>>> - Used proper ACV perfmode bit/freq > >>>>>> - Link to v1: https://lore.kernel.org/r/20250721-topic-x1e80100- > >>>>>> gpu-bwvote-v1-1-946619b0f73a@linaro.org > >>>>>> --- > >>>>>> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 11 +++++++++++ > >>>>>> 1 file changed, 11 insertions(+) > >>>>>> > >>>>>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/ > >>>>>> gpu/drm/msm/adreno/a6xx_catalog.c > >>>>>> index > >>>>>> 00e1afd46b81546eec03e22cda9e9a604f6f3b60..892f98b1f2ae582268adebd758437ff60456cdd5 100644 > >>>>>> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > >>>>>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > >>>>>> @@ -1440,6 +1440,17 @@ static const struct adreno_info a7xx_gpus[] = { > >>>>>> .pwrup_reglist = &a7xx_pwrup_reglist, > >>>>>> .gmu_chipid = 0x7050001, > >>>>>> .gmu_cgc_mode = 0x00020202, > >>>>>> + .bcms = (const struct a6xx_bcm[]) { > >>>>>> + { .name = "SH0", .buswidth = 16 }, > >>>>>> + { .name = "MC0", .buswidth = 4 }, > >>>>>> + { > >>>>>> + .name = "ACV", > >>>>>> + .fixed = true, > >>>>>> + .perfmode = BIT(3), > >>>>>> + .perfmode_bw = 16500000, > >>>>> > >>>>> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> > >>>> > >>>> Actually no, BIT(3) is for the CPU (OS), GPU should use BIT(2) > > > > You are right that BIT(2) is GPU specific, but that support was > > commercialized from A7XX_GEN3. Anyway, the Win KMD uses BIT(2), so lets > > use that in Linux too. > > > > I know some docs show BIT(2) support, but lets not bring in untested > > configurations. > > Eh, then let's get the docs fixed if you don't trust them because we can't > work like that.. > > FWIW this is information from per-platform RPMh cmd-db data If it comes from cmd-db, then we should be requesting it from the cmd-db driver rather than hardcoding it here. -- With best wishes Dmitry ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2] drm/msm: adreno: a6xx: enable GMU bandwidth voting for x1e80100 GPU 2025-08-15 22:15 ` Dmitry Baryshkov @ 2025-08-18 7:17 ` Akhil P Oommen 0 siblings, 0 replies; 11+ messages in thread From: Akhil P Oommen @ 2025-08-18 7:17 UTC (permalink / raw) To: Dmitry Baryshkov, Konrad Dybcio Cc: Neil Armstrong, Rob Clark, Sean Paul, Konrad Dybcio, Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang, Marijn Suijten, David Airlie, Simona Vetter, linux-arm-msm, dri-devel, freedreno, linux-kernel On 8/16/2025 3:45 AM, Dmitry Baryshkov wrote: > On Thu, Aug 14, 2025 at 07:52:13PM +0200, Konrad Dybcio wrote: >> On 8/14/25 6:38 PM, Akhil P Oommen wrote: >>> On 8/14/2025 7:56 PM, Neil Armstrong wrote: >>>> Hi, >>>> >>>> On 14/08/2025 13:22, Konrad Dybcio wrote: >>>>> On 8/14/25 1:21 PM, Konrad Dybcio wrote: >>>>>> On 7/31/25 12:19 PM, Konrad Dybcio wrote: >>>>>>> On 7/25/25 10:35 AM, Neil Armstrong wrote: >>>>>>>> The Adreno GPU Management Unit (GMU) can also scale DDR Bandwidth >>>>>>>> along >>>>>>>> the Frequency and Power Domain level, but by default we leave the >>>>>>>> OPP core scale the interconnect ddr path. >>>>>>>> >>>>>>>> Declare the Bus Control Modules (BCMs) and the corresponding >>>>>>>> parameters >>>>>>>> in the GPU info struct to allow the GMU to vote for the bandwidth. >>>>>>>> >>>>>>>> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> >>>>>>>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> >>>>>>>> --- >>>>>>>> Changes in v2: >>>>>>>> - Used proper ACV perfmode bit/freq >>>>>>>> - Link to v1: https://lore.kernel.org/r/20250721-topic-x1e80100- >>>>>>>> gpu-bwvote-v1-1-946619b0f73a@linaro.org >>>>>>>> --- >>>>>>>> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 11 +++++++++++ >>>>>>>> 1 file changed, 11 insertions(+) >>>>>>>> >>>>>>>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/ >>>>>>>> gpu/drm/msm/adreno/a6xx_catalog.c >>>>>>>> index >>>>>>>> 00e1afd46b81546eec03e22cda9e9a604f6f3b60..892f98b1f2ae582268adebd758437ff60456cdd5 100644 >>>>>>>> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >>>>>>>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >>>>>>>> @@ -1440,6 +1440,17 @@ static const struct adreno_info a7xx_gpus[] = { >>>>>>>> .pwrup_reglist = &a7xx_pwrup_reglist, >>>>>>>> .gmu_chipid = 0x7050001, >>>>>>>> .gmu_cgc_mode = 0x00020202, >>>>>>>> + .bcms = (const struct a6xx_bcm[]) { >>>>>>>> + { .name = "SH0", .buswidth = 16 }, >>>>>>>> + { .name = "MC0", .buswidth = 4 }, >>>>>>>> + { >>>>>>>> + .name = "ACV", >>>>>>>> + .fixed = true, >>>>>>>> + .perfmode = BIT(3), >>>>>>>> + .perfmode_bw = 16500000, >>>>>>> >>>>>>> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> >>>>>> >>>>>> Actually no, BIT(3) is for the CPU (OS), GPU should use BIT(2) >>> >>> You are right that BIT(2) is GPU specific, but that support was >>> commercialized from A7XX_GEN3. Anyway, the Win KMD uses BIT(2), so lets >>> use that in Linux too. >>> >>> I know some docs show BIT(2) support, but lets not bring in untested >>> configurations. >> >> Eh, then let's get the docs fixed if you don't trust them because we can't >> work like that.. >> >> FWIW this is information from per-platform RPMh cmd-db data > > If it comes from cmd-db, then we should be requesting it from the cmd-db > driver rather than hardcoding it here. Not really. This should be under the control of GPU driver. BIT(3) is correct for X1E. -Akhil. > ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2] drm/msm: adreno: a6xx: enable GMU bandwidth voting for x1e80100 GPU 2025-08-14 16:38 ` Akhil P Oommen 2025-08-14 17:52 ` Konrad Dybcio @ 2025-08-15 22:15 ` Dmitry Baryshkov 1 sibling, 0 replies; 11+ messages in thread From: Dmitry Baryshkov @ 2025-08-15 22:15 UTC (permalink / raw) To: Akhil P Oommen Cc: Neil Armstrong, Konrad Dybcio, Rob Clark, Sean Paul, Konrad Dybcio, Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang, Marijn Suijten, David Airlie, Simona Vetter, linux-arm-msm, dri-devel, freedreno, linux-kernel On Thu, Aug 14, 2025 at 10:08:26PM +0530, Akhil P Oommen wrote: > On 8/14/2025 7:56 PM, Neil Armstrong wrote: > > Hi, > > > > On 14/08/2025 13:22, Konrad Dybcio wrote: > >> On 8/14/25 1:21 PM, Konrad Dybcio wrote: > >>> On 7/31/25 12:19 PM, Konrad Dybcio wrote: > >>>> On 7/25/25 10:35 AM, Neil Armstrong wrote: > >>>>> The Adreno GPU Management Unit (GMU) can also scale DDR Bandwidth > >>>>> along > >>>>> the Frequency and Power Domain level, but by default we leave the > >>>>> OPP core scale the interconnect ddr path. > >>>>> > >>>>> Declare the Bus Control Modules (BCMs) and the corresponding > >>>>> parameters > >>>>> in the GPU info struct to allow the GMU to vote for the bandwidth. > >>>>> > >>>>> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> > >>>>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> > >>>>> --- > >>>>> Changes in v2: > >>>>> - Used proper ACV perfmode bit/freq > >>>>> - Link to v1: https://lore.kernel.org/r/20250721-topic-x1e80100- > >>>>> gpu-bwvote-v1-1-946619b0f73a@linaro.org > >>>>> --- > >>>>> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 11 +++++++++++ > >>>>> 1 file changed, 11 insertions(+) > >>>>> > >>>>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/ > >>>>> gpu/drm/msm/adreno/a6xx_catalog.c > >>>>> index > >>>>> 00e1afd46b81546eec03e22cda9e9a604f6f3b60..892f98b1f2ae582268adebd758437ff60456cdd5 100644 > >>>>> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > >>>>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > >>>>> @@ -1440,6 +1440,17 @@ static const struct adreno_info a7xx_gpus[] = { > >>>>> .pwrup_reglist = &a7xx_pwrup_reglist, > >>>>> .gmu_chipid = 0x7050001, > >>>>> .gmu_cgc_mode = 0x00020202, > >>>>> + .bcms = (const struct a6xx_bcm[]) { > >>>>> + { .name = "SH0", .buswidth = 16 }, > >>>>> + { .name = "MC0", .buswidth = 4 }, > >>>>> + { > >>>>> + .name = "ACV", > >>>>> + .fixed = true, > >>>>> + .perfmode = BIT(3), > >>>>> + .perfmode_bw = 16500000, > >>>> > >>>> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> > >>> > >>> Actually no, BIT(3) is for the CPU (OS), GPU should use BIT(2) > > You are right that BIT(2) is GPU specific, but that support was > commercialized from A7XX_GEN3. Anyway, the Win KMD uses BIT(2), so lets > use that in Linux too. > > I know some docs show BIT(2) support, but lets not bring in untested > configurations. > I'd say, I can't parse the comment. Should we use BIT(2) or BIT(3) here? > -Akhil. > > >> > >> This is *very* platform-dependent, goes without saying.. > >> > >> I see BIT(2) is also valid for X1P4 > > > > > > I'm confused, Akhil can you confirm ? > > > > Neil> > >> > >> Konrad > > > -- With best wishes Dmitry ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2] drm/msm: adreno: a6xx: enable GMU bandwidth voting for x1e80100 GPU 2025-07-25 8:35 [PATCH v2] drm/msm: adreno: a6xx: enable GMU bandwidth voting for x1e80100 GPU Neil Armstrong 2025-07-31 10:19 ` Konrad Dybcio @ 2025-08-18 7:13 ` Akhil P Oommen 1 sibling, 0 replies; 11+ messages in thread From: Akhil P Oommen @ 2025-08-18 7:13 UTC (permalink / raw) To: Neil Armstrong, Rob Clark, Sean Paul, Konrad Dybcio, Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang, Marijn Suijten, David Airlie, Simona Vetter Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel, Dmitry Baryshkov On 7/25/2025 2:05 PM, Neil Armstrong wrote: > The Adreno GPU Management Unit (GMU) can also scale DDR Bandwidth along > the Frequency and Power Domain level, but by default we leave the > OPP core scale the interconnect ddr path. > > Declare the Bus Control Modules (BCMs) and the corresponding parameters > in the GPU info struct to allow the GMU to vote for the bandwidth. > > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> > Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> -Akhil > --- > Changes in v2: > - Used proper ACV perfmode bit/freq > - Link to v1: https://lore.kernel.org/r/20250721-topic-x1e80100-gpu-bwvote-v1-1-946619b0f73a@linaro.org > --- > drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > index 00e1afd46b81546eec03e22cda9e9a604f6f3b60..892f98b1f2ae582268adebd758437ff60456cdd5 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > @@ -1440,6 +1440,17 @@ static const struct adreno_info a7xx_gpus[] = { > .pwrup_reglist = &a7xx_pwrup_reglist, > .gmu_chipid = 0x7050001, > .gmu_cgc_mode = 0x00020202, > + .bcms = (const struct a6xx_bcm[]) { > + { .name = "SH0", .buswidth = 16 }, > + { .name = "MC0", .buswidth = 4 }, > + { > + .name = "ACV", > + .fixed = true, > + .perfmode = BIT(3), > + .perfmode_bw = 16500000, > + }, > + { /* sentinel */ }, > + }, > }, > .preempt_record_size = 4192 * SZ_1K, > .speedbins = ADRENO_SPEEDBINS( > > --- > base-commit: 97987520025658f30bb787a99ffbd9bbff9ffc9d > change-id: 20250721-topic-x1e80100-gpu-bwvote-9fc4690fe5e3 > > Best regards, ^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2025-08-18 7:17 UTC | newest] Thread overview: 11+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-07-25 8:35 [PATCH v2] drm/msm: adreno: a6xx: enable GMU bandwidth voting for x1e80100 GPU Neil Armstrong 2025-07-31 10:19 ` Konrad Dybcio 2025-08-14 11:21 ` Konrad Dybcio 2025-08-14 11:22 ` Konrad Dybcio 2025-08-14 14:26 ` Neil Armstrong 2025-08-14 16:38 ` Akhil P Oommen 2025-08-14 17:52 ` Konrad Dybcio 2025-08-15 22:15 ` Dmitry Baryshkov 2025-08-18 7:17 ` Akhil P Oommen 2025-08-15 22:15 ` Dmitry Baryshkov 2025-08-18 7:13 ` Akhil P Oommen
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).