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AJvYcCXFDUVGKrvFtgsSDdHCBz8DWCUWrSisfO1ri5SMOyo8X91aHr4BpTCAPjTBjgr6ujfqq9dKrTsVNXbjHh2IyFDExMZn4ApMpJ1Mtopz X-Gm-Message-State: AOJu0YxttHPE2eSR8sZk0Zq+5lb9XNjDbYCiyoLEiakfRDRvxPzBaw5/ r+8r0zpcqSBhT3bGMY1i1V6QhIoLWDyYqt+iu//wa9xqPfGQ3JzL X-Google-Smtp-Source: AGHT+IFc0po3mo4O9fpfmCnNRPHDYRjKwDTdjNmK8sh/+kEbHxstRUb///5F+1qJ3wH6KwvLikxDvg== X-Received: by 2002:a17:907:e2df:b0:a7d:a031:7bb2 with SMTP id a640c23a62f3a-a839295605bmr878537566b.40.1724091321672; Mon, 19 Aug 2024 11:15:21 -0700 (PDT) Received: from [192.168.1.100] ([46.248.82.114]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a83838d00f0sm656546266b.87.2024.08.19.11.15.20 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 19 Aug 2024 11:15:21 -0700 (PDT) Message-ID: Date: Mon, 19 Aug 2024 20:15:19 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH] iommu/amd: Modify set_dte_entry() to use 128-bit cmpxchg operation Content-Language: en-US To: Suravee Suthikulpanit , linux-kernel@vger.kernel.org, iommu@lists.linux.dev Cc: joro@8bytes.org, robin.murphy@arm.com, vasant.hegde@amd.com, jgg@nvidia.com, kevin.tian@intel.com, jon.grimm@amd.com, santosh.shukla@amd.com, pandoh@google.com, kumaranand@google.com References: <20240819161839.4657-1-suravee.suthikulpanit@amd.com> From: Uros Bizjak In-Reply-To: <20240819161839.4657-1-suravee.suthikulpanit@amd.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 19. 08. 24 18:18, Suravee Suthikulpanit wrote: > The current implementation does not follow the 128-bit write > requirement to update DTE as specified in the AMD I/O Virtualization > Techonology (IOMMU) Specification. > > In addition, the function is used to program several DTE fields > (e.g. stage1 table, stage2 table, domain id, and etc.), which is > difficult to keep track with current implementation. > > Therefore, introduce new a new dte256_t data type and a helper function > update_dte_256(), which uses two try_cmpxchg128 operations to update > 256-bit DTE. > > Also, separate logic for setting up the GCR3 Table Root Pointer, GIOV, GV, > GLX, and GuestPagingMode into another helper function set_dte_gcr3_table(). > > Signed-off-by: Suravee Suthikulpanit [...] > +static void update_dte256(struct amd_iommu *iommu, u16 devid, struct dte256 *new) > +{ > + struct dev_table_entry *dev_table = get_dev_table(iommu); > + struct dte256 *ptr = (struct dte256 *)&dev_table[devid]; > + struct dte256 old = { > + .qw_lo.data = ptr->qw_lo.data, > + .qw_hi.data = ptr->qw_hi.data, > + }; > + > + /* Update qw_lo */ > + if (!try_cmpxchg128(&ptr->qw_lo.data, &old.qw_lo.data, new->qw_lo.data)) > + goto err_out; > + > + /* Update qw_hi */ > + if (!try_cmpxchg128(&ptr->qw_hi.data, &old.qw_hi.data, new->qw_hi.data)) { > + /* Restore qw_lo */ > + try_cmpxchg128(&ptr->qw_lo.data, &new->qw_lo.data, old.qw_lo.data); You should use plain cmpxchg128() when the result is unused. Uros.