RE: [PATCH v3 2/6] irqchip: Add interrupt controller support for Realtek DHC SoCs

James Tai [戴志峰]
2023-12-22T06:21:11Z

Hi Thomas,

>>>On Wed, Nov 29 2023 at 13:43, James Tai wrote:
>>>> +static inline void realtek_intc_clear_ints_bit(struct
>>>> +realtek_intc_data *data, int bit) {
>>>> + writel(BIT(bit) & ~1, data->base + data->info->isr_offset);
>>>
>>>That '& ~1' solves what aside of preventing bit 0 from being written?
>>>
>> The ISR register uses bit 0 to clear or set ISR status.
>> Write 0 to clear bits and write 1 to set bits.
>> Therefore, to clear the interrupt status, bit 0 should consistently be
>> set to '0'.
>
>And how does BIT(bit) with 1 <= bit <= 31 end up having bit 0 set?
>
>Also a comment explaining the reasoning here would be helpful.

To perform the clearing action in the ISR register, it's essential that bit 0 remains set to 0.
This is because bit 0 in the ISR register has a specific function for controlling the interrupt status.
When BIT(bit) is used with 1 <= bit <= 31, it generates a bitmask with only that particular bit set to 1, and all other bits, including bit 0, set to 0.
The '& ~1' operation is then applied to ensure that even if bit 0 was somehow set, it will be cleared, maintaining the register's functionality.

For example, suppose the current value of the ISR register is 0x4, and we want to clear bit 3.
In that case, writing 0x4 (which represents bit 3 set to 1) to the ISR register will clear bit 3.

Thanks for your feedback.

Regards,
James