From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E6002308F32 for ; Tue, 4 Aug 2026 21:47:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785880032; cv=none; b=ZTqL5QEviIJQWAEjw+faKTTyfS1MDzMtp+TNW43TzrWUr/MJ1IAW12eQ6anmXT2QTwwzZAbrTtuVvCairvdraCC2YxrzvZ3euObWRqdN2mW8HRtX2IH2Pb1Q/BQFlKHSv2SBJr5/eFLDbHgUoSmh9ME3HjwkbY/TEsIO+rUxJJs= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785880032; c=relaxed/simple; bh=Kyy1S2eYWB1eVGhXTTb8uaGQ41RPG9dDs3Q75QJ9JPM=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=knkhJwL1abn3UzzrzG0PCWeeMMHhGLQKXQkTWa2VL16v6zURVTZtSOddsBeluS2AxYbHHnidDhGW1Nfif766HJq1jtnMl96DzZy7gG77I+7Sue7Cpd7LqsCtxF2DJg9L5rUuuDNF2YRFIy+87cA08YYeqjeYzkRlBtQedz+Hvyw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=anIpDvCb; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="anIpDvCb" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 82C651F000E9; Tue, 4 Aug 2026 21:47:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1785880031; bh=b4Tb1oIjWwUxjFhTBFD/zWgNtoh6N0RIyHfctUTX0zA=; h=Date:Subject:To:Cc:References:From:In-Reply-To; b=anIpDvCbLz1al5lEwizeQ9TRqV0GfEwS3ElIBSUJbK9mwo6IQiwKGEfx9O3lKpIe5 6rLdNm+ZejMW8uukRRb/U3GnkcSRU5N4Qgrcrbhej0DmvEgRPRShipVaDF+ifEO29O un+yx37gRX/Ir3fQ5Occp8CBb7sXLKEvdaBZCGGb0EBsAiEBMJtcJ2rPre27JqQaow j5dDnMSADfw7+CXmEYORzsAS3nPPS4nYt4Cs/K35WAbVCEZAfOOtMTVDYKH/DNuyCz zcBZ3GzUGKJAdAqEAhdP1CCEk3DSYInSPWkW6cpK9Ae6V+Fn5ShxZOAaJZfpi5l3cq q6FXjyJt6QDtQ== Message-ID: Date: Tue, 4 Aug 2026 23:47:03 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC v2 PATCH 0/16] Optimize this_cpu_*() ops for non-x86 (ARM64 for this series) To: "Christoph Lameter (Ampere)" Cc: "Lorenzo Stoakes (ARM)" , Mark Rutland , Yang Shi , Ryan Roberts , dennis@kernel.org, tj@kernel.org, urezki@gmail.com, catalin.marinas@arm.com, will@kernel.org, akpm@linux-foundation.org, hca@linux.ibm.com, gor@linux.ibm.com, agordeev@linux.ibm.com, linux-mm@kvack.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Linus Torvalds , Jason Gunthorpe References: <20260715180455.515692-1-yang@os.amperecomputing.com> <0344c559-1959-4531-9265-d5a5180eb7cd@arm.com> <25d1e09b-53e4-7cd5-87db-b58437e4e690@gentwo.org> <4887267b-dc26-4c33-96ca-8dff054a0d1f@kernel.org> <63ea8156-a109-b2a2-6d35-1c17ad7f1a9d@gentwo.org> <84b31836-1d10-4bec-a469-468b91fd4645@kernel.org> <9f146ce0-4adc-0c00-a2d8-c01b47edc9d1@gentwo.org> From: "David Hildenbrand (Arm)" Content-Language: en-US Autocrypt: addr=david@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 8/4/26 23:25, Christoph Lameter (Ampere) wrote: > On Tue, 4 Aug 2026, David Hildenbrand (Arm) wrote: > >>> rather hacky restart logic. It relies on a long preemable and postscript >>> to each per cpu operations. > >> But I am sure you did you homework and have data to back up your claims. Please >> share that data, because I am very curious. > > The comparison here is a single instruction on one side and abnd the per > cpu operation prefixed with a preeamble and another instruction / set of > instructions on the other side. > > Even if its only one before and one after then we are still looking at 3 > instructions instead of one. This is a frequently used operation in the > VM. > > You need data to show that one instruction is faster than 3??? I want you to show that the difference *matters* in *practice* enough that we should *care* about accepting the additional *complexity*. No hand-waving about "3 > 1". IIRC people were asking that previously but received no results back. So to be clear: claiming that the additional instructions are unacceptable I'd expect something minimal like: "removing these 3 instructions speeds up micro-benchmark (a, b, c) by X% and macro-benchmarks (d, e, f) by Y% compared to Mark's approach". Maybe there really is a big difference. > >> Mark's solution is the obvious improvement to the problem, doing it just like >> s390 already does. > > Well there is interest by the S390 folks to move to what we proposed from > what I can tell. Heiko said that as reply to v1, bit he's been replying a lot on Mark's patches. Only Heiko can tell. (on CC) > > >> If the proposed solution has a significant benefit over Mark's solution it could >> be discussed as a next step; and it must be backed with sufficient data to >> warrant all this complexity here. > > You cannot accept that one instruction is faster than the same > instruction prefixed with another and something else at its tail? I am pretty sure that you got exactly what I meant, you likely just don't have the data to back it up. Proof me wrong! -- Cheers, David