From: Santhosh Kumar K <s-k6@ti.com>
To: Pratyush Yadav <pratyush@kernel.org>
Cc: <miquel.raynal@bootlin.com>, <broonie@kernel.org>,
<vigneshr@ti.com>, <marex@denx.de>, <computersforpeace@gmail.com>,
<grmoore@opensource.altera.com>, <theo.lebrun@bootlin.com>,
<linux-spi@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<praneeth@ti.com>, <p-mantena@ti.com>, <a-dutta@ti.com>,
<u-kumar1@ti.com>, <s-k6@ti.com>
Subject: Re: [PATCH 3/4] spi: cadence-quadspi: Fix cqspi_setup_flash()
Date: Fri, 5 Sep 2025 16:34:10 +0530 [thread overview]
Message-ID: <ea97b0b4-3467-4e18-9e8c-80b75e067f3d@ti.com> (raw)
In-Reply-To: <mafs0ms7ath3l.fsf@kernel.org>
Hello,
On 04/09/25 20:11, Pratyush Yadav wrote:
> On Thu, Sep 04 2025, Santhosh Kumar K wrote:
>
>> The 'max_cs' stores the largest chip select number. It should only
>> be updated when the current 'cs' is greater than existing 'max_cs'. So,
>> fix the condition accordingly.
>>
>> Fixes: 0f3841a5e115 ("spi: cadence-qspi: report correct number of chip-select")
>> Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
>> ---
>> drivers/spi/spi-cadence-quadspi.c | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
>> index 447a32a08a93..da3ec15abb3e 100644
>> --- a/drivers/spi/spi-cadence-quadspi.c
>> +++ b/drivers/spi/spi-cadence-quadspi.c
>> @@ -1722,7 +1722,7 @@ static const struct spi_controller_mem_caps cqspi_mem_caps = {
>>
>> static int cqspi_setup_flash(struct cqspi_st *cqspi)
>> {
>> - unsigned int max_cs = cqspi->num_chipselect - 1;
>> + unsigned int max_cs = 0;
>> struct platform_device *pdev = cqspi->pdev;
>> struct device *dev = &pdev->dev;
>> struct cqspi_flash_pdata *f_pdata;
>> @@ -1740,7 +1740,7 @@ static int cqspi_setup_flash(struct cqspi_st *cqspi)
>> if (cs >= cqspi->num_chipselect) {
>> dev_err(dev, "Chip select %d out of range.\n", cs);
>> return -EINVAL;
>> - } else if (cs < max_cs) {
>> + } else if (cs > max_cs) {
>
> Makes sense. Out of curiosity, are you using multiple CS in a real use
> case or is this only theoretical?
Real use case, Pratyush - we have both OSPI NOR and QSPI NAND in our
new AM62Lx EVM - CS0 and CS3 respectively.
>
> Also nit: this could be simplified to:
>
> if (cs >= cqspi->num_chipselect) {
> dev_err(dev, "Chip select %d out of range.\n", cs);
> return -EINVAL;
> }
>
> max_cs = max_t(unsigned int, cs, max_cs);
>
> but I think it is fine either way.
Yeah, this one's simpler, I'll go with this. Thanks!
Regards,
Santhosh.
>
> Reviewed-by: Pratyush Yadav <pratyush@kernel.org>
>
>> max_cs = cs;
>> }
>
next prev parent reply other threads:[~2025-09-05 11:04 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-04 13:31 [PATCH 0/4] Miscellaneous fixes and clean-ups Santhosh Kumar K
2025-09-04 13:31 ` [PATCH 1/4] spi: cadence-quadspi: Flush posted register writes before INDAC access Santhosh Kumar K
2025-09-04 14:35 ` Pratyush Yadav
2025-09-04 13:31 ` [PATCH 2/4] spi: cadence-quadspi: Flush posted register writes before DAC access Santhosh Kumar K
2025-09-04 14:36 ` Pratyush Yadav
2025-09-04 13:31 ` [PATCH 3/4] spi: cadence-quadspi: Fix cqspi_setup_flash() Santhosh Kumar K
2025-09-04 14:41 ` Pratyush Yadav
2025-09-05 11:04 ` Santhosh Kumar K [this message]
2025-09-04 15:32 ` Théo Lebrun
2025-09-05 11:04 ` Santhosh Kumar K
2025-09-04 13:31 ` [PATCH 4/4] spi: cadence-quadspi: Use BIT() macros where possible Santhosh Kumar K
2025-09-04 14:49 ` Pratyush Yadav
2025-09-05 11:04 ` Santhosh Kumar K
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