From: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
To: "David E. Box" <david.e.box@linux.intel.com>
Cc: irenic.rajneesh@gmail.com, ilpo.jarvinen@linux.intel.com,
srinivas.pandruvada@linux.intel.com, xi.pardee@linux.intel.com,
hansg@kernel.org, linux-kernel@vger.kernel.org,
platform-driver-x86@vger.kernel.org
Subject: Re: [PATCH V2 06/17] platform/x86/intel/pmt: Unify header fetch and add ACPI source
Date: Tue, 7 Apr 2026 15:14:15 +0300 (EEST) [thread overview]
Message-ID: <eaaa0f6c-36ea-d9f6-a8b1-0c91551a1234@linux.intel.com> (raw)
In-Reply-To: <20260325014819.1283566-7-david.e.box@linux.intel.com>
On Tue, 24 Mar 2026, David E. Box wrote:
> Allow the PMT class to read discovery headers from either PCI MMIO or
> ACPI-provided entries, depending on the discovery source. The new
> source-aware fetch helper retrieves the first two QWORDs for both paths
> while keeping the mapped discovery table available for users such as
> crashlog.
>
> Split intel_pmt_populate_entry() into source-specific resolvers:
> - pmt_resolve_access_pci(): handles both ACCESS_LOCAL and ACCESS_BARID
> for PCI-backed devices and sets entry->pcidev. Same existing
> functionality.
> - pmt_resolve_access_acpi(): handles only ACCESS_BARID for ACPI-backed
> devices, rejecting ACCESS_LOCAL which has no valid semantics without
> a physical discovery resource.
>
> This maintains existing PCI behavior and makes no functional changes
> for PCI devices.
>
> Signed-off-by: David E. Box <david.e.box@linux.intel.com>
> ---
>
> V2 changes:
> - In pmt_resolve_access_acpi(), moved dev_err() call to single line
> instead of split across two lines
> - Restructured error handling in intel_pmt_populate_entry(), moving error
> returns from after switch/case into each case statement for better
> readability
> - Addressed Ilpo's feedback on error message formatting and error
> handling patterns
>
> drivers/platform/x86/intel/pmt/class.c | 123 +++++++++++++++++++++++--
> 1 file changed, 114 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/platform/x86/intel/pmt/class.c b/drivers/platform/x86/intel/pmt/class.c
> index 3fcea6a6e763..64678f55a20e 100644
> --- a/drivers/platform/x86/intel/pmt/class.c
> +++ b/drivers/platform/x86/intel/pmt/class.c
> @@ -205,9 +205,9 @@ struct class intel_pmt_class = {
> };
> EXPORT_SYMBOL_GPL(intel_pmt_class);
>
> -static int intel_pmt_populate_entry(struct intel_pmt_entry *entry,
> - struct intel_vsec_device *ivdev,
> - int idx)
> +static int pmt_resolve_access_pci(struct intel_pmt_entry *entry,
> + struct intel_vsec_device *ivdev,
> + int idx)
> {
> struct pci_dev *pci_dev = to_pci_dev(ivdev->dev);
> struct device *dev = &ivdev->auxdev.dev;
> @@ -287,6 +287,81 @@ static int intel_pmt_populate_entry(struct intel_pmt_entry *entry,
> }
>
> entry->pcidev = pci_dev;
> +
> + return 0;
> +}
> +
> +static int pmt_resolve_access_acpi(struct intel_pmt_entry *entry,
> + struct intel_vsec_device *ivdev)
> +{
> + struct pci_dev *pci_dev = NULL;
> + struct device *dev = &ivdev->auxdev.dev;
> + struct intel_pmt_header *header = &entry->header;
> + u8 bir;
> +
> + if (dev_is_pci(ivdev->dev))
> + pci_dev = to_pci_dev(ivdev->dev);
> +
> + /*
> + * The base offset should always be 8 byte aligned.
> + *
> + * For non-local access types the lower 3 bits of base offset
> + * contains the index of the base address register where the
> + * telemetry can be found.
> + */
> + bir = GET_BIR(header->base_offset);
> +
> + switch (header->access_type) {
> + case ACCESS_BARID:
> + /* ACPI platform drivers use base_addr */
> + if (ivdev->base_addr) {
> + entry->base_addr = ivdev->base_addr +
> + GET_ADDRESS(header->base_offset);
> + break;
> + }
> +
> + /* If base_addr is not provided, then this is an ACPI companion device */
> + if (!pci_dev) {
> + dev_err(dev, "ACCESS_BARID requires PCI BAR resources or base_addr\n");
> + return -EINVAL;
> + }
> +
> + entry->base_addr = pci_resource_start(pci_dev, bir) +
> + GET_ADDRESS(header->base_offset);
Could you align this to pci_.
> + break;
> + default:
> + dev_err(dev, "Unsupported access type %d for ACPI based PMT\n",
> + header->access_type);
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +static int intel_pmt_populate_entry(struct intel_pmt_entry *entry,
> + struct intel_vsec_device *ivdev,
> + int idx)
> +{
> + struct intel_pmt_header *header = &entry->header;
> + struct device *dev = &ivdev->auxdev.dev;
> + int ret;
> +
> + switch (ivdev->src) {
> + case INTEL_VSEC_DISC_PCI:
> + ret = pmt_resolve_access_pci(entry, ivdev, idx);
> + if (ret)
> + return ret;
> + break;
> + case INTEL_VSEC_DISC_ACPI:
> + ret = pmt_resolve_access_acpi(entry, ivdev);
> + if (ret)
> + return ret;
> + break;
> + default:
> + dev_err(dev, "Unknown discovery source: %d\n", ivdev->src);
> + return -EINVAL;
> + }
> +
> entry->guid = header->guid;
> entry->size = header->size;
> entry->cb = ivdev->priv_data;
> @@ -371,18 +446,48 @@ static int intel_pmt_dev_register(struct intel_pmt_entry *entry,
> return ret;
> }
>
> +static int pmt_get_headers(struct intel_vsec_device *ivdev, int idx,
> + struct intel_pmt_entry *entry, u64 headers[2])
> +{
> + struct device *dev = &ivdev->auxdev.dev;
> +
> + switch (ivdev->src) {
> + case INTEL_VSEC_DISC_PCI: {
> + void __iomem *disc_table;
> +
> + disc_table = devm_ioremap_resource(dev, &ivdev->resource[idx]);
> + if (IS_ERR(disc_table))
> + return PTR_ERR(disc_table);
> +
> + memcpy_fromio(headers, disc_table, 2 * sizeof(u64));
> +
> + /* Used by crashlog driver */
> + entry->disc_table = disc_table;
> +
> + return 0;
> + }
> + case INTEL_VSEC_DISC_ACPI:
> + memcpy(headers, &ivdev->acpi_disc[idx][0], 2 * sizeof(u64));
You seem to repeat literal 2 when you mean the size of the headers so it
would warrant a define (and perhaps using sizeof(headers) here with the
memcpy() if it works with headers[2] being passed in as an array, I'm not
sure how C handles that case).
It was in the earlier patch too as literal.
--
i.
> +
> + return 0;
> + default:
> + dev_err(dev, "Unknown discovery source type: %d\n", ivdev->src);
> + break;
> + }
> +
> + return -EINVAL;
> +}
> +
> static int pmt_read_header(struct intel_vsec_device *ivdev, int idx,
> struct intel_pmt_entry *entry)
> {
> struct intel_pmt_header *header = &entry->header;
> - struct device *dev = &ivdev->auxdev.dev;
> u64 headers[2];
> + int ret;
>
> - entry->disc_table = devm_ioremap_resource(dev, &ivdev->resource[idx]);
> - if (IS_ERR(entry->disc_table))
> - return PTR_ERR(entry->disc_table);
> -
> - memcpy_fromio(headers, entry->disc_table, 2 * sizeof(u64));
> + ret = pmt_get_headers(ivdev, idx, entry, headers);
> + if (ret)
> + return ret;
>
> header->access_type = FIELD_GET(PMT_ACCESS_TYPE, headers[0]);
> header->telem_type = FIELD_GET(PMT_TELEM_TYPE, headers[0]);
>
next prev parent reply other threads:[~2026-04-07 12:14 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-25 1:48 [PATCH V2 00/17] Add ACPI-based PMT discovery support for Intel PMC David E. Box
2026-03-25 1:48 ` [PATCH V2 01/17] platform/x86/intel/pmt: Add pre/post decode hooks around header parsing David E. Box
2026-03-25 1:48 ` [PATCH V2 02/17] platform/x86/intel/pmt/crashlog: Split init into pre-decode David E. Box
2026-03-25 1:48 ` [PATCH V2 03/17] platform/x86/intel/pmt/telemetry: Move overlap check to post-decode hook David E. Box
2026-04-07 11:05 ` Ilpo Järvinen
2026-03-25 1:48 ` [PATCH V2 04/17] platform/x86/intel/pmt: Move header decode into common helper David E. Box
2026-04-07 11:05 ` Ilpo Järvinen
2026-03-25 1:48 ` [PATCH V2 05/17] platform/x86/intel/pmt: Pass discovery index instead of resource David E. Box
2026-04-07 11:07 ` Ilpo Järvinen
2026-03-25 1:48 ` [PATCH V2 06/17] platform/x86/intel/pmt: Unify header fetch and add ACPI source David E. Box
2026-04-07 12:14 ` Ilpo Järvinen [this message]
2026-03-25 1:48 ` [PATCH V2 07/17] platform/x86/intel/pmc: Add PMC SSRAM Kconfig description David E. Box
2026-04-07 12:16 ` Ilpo Järvinen
2026-03-25 1:48 ` [PATCH V2 08/17] platform/x86/intel/pmc: Add ACPI PWRM telemetry driver for Nova Lake S David E. Box
2026-04-07 12:56 ` Ilpo Järvinen
2026-03-25 1:48 ` [PATCH V2 09/17] platform/x86/intel/pmc/ssram: Rename probe and PCI ID table for consistency David E. Box
2026-03-25 1:48 ` [PATCH V2 10/17] platform/x86/intel/pmc/ssram: Use fixed-size static pmc array David E. Box
2026-04-07 13:08 ` Ilpo Järvinen
2026-03-25 1:48 ` [PATCH V2 11/17] platform/x86/intel/pmc/ssram: Refactor DEVID/PWRMBASE extraction into helper David E. Box
2026-04-07 13:18 ` Ilpo Järvinen
2026-03-25 1:48 ` [PATCH V2 12/17] platform/x86/intel/pmc/ssram: Add PCI platform data David E. Box
2026-03-25 1:48 ` [PATCH V2 13/17] platform/x86/intel/pmc/ssram: Refactor memory barrier for reentrant probe David E. Box
2026-03-25 1:48 ` [PATCH V2 14/17] platform/x86/intel/pmc/ssram_telemetry: Fix cleanup pattern for __free() variables David E. Box
2026-04-07 13:33 ` Ilpo Järvinen
2026-04-17 22:28 ` David Box
2026-03-25 1:48 ` [PATCH V2 15/17] platform/x86/intel/pmc/ssram: Add ACPI discovery scaffolding David E. Box
2026-03-25 1:48 ` [PATCH V2 16/17] platform/x86/intel/pmc/ssram: Make PMT registration optional David E. Box
2026-03-25 1:48 ` [PATCH V2 17/17] platform/x86/intel/pmc: Add NVL PCI IDs for SSRAM telemetry discovery David E. Box
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