From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D9EB6372B25 for ; Wed, 8 Jul 2026 14:54:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783522445; cv=none; b=osC7LdpCTGY8MNHLnTyRh6jhpiTVcnLlue+CYv+2idrKd1dPL7RCcPsGK11zXxMPpM2ByGT41lIpmLOCQM2gLSj7cN8qNdWp5CcrMNHZJID7xmcNJyb4UPyh+jIMleAkUt62A1bUbyvqBqG82XM0asZ0dlEpi7cIAbes5FocKWo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783522445; c=relaxed/simple; bh=AcjH9SdpY3q8KEK0I3lS3ZGt8lxh8eDzLRv5cCg3MxE=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=W8a37s858hAA3Yl1NAwPDPGfFlS6e4ufXd9vkPf3T0E8A64Nao2npkbuDxpUU+aHysJD8/UrpTi0n8BnWasUlbfr16WTbvAMvEYU0cniILtNhh79YtblvkOedM1KKhtb1uWeg/+3UxvHctpVRGpV//S4NdC3Wmj5CaVkoGWjR50= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=JvCChG4O; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="JvCChG4O" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6498A1CDD; Wed, 8 Jul 2026 07:53:58 -0700 (PDT) Received: from [10.57.40.57] (unknown [10.57.40.57]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 485F93F7B4; Wed, 8 Jul 2026 07:54:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1783522442; bh=AcjH9SdpY3q8KEK0I3lS3ZGt8lxh8eDzLRv5cCg3MxE=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=JvCChG4OSuivC3Xf/PYguCGP8vc6OJahpyxXERigM45LIuL7Uu9uHfybLD+9UnzB+ F3p4XuN70nj9yuaFRH9l3gaLgCJL/2QrKzbgAQC/as628RQD5wcochQ6Vu1HZIi2y+ 5WoQArH696XYwtqTAdcev+FOYFLD55HAt2iD98Ug= Message-ID: Date: Wed, 8 Jul 2026 15:53:59 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 3/6] arm64: cpufeature: Extend bbml2_noabort support list Content-Language: en-GB To: Linu Cherian , Catalin Marinas , Will Deacon , Ryan Roberts , Kevin Brodsky , Anshuman Khandual , Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20260708144331.679816-1-linu.cherian@arm.com> <20260708144331.679816-4-linu.cherian@arm.com> From: Suzuki K Poulose In-Reply-To: <20260708144331.679816-4-linu.cherian@arm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 08/07/2026 15:43, Linu Cherian wrote: > Add below cpus to the midr list, which supports > BBML2_NOABORT. > > Cortex A520(AE) > Cortex A715 > Cortex A720(AE) > Cortex A725 > Neoverse N3 > C1-Nano > C1-Pro > C1-Ultra > C1-Premium > > C1-Ultra and C1-Premium both suffer from erratum 3683289, > where Break-Before-Make must be followed to avoid a livelock. > For both CPUs, the erratum is fixed from r1p1. > Hence we do not enable BBML2_NOABORT for CPU revisions <= r1p0. Please could you also update the list of errata here : Documentation/arch/arm64/silicon-errata.rst > > The relevant SDENs are: > * C1-Ultra: https://developer.arm.com/documentation/111077/9-00/ > * C1-Premium: https://developer.arm.com/documentation/111078/9-00/ > > Signed-off-by: Linu Cherian > --- > arch/arm64/kernel/cpufeature.c | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index 9a22df0c5120..adcabea80fcb 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -2152,6 +2152,15 @@ bool cpu_supports_bbml2_noabort(void) > MIDR_ALL_VERSIONS(MIDR_NVIDIA_OLYMPUS), > MIDR_ALL_VERSIONS(MIDR_AMPERE1), > MIDR_ALL_VERSIONS(MIDR_AMPERE1A), > + MIDR_ALL_VERSIONS(MIDR_CORTEX_A520AE), > + MIDR_ALL_VERSIONS(MIDR_CORTEX_A715), > + MIDR_ALL_VERSIONS(MIDR_CORTEX_A720AE), > + MIDR_ALL_VERSIONS(MIDR_CORTEX_A725), > + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N3), > + MIDR_ALL_VERSIONS(MIDR_C1_NANO), > + MIDR_ALL_VERSIONS(MIDR_C1_PRO), And mention it here, so that it is evident from the code alone ? > + MIDR_REV_RANGE(MIDR_C1_ULTRA, 1, 1, 0xf), > + MIDR_REV_RANGE(MIDR_C1_PREMIUM, 1, 1, 0xf), Suzuki > {} > }; >