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Fri, 28 Feb 2025 11:13:25 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 51SBDOEi011059 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 28 Feb 2025 11:13:24 GMT Received: from [10.151.36.43] (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 28 Feb 2025 03:13:21 -0800 Message-ID: Date: Fri, 28 Feb 2025 16:43:19 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH v1 2/3] arm64: dts: qcom: ipq9574: Enable SPI NAND for ipq9574 Content-Language: en-US To: Konrad Dybcio , , , , , , , , References: <20250224113742.2829545-1-quic_mdalam@quicinc.com> <20250224113742.2829545-3-quic_mdalam@quicinc.com> <51ceb7ae-0dbe-4585-a955-e84bcde6c8f9@oss.qualcomm.com> From: Md Sadre Alam In-Reply-To: <51ceb7ae-0dbe-4585-a955-e84bcde6c8f9@oss.qualcomm.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 2HRbun5o0aoiCrMImaDlrqOWVWPXtCY8 X-Proofpoint-ORIG-GUID: 2HRbun5o0aoiCrMImaDlrqOWVWPXtCY8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-28_02,2025-02-27_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 impostorscore=0 phishscore=0 bulkscore=0 malwarescore=0 mlxscore=0 priorityscore=1501 adultscore=0 spamscore=0 mlxlogscore=836 lowpriorityscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2502100000 definitions=main-2502280080 On 2/25/2025 2:06 AM, Konrad Dybcio wrote: > On 24.02.2025 12:37 PM, Md Sadre Alam wrote: >> Enable SPI NAND support for ipq9574 SoC. >> >> Signed-off-by: Md Sadre Alam >> --- >> * Moved out ipq9574-rdp-common.dtsi changes into this patch from >> previous patch >> --- >> .../boot/dts/qcom/ipq9574-rdp-common.dtsi | 43 +++++++++++++++++++ >> 1 file changed, 43 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi >> index ae12f069f26f..6d1e84301671 100644 >> --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi >> +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi >> @@ -139,6 +139,49 @@ gpio_leds_default: gpio-leds-default-state { >> drive-strength = <8>; >> bias-pull-up; >> }; >> + >> + qpic_snand_default_state: qpic-snand-default-state { >> + clock-pins { >> + pins = "gpio5"; >> + function = "qspi_clk"; >> + drive-strength = <8>; >> + bias-disable; >> + }; >> + >> + cs-pins { >> + pins = "gpio4"; >> + function = "qspi_cs"; >> + drive-strength = <8>; >> + bias-disable; >> + }; >> + >> + data-pins { >> + pins = "gpio0", "gpio1", "gpio2", "gpio3"; >> + function = "qspi_data"; >> + drive-strength = <8>; >> + bias-disable; >> + }; >> + }; >> +}; >> + >> +&qpic_bam { >> + status = "okay"; >> +}; >> + >> +&qpic_nand { >> + pinctrl-0 = <&qpic_snand_default_state>; >> + pinctrl-names = "default"; >> + status = "okay"; > > Please add a newline before status Ok, will do in next revision. > > Reviewed-by: Konrad Dybcio > > Konrad