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From: Reinette Chatre <reinette.chatre@intel.com>
To: <babu.moger@amd.com>, <corbet@lwn.net>, <tglx@linutronix.de>,
	<mingo@redhat.com>, <bp@alien8.de>, <dave.hansen@linux.intel.com>,
	<x86@kernel.org>
Cc: <fenghua.yu@intel.com>, <hpa@zytor.com>, <paulmck@kernel.org>,
	<thuth@redhat.com>, <xiongwei.song@windriver.com>,
	<ardb@kernel.org>, <pawan.kumar.gupta@linux.intel.com>,
	<daniel.sneddon@linux.intel.com>, <sandipan.das@amd.com>,
	<kai.huang@intel.com>, <peterz@infradead.org>,
	<kan.liang@linux.intel.com>, <pbonzini@redhat.com>,
	<xin3.li@intel.com>, <ebiggers@google.com>,
	<alexandre.chartre@oracle.com>, <perry.yuan@amd.com>,
	<tan.shaopeng@fujitsu.com>, <james.morse@arm.com>,
	<tony.luck@intel.com>, <maciej.wieczor-retman@intel.com>,
	<linux-doc@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<peternewman@google.com>, <eranian@google.com>
Subject: Re: [PATCH 5/7] x86/resctrl: Add interface to enable/disable SDCIAE
Date: Thu, 19 Sep 2024 08:35:19 -0700	[thread overview]
Message-ID: <ec170d40-7390-4cc7-9128-d200df7405ee@intel.com> (raw)
In-Reply-To: <ecdffce0-796b-4ebe-8999-73f2be1e703b@amd.com>

Hi Babu,

On 9/18/24 1:10 PM, Moger, Babu wrote:
> On 9/13/24 15:51, Reinette Chatre wrote:
>> On 8/16/24 9:16 AM, Babu Moger wrote:

...

>>> +        if (enable) {
>>> +            ret = closid_alloc_sdciae(r);
>>> +            if (ret < 0) {
>>> +                rdt_last_cmd_puts("SDCIAE CLOSID is not available\n");
>>> +                goto out_sdciae;
>>> +            }
>>> +        } else {
>>> +            sdciae_closid = get_sdciae_closid(r);
>>> +            closid_free(sdciae_closid);
>>> +        }
>>
>>
>>> +
>>> +        ret = resctrl_arch_set_sdciae_enabled(RDT_RESOURCE_L3, enable);
>>
>> I assume that once SDCIAE is enabled the I/O traffic will start flowing to
>> whatever
>> was the last CBM of the max CLOSID? Is this intended or should there be
>> some default
>> CBM that this feature should start with?
> 
> It will start with whatever the last CBM for max CLOSID.

This seems arbitrary based on whatever allocation the previous resource group
using the CLOSID has. When a new resource group is created resctrl ensures
that it is created with all usable allocations, see rdtgroup_init_cat().
Letting cache injection start with whatever allocation remnant programmed
in a register does not seem ideal. What if, for example, after that resource
group was removed, a new exclusive resource group was created that overlaps
with that allocation? 

Reinette

  reply	other threads:[~2024-09-19 15:35 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-08-16 16:16 [PATCH 0/7] x86/resctrl : Support L3 Smart Data Cache Injection Allocation Enforcement (SDCIAE) Babu Moger
2024-08-16 16:16 ` [PATCH 1/7] x86/cpufeatures: Add support for L3 Smart Data Cache Injection Allocation Enforcement Babu Moger
2024-08-17 14:50   ` Borislav Petkov
2024-08-19 20:17     ` Moger, Babu
2024-09-13 20:44   ` Reinette Chatre
2024-09-18  0:50     ` Moger, Babu
2024-08-16 16:16 ` [PATCH 2/7] x86/resctrl: Add SDCIAE feature in the command line options Babu Moger
2024-09-13 20:45   ` Reinette Chatre
2024-09-18 14:38     ` Moger, Babu
2024-08-16 16:16 ` [PATCH 3/7] x86/resctrl: Introduce sdciae_capable in rdt_resource Babu Moger
2024-09-13 20:45   ` Reinette Chatre
2024-09-18 15:27     ` Moger, Babu
2024-09-18 18:22       ` Moger, Babu
2024-09-19 15:33         ` Reinette Chatre
2024-09-20 21:05           ` Moger, Babu
2024-10-15 20:40           ` Moger, Babu
2024-10-16 15:54             ` Reinette Chatre
2024-10-16 16:46               ` Moger, Babu
2024-10-16 18:31                 ` Reinette Chatre
2024-08-16 16:16 ` [PATCH 4/7] x86/resctrl: Implement SDCIAE enable/disable Babu Moger
2024-09-13 20:46   ` Reinette Chatre
2024-09-18 16:26     ` Moger, Babu
2024-09-19 15:34       ` Reinette Chatre
2024-09-20 21:33         ` Moger, Babu
2024-08-16 16:16 ` [PATCH 5/7] x86/resctrl: Add interface to enable/disable SDCIAE Babu Moger
2024-09-13 20:51   ` Reinette Chatre
2024-09-18 20:10     ` Moger, Babu
2024-09-19 15:35       ` Reinette Chatre [this message]
2024-10-15 19:25         ` Moger, Babu
2024-10-16 15:53           ` Reinette Chatre
2024-10-16 16:52             ` Moger, Babu
2024-08-16 16:16 ` [PATCH 6/7] x86/resctrl: Introduce interface to display SDCIAE Capacity Bit Masks Babu Moger
2024-09-13 20:52   ` Reinette Chatre
2024-09-18 20:19     ` Moger, Babu
2024-08-16 16:16 ` [PATCH 7/7] x86/resctrl: Introduce interface to modify " Babu Moger
2024-09-13 20:44 ` [PATCH 0/7] x86/resctrl : Support L3 Smart Data Cache Injection Allocation Enforcement (SDCIAE) Reinette Chatre
2024-09-17 20:51   ` Moger, Babu

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