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[68.228.73.187]) by smtp.gmail.com with ESMTPSA id q25-v6sm13920461pfh.113.2018.09.15.14.11.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 15 Sep 2018 14:11:32 -0700 (PDT) Subject: Re: [PATCH net-next v3 09/11] dt-bindings: add constants for Microsemi Ocelot SerDes driver To: Quentin Schulz , alexandre.belloni@bootlin.com, ralf@linux-mips.org, paul.burton@mips.com, jhogan@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, davem@davemloft.net, kishon@ti.com, andrew@lunn.ch Cc: allan.nielsen@microchip.com, linux-mips@linux-mips.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, thomas.petazzoni@bootlin.com References: <73113ea4b3d8d34c05d88413b3d15cc1733cf25e.1536912834.git-series.quentin.schulz@bootlin.com> From: Florian Fainelli Message-ID: Date: Fri, 14 Sep 2018 19:31:31 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 MIME-Version: 1.0 In-Reply-To: <73113ea4b3d8d34c05d88413b3d15cc1733cf25e.1536912834.git-series.quentin.schulz@bootlin.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 09/14/18 01:16, Quentin Schulz wrote: > The Microsemi Ocelot has multiple SerDes and requires that the SerDes be > muxed accordingly to the hardware representation. > > Let's add a constant for each SerDes available in the Microsemi Ocelot. > > Signed-off-by: Quentin Schulz > --- > include/dt-bindings/phy/phy-ocelot-serdes.h | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > create mode 100644 include/dt-bindings/phy/phy-ocelot-serdes.h > > diff --git a/include/dt-bindings/phy/phy-ocelot-serdes.h b/include/dt-bindings/phy/phy-ocelot-serdes.h > new file mode 100644 > index 0000000..cf111ba > --- /dev/null > +++ b/include/dt-bindings/phy/phy-ocelot-serdes.h > @@ -0,0 +1,19 @@ > +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ > +/* Copyright (c) 2018 Microsemi Corporation */ > +#ifndef __PHY_OCELOT_SERDES_H__ > +#define __PHY_OCELOT_SERDES_H__ > + > +#define SERDES1G_0 0 > +#define SERDES1G_1 1 > +#define SERDES1G_2 2 > +#define SERDES1G_3 3 > +#define SERDES1G_4 4 > +#define SERDES1G_5 5 > +#define SERDES1G_MAX 6 Given you use the C preprocessor you could have done something like: #define SERDES1G(x) (x) #define SERDES1G_MAX 5 #define SERDES6G(x) ((x) + SERDES1G_MAX) etc. but this works for me as well. > +#define SERDES6G_0 SERDES1G_MAX > +#define SERDES6G_1 (SERDES1G_MAX + 1) > +#define SERDES6G_2 (SERDES1G_MAX + 2) > +#define SERDES6G_MAX (SERDES1G_MAX + 3) > +#define SERDES_MAX (SERDES1G_MAX + SERDES6G_MAX) > + > +#endif > -- Florian