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Tue, 22 Jul 2025 09:37:50 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 571CB4005B; Tue, 22 Jul 2025 09:36:26 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 1132476DC2F; Tue, 22 Jul 2025 09:35:09 +0200 (CEST) Received: from [10.48.86.185] (10.48.86.185) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 22 Jul 2025 09:35:07 +0200 Message-ID: Date: Tue, 22 Jul 2025 09:35:06 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 05/16] dt-bindings: memory: add jedec,ddr[3-4]-channel binding To: Rob Herring CC: Will Deacon , Mark Rutland , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Philipp Zabel , Jonathan Corbet , Gatien Chevallier , Michael Turquette , Stephen Boyd , Gabriel Fernandez , Krzysztof Kozlowski , Le Goffic , , , , , , , References: <20250711-ddrperfm-upstream-v2-0-cdece720348f@foss.st.com> <20250711-ddrperfm-upstream-v2-5-cdece720348f@foss.st.com> <20250721200926.GA1179079-robh@kernel.org> Content-Language: en-US From: Clement LE GOFFIC In-Reply-To: <20250721200926.GA1179079-robh@kernel.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-22_01,2025-07-21_02,2025-03-28_01 Hi Rob, On 7/21/25 22:09, Rob Herring wrote: > On Fri, Jul 11, 2025 at 04:48:57PM +0200, Clément Le Goffic wrote: >> Introduce as per jedec,lpddrX-channel binding, jdec,ddr[3-4]-channel >> binding. >> >> Signed-off-by: Clément Le Goffic >> --- >> .../memory-controllers/ddr/jedec,ddr-channel.yaml | 53 ++++++++++++++++++++++ >> 1 file changed, 53 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,ddr-channel.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,ddr-channel.yaml >> new file mode 100644 >> index 000000000000..31daa22bcd4a >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,ddr-channel.yaml >> @@ -0,0 +1,53 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,ddr-channel.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: DDR channel with chip/rank topology description >> + >> +description: >> + A DDR channel is a logical grouping of memory chips that are connected >> + to a host system. The main purpose of this node is to describe the >> + overall DDR topology of the system, including the amount of individual >> + DDR chips. >> + >> +maintainers: >> + - Clément Le Goffic >> + >> +properties: >> + compatible: >> + enum: >> + - jedec,ddr3-channel >> + - jedec,ddr4-channel >> + >> + io-width: >> + description: >> + The number of DQ pins in the channel. If this number is different >> + from (a multiple of) the io-width of the DDR chip, that means that >> + multiple instances of that type of chip are wired in parallel on this >> + channel (with the channel's DQ pins split up between the different >> + chips, and the CA, CS, etc. pins of the different chips all shorted >> + together). This means that the total physical memory controlled by a >> + channel is equal to the sum of the densities of each rank on the >> + connected DDR chip, times the io-width of the channel divided by >> + the io-width of the DDR chip. >> + enum: >> + - 8 >> + - 16 >> + - 32 >> + - 64 >> + - 128 > > This is duplicating what's in jedec,lpddr-channel.yaml. Refactor or add > to it rather than duplicating. Yes I wanted something unique as "jedec,lpddr-channel.yaml" is specifically for lpddr. I think I'll refactor and rename it "jedec,memory-channel.yaml" so it is more generic. > Is there some reason regular DDR3/4 doesn't have ranks? I'm pretty sure > it can... Yes it does but I wasn't needing it and they are not required in case of lpddr. It will be fixed by refactoring jedec,lpddr-channel.yaml binding. Best regards, Clément