From: "Li, Aubrey" <aubrey.li@linux.intel.com>
To: Dave Hansen <dave.hansen@intel.com>,
Aubrey Li <aubrey.li@intel.com>,
tglx@linutronix.de, mingo@redhat.com, peterz@infradead.org,
hpa@zytor.com
Cc: ak@linux.intel.com, tim.c.chen@linux.intel.com,
arjan@linux.intel.com, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 1/2] x86/fpu: track AVX-512 usage of tasks
Date: Sat, 17 Nov 2018 08:36:31 +0800 [thread overview]
Message-ID: <ed5bf776-3e39-5a5f-4072-52dacde41772@linux.intel.com> (raw)
In-Reply-To: <b67c995e-3883-ce17-0396-b1621ec5d58f@intel.com>
On 2018/11/17 7:10, Dave Hansen wrote:
> On 11/15/18 4:21 PM, Li, Aubrey wrote:
>> "Core cycles where the core was running with power delivery for license
>> level 2 (introduced in Skylake Server microarchitecture). This includes
>> high current AVX 512-bit instructions."
>>
>> I translated license level 2 to frequency drop.
>
> BTW, the "high" in that text: "high-current AVX 512-bit instructions" is
> talking about high-current, not "high ... instructions" or high-numbered
> registers. I think that might be the source of some of the confusion
> about which XSAVE state needs to be examined.
>
> Just to be clear: there are 3 AVX-512 XSAVE states:
>
> XFEATURE_OPMASK,
> XFEATURE_ZMM_Hi256,
> XFEATURE_Hi16_ZMM,
>
> I honestly don't know what XFEATURE_OPMASK does. It does not appear to
> be affected by VZEROUPPER (although VZEROUPPER's SDM documentation isn't
> looking too great).
>
> But, XFEATURE_ZMM_Hi256 is used for the upper 256 bits of the
> registers ZMM0-ZMM15. Those are AVX-512-only registers. The only way
> to get data into XFEATURE_ZMM_Hi256 state is by using AVX512 instructions.
>
> XFEATURE_Hi16_ZMM is the same. The only way to get state in there is
> with AVX512 instructions.
>
> So, first of all, I think you *MUST* check XFEATURE_ZMM_Hi256 and
> XFEATURE_Hi16_ZMM. That's without question.
No, XFEATURE_ZMM_Hi256 does not request turbo license 2, so it's less
interested to us.
>
> It's probably *possible* to run AVX512 instructions by loading state
> into the YMM register and then executing AVX512 instructions that only
> write to memory and never to register state. That *might* allow
> XFEATURE_Hi16_ZMM and XFEATURE_ZMM_Hi256 to stay in the init state, but
> for the frequency to be affected since AVX512 instructions _are_
> executing. But, there's no way to detect this situation from XSAVE
> states themselves.
>
Andi should have more details on this. FWICT, not all AVX512 instructions
has high current, those only touching memory do not cause notable frequency
drop.
Thanks,
-Aubrey
next prev parent reply other threads:[~2018-11-17 0:36 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-14 23:00 [PATCH v3 1/2] x86/fpu: track AVX-512 usage of tasks Aubrey Li
2018-11-14 23:00 ` [PATCH v3 2/2] proc: add /proc/<pid>/arch_state Aubrey Li
2018-11-15 15:18 ` Dave Hansen
2018-11-16 0:32 ` Li, Aubrey
2018-11-19 17:39 ` Peter Zijlstra
2018-11-21 1:39 ` Li, Aubrey
2018-11-21 8:19 ` Peter Zijlstra
2018-11-21 9:53 ` Peter Zijlstra
2018-11-21 17:12 ` Palmer Dabbelt
2018-11-22 1:40 ` Li, Aubrey
2018-11-23 17:11 ` Dave Martin
2018-11-15 15:40 ` [PATCH v3 1/2] x86/fpu: track AVX-512 usage of tasks Dave Hansen
2018-11-16 0:21 ` Li, Aubrey
2018-11-16 1:04 ` Dave Hansen
2018-11-16 23:10 ` Dave Hansen
2018-11-17 0:36 ` Li, Aubrey [this message]
-- strict thread matches above, loose matches on Subject: below --
2018-11-18 14:03 Samuel Neves
2018-11-20 13:20 ` Li, Aubrey
2018-11-20 14:47 ` Samuel Neves
2018-11-26 3:36 ` Li, Aubrey
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