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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac71961f3c7sm320820566b.94.2025.03.29.04.42.03 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 29 Mar 2025 04:42:05 -0700 (PDT) Message-ID: Date: Sat, 29 Mar 2025 12:42:02 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v8 4/4] PCI: dwc: Add support for configuring lane equalization presets To: Manivannan Sadhasivam , Konrad Dybcio Cc: Krishna Chaitanya Chundru , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Helgaas , Jingoo Han , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, quic_mrana@quicinc.com, quic_vbadigan@quicinc.com References: <20250316-preset_v6-v8-0-0703a78cb355@oss.qualcomm.com> <20250316-preset_v6-v8-4-0703a78cb355@oss.qualcomm.com> <3sbflmznjfqpcja52v6bso74vhouv7ncuikrba5zlb74tqqb5u@ovndmib3kgqf> <92c4854d-033e-c7b5-ca92-cf44a1a8c0cc@oss.qualcomm.com> <5fece4ac-2899-4e7d-8205-3b1ebba4b56b@oss.qualcomm.com> <622788fa-a067-49ac-b5b1-e4ec339e026f@oss.qualcomm.com> <4rep2gvymazkk7pgve36cw7moppozaju7h6aqc3gflxrvkskig@62ykri6v4trs> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <4rep2gvymazkk7pgve36cw7moppozaju7h6aqc3gflxrvkskig@62ykri6v4trs> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: fJppjlmA0wbo6LDJ_oa9u0InURnBcvNk X-Authority-Analysis: v=2.4 cv=YqcPR5YX c=1 sm=1 tr=0 ts=67e7dc8f cx=c_pps a=UgVkIMxJMSkC9lv97toC5g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=Vs1iUdzkB0EA:10 a=EUspDBNiAAAA:8 a=jKyjlexm6IKzr5l-IOMA:9 a=QEXdDO2ut3YA:10 a=1HOtulTD9v-eNWfpl4qZ:22 X-Proofpoint-ORIG-GUID: fJppjlmA0wbo6LDJ_oa9u0InURnBcvNk X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-29_01,2025-03-27_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 clxscore=1015 priorityscore=1501 malwarescore=0 spamscore=0 phishscore=0 impostorscore=0 suspectscore=0 mlxlogscore=999 bulkscore=0 adultscore=0 lowpriorityscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2503290083 On 3/29/25 10:39 AM, Manivannan Sadhasivam wrote: > On Sat, Mar 29, 2025 at 09:59:46AM +0100, Konrad Dybcio wrote: >> On 3/29/25 7:30 AM, Manivannan Sadhasivam wrote: >>> On Fri, Mar 28, 2025 at 10:53:19PM +0100, Konrad Dybcio wrote: >>>> On 3/28/25 7:45 AM, Manivannan Sadhasivam wrote: >>>>> On Fri, Mar 28, 2025 at 11:04:11AM +0530, Krishna Chaitanya Chundru wrote: >>>>>> >>>>>> >>>>>> On 3/28/2025 10:23 AM, Manivannan Sadhasivam wrote: >>>>>>> On Sun, Mar 16, 2025 at 09:39:04AM +0530, Krishna Chaitanya Chundru wrote: >>>>>>>> PCIe equalization presets are predefined settings used to optimize >>>>>>>> signal integrity by compensating for signal loss and distortion in >>>>>>>> high-speed data transmission. >>>>>>>> >>>>>>>> Based upon the number of lanes and the data rate supported, write >>>>>>>> the preset data read from the device tree in to the lane equalization >>>>>>>> control registers. >>>>>>>> >>>>>>>> Signed-off-by: Krishna Chaitanya Chundru >>>>>>>> --- >>>>>>>> drivers/pci/controller/dwc/pcie-designware-host.c | 60 +++++++++++++++++++++++ >>>>>>>> drivers/pci/controller/dwc/pcie-designware.h | 3 ++ >>>>>>>> include/uapi/linux/pci_regs.h | 3 ++ >>>>>>>> 3 files changed, 66 insertions(+) >>>>>>>> >>>>>>>> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c >>>>>>>> index dd56cc02f4ef..7c6e6a74383b 100644 >>>>>>>> --- a/drivers/pci/controller/dwc/pcie-designware-host.c >>>>>>>> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c >>>>>>>> @@ -507,6 +507,10 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) >>>>>>>> if (pci->num_lanes < 1) >>>>>>>> pci->num_lanes = dw_pcie_link_get_max_link_width(pci); >>>>>>>> + ret = of_pci_get_equalization_presets(dev, &pp->presets, pci->num_lanes); >>>>>>>> + if (ret) >>>>>>>> + goto err_free_msi; >>>>>>>> + >>>>>>>> /* >>>>>>>> * Allocate the resource for MSG TLP before programming the iATU >>>>>>>> * outbound window in dw_pcie_setup_rc(). Since the allocation depends >>>>>>>> @@ -808,6 +812,61 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) >>>>>>>> return 0; >>>>>>>> } >>>>>>>> +static void dw_pcie_program_presets(struct dw_pcie_rp *pp, enum pci_bus_speed speed) >>>>>>>> +{ >>>>>>>> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); >>>>>>>> + u8 lane_eq_offset, lane_reg_size, cap_id; >>>>>>>> + u8 *presets; >>>>>>>> + u32 cap; >>>>>>>> + int i; >>>>>>>> + >>>>>>>> + if (speed == PCIE_SPEED_8_0GT) { >>>>>>>> + presets = (u8 *)pp->presets.eq_presets_8gts; >>>>>>>> + lane_eq_offset = PCI_SECPCI_LE_CTRL; >>>>>>>> + cap_id = PCI_EXT_CAP_ID_SECPCI; >>>>>>>> + /* For data rate of 8 GT/S each lane equalization control is 16bits wide*/ >>>>>>>> + lane_reg_size = 0x2; >>>>>>>> + } else if (speed == PCIE_SPEED_16_0GT) { >>>>>>>> + presets = pp->presets.eq_presets_Ngts[EQ_PRESET_TYPE_16GTS - 1]; >>>>>>>> + lane_eq_offset = PCI_PL_16GT_LE_CTRL; >>>>>>>> + cap_id = PCI_EXT_CAP_ID_PL_16GT; >>>>>>>> + lane_reg_size = 0x1; >>>>>>>> + } else { >>>>>>> >>>>>>> Can you add conditions for other data rates also? Like 32, 64 GT/s. If >>>>>>> controller supports them and if the presets property is defined in DT, then you >>>>>>> should apply the preset values. >>>>>>> >>>>>>> If the presets property is not present in DT, then below 'PCI_EQ_RESV' will >>>>>>> safely return. >>>>>>> >>>>>> I am fine to add it, but there is no GEN5 or GEN6 controller support >>>>>> added in dwc, isn't it best to add when that support is added and >>>>>> tested. >>>>>> >>>>> >>>>> What is the guarantee that this part of the code will be updated once the >>>>> capable controllers start showing up? I don't think there will be any issue in >>>>> writing to these registers. >>>> >>>> Let's not make assumptions about the spec of a cross-vendor mass-deployed IP >>>> >>> >>> I have seen the worse... The problem is, if those controllers start to show up >>> and define preset properties in DT, there will be no errors whatsoever to >>> indicate that the preset values were not applied, resulting in hard to debug >>> errors. >> >> else { >> dev_warn(pci->dev, "Missing equalization presets programming sequence\n"); >> } >> > > Then we'd warn for controllers supporting GEN5 or more if they do not pass the > presets property (which is optional). Ohh, I didn't think about that - and I can only think about solutions that are rather janky.. with perhaps the least janky one being changing the else case I proposed above into: else if (speed >= PCIE_SPEED_32_0GT && eq_presets_Ngts[speed - PCIE_SPEED_16_0GT][0] != PCI_EQ_RESV) { ... }> >>> >>> I'm not forseeing any issue in this part of the code to support higher GEN >>> speeds though. >> >> I would hope so as well, but both not programming and misprogramming are >> equally hard to detect >> > > I don't disagree. I wanted to have it since there is no sensible way of warning > users that this part of the code needs to be updated in the future. I understand, however I'm worried that the programming sequence or register may change for higher speeds in a way that would be incompatible with what we assume here Konrad