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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac3ef8d3ee9sm880947766b.67.2025.03.25.07.41.48 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 25 Mar 2025 07:41:50 -0700 (PDT) Message-ID: Date: Tue, 25 Mar 2025 15:41:48 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 0/5] Add snps,dis_u3_susphy_quirk for some QC targets To: Prashanth K , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: cros-qcom-dts-watchers@chromium.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250325123019.597976-1-prashanth.k@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20250325123019.597976-1-prashanth.k@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: JKyHoIDfORawgdSjtaHojb3B6cx4p--o X-Proofpoint-ORIG-GUID: JKyHoIDfORawgdSjtaHojb3B6cx4p--o X-Authority-Analysis: v=2.4 cv=IKYCChvG c=1 sm=1 tr=0 ts=67e2c0b0 cx=c_pps a=7E5Bxpl4vBhpaufnMqZlrw==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=Vs1iUdzkB0EA:10 a=VwQbUJbxAAAA:8 a=COk6AnOGAAAA:8 a=-hWUoSwDaZ0JBn50UMYA:9 a=QEXdDO2ut3YA:10 a=pJ04lnu7RYOZP9TFuWaZ:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-25_06,2025-03-25_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 phishscore=0 lowpriorityscore=0 impostorscore=0 bulkscore=0 spamscore=0 priorityscore=1501 adultscore=0 malwarescore=0 mlxlogscore=883 mlxscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2503250103 On 3/25/25 1:30 PM, Prashanth K wrote: > During device mode initialization on certain QC targets, before the > runstop bit is set, sometimes it's observed that the GEVNTADR{LO/HI} > register write fails. As a result, GEVTADDR registers are still 0x0. > Upon setting runstop bit, DWC3 controller attempts to write the new > events to address 0x0, causing an SMMU fault and system crash. More > info about the crash at [1]. > > This was initially observed on SM8450 and later reported on few > other targets as well. As suggested by Qualcomm HW team, clearing > the GUSB3PIPECTL.SUSPHY bit resolves the issue by preventing register > write failures. Address this by setting the snps,dis_u3_susphy_quirk > to keep the GUSB3PIPECTL.SUSPHY bit cleared. This change was tested > on multiple targets (SM8350, SM8450 QCS615 etc.) for over an year > and hasn't exhibited any side effects. > > [1]: https://lore.kernel.org/all/fa94cbc9-e637-ba9b-8ec8-67c6955eca98@quicinc.com/ > > Prashanth K (3): > arm64: dts: qcom: sm8150: Add snps,dis_u3_susphy_quirk > arm64: dts: qcom: sm8350: Add snps,dis_u3_susphy_quirk > arm64: dts: qcom: sm8450: Add snps,dis_u3_susphy_quirk > > Pratham Pratap (2): > arm64: dts: qcom: qcs615: Add snps,dis_u3_susphy_quirk > arm64: dts: qcom: qdu1000: Add snps,dis_u3_susphy_quirk Are there more targets affected, from the list of the ones currently supported upstream? Konrad