From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 76ECEC433E0 for ; Fri, 26 Feb 2021 17:32:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2CE1464F32 for ; Fri, 26 Feb 2021 17:32:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230049AbhBZRcR (ORCPT ); Fri, 26 Feb 2021 12:32:17 -0500 Received: from m42-2.mailgun.net ([69.72.42.2]:35262 "EHLO m42-2.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229751AbhBZRcI (ORCPT ); Fri, 26 Feb 2021 12:32:08 -0500 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1614360703; h=Message-ID: References: In-Reply-To: Reply-To: Subject: Cc: To: From: Date: Content-Transfer-Encoding: Content-Type: MIME-Version: Sender; bh=M7HvRPiSZ2xSbCT1WOfPlcHl519+4Bp5gCcSHWi5Dtk=; b=TacWN7Gmsp7ybE/rqJcG8t0ZqL8w5V+M0Id4cLIFkjS7CZvCcZq/E5DoiJ8PVqSGa7Z6b13d MmGEiW2EeZKMGl20pXj7AihoE0H54C1B63W1g6BN8b6sa4B1T/w3QdIDKBx4TdljPs7tfWEk aSqvGPAdtO6avst4BDtxxFlYcJs= X-Mailgun-Sending-Ip: 69.72.42.2 X-Mailgun-Sid: WyI0MWYwYSIsICJsaW51eC1rZXJuZWxAdmdlci5rZXJuZWwub3JnIiwgImJlOWU0YSJd Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n02.prod.us-east-1.postgun.com with SMTP id 6039306d9e950d0db1367b47 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Fri, 26 Feb 2021 17:31:25 GMT Sender: bbhatt=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 7BE07C433CA; Fri, 26 Feb 2021 17:31:24 +0000 (UTC) Received: from mail.codeaurora.org (localhost.localdomain [127.0.0.1]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: bbhatt) by smtp.codeaurora.org (Postfix) with ESMTPSA id 09078C433C6; Fri, 26 Feb 2021 17:31:23 +0000 (UTC) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: 7bit Date: Fri, 26 Feb 2021 09:31:23 -0800 From: Bhaumik Bhatt To: Gokul Sriram Palanisamy Cc: Manivannan Sadhasivam , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, jhugo@codeaurora.org, hemantk@codeaurora.org, sricharan@codeaurora.org Subject: Re: [PATCH v2] bus: mhi: core: Add unique qrtr node id support Organization: Qualcomm Innovation Center, Inc. Reply-To: bbhatt@codeaurora.org Mail-Reply-To: bbhatt@codeaurora.org In-Reply-To: <20210226145245.GB70936@thinkpad> References: <1614336169-31467-1-git-send-email-gokulsri@codeaurora.org> <1614336169-31467-2-git-send-email-gokulsri@codeaurora.org> <20210226145245.GB70936@thinkpad> Message-ID: X-Sender: bbhatt@codeaurora.org User-Agent: Roundcube Webmail/1.3.9 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2021-02-26 06:52 AM, Manivannan Sadhasivam wrote: > On Fri, Feb 26, 2021 at 04:12:49PM +0530, Gokul Sriram Palanisamy > wrote: >> On platforms with two or more identical mhi >> devices, qmi service will run with identical >> qrtr-node-id. Because of this identical ID, >> host qrtr-lookup cannot register more than one >> qmi service with identical node ID. Ultimately, >> only one qmi service will be avilable for the >> underlying drivers to communicate with. >> >> On QCN9000, it implements a unique qrtr-node-id >> and qmi instance ID using a unique instance ID >> written to a debug register from host driver >> soon after SBL is loaded. >> >> This change generates a unique instance ID from >> PCIe domain number and bus number, writes to the >> given debug register just after SBL is loaded so >> that it is available for FW when the QMI service >> is spawned. >> >> sample: >> root@OpenWrt:/# qrtr-lookup >> Service Version Instance Node Port >> 15 1 0 8 1 Test service >> 69 1 8 8 2 ATH10k WLAN firmware service >> 15 1 0 24 1 Test service >> 69 1 24 24 2 ATH10k WLAN firmware service >> >> Here 8 and 24 on column 3 (QMI Instance ID) >> and 4 (QRTR Node ID) are the node IDs that >> is unique per mhi device. >> >> Signed-off-by: Gokul Sriram Palanisamy >> --- >> drivers/bus/mhi/core/boot.c | 14 ++++++++++++++ >> 1 file changed, 14 insertions(+) >> >> diff --git a/drivers/bus/mhi/core/boot.c b/drivers/bus/mhi/core/boot.c >> index c2546bf..5e5dad5 100644 >> --- a/drivers/bus/mhi/core/boot.c >> +++ b/drivers/bus/mhi/core/boot.c >> @@ -16,8 +16,12 @@ >> #include >> #include >> #include >> +#include >> #include "internal.h" >> >> +#define QRTR_INSTANCE_MASK 0x000000FF >> +#define QRTR_INSTANCE_SHIFT 0 >> + >> /* Setup RDDM vector table for RDDM transfer and program RXVEC */ >> void mhi_rddm_prepare(struct mhi_controller *mhi_cntrl, >> struct image_info *img_info) >> @@ -391,6 +395,9 @@ void mhi_fw_load_handler(struct mhi_controller >> *mhi_cntrl) >> const struct firmware *firmware = NULL; >> struct image_info *image_info; >> struct device *dev = &mhi_cntrl->mhi_dev->dev; >> + struct pci_dev *pci_dev = to_pci_dev(mhi_cntrl->cntrl_dev); >> + struct pci_bus *bus = pci_dev->bus; >> + uint32_t instance; >> const char *fw_name; >> void *buf; >> dma_addr_t dma_addr; >> @@ -466,6 +473,13 @@ void mhi_fw_load_handler(struct mhi_controller >> *mhi_cntrl) >> return; >> } >> >> + instance = ((pci_domain_nr(bus) & 0xF) << 4) | (bus->number & 0xF); >> + instance &= QRTR_INSTANCE_MASK; >> + >> + mhi_write_reg_field(mhi_cntrl, mhi_cntrl->bhi, >> + BHI_ERRDBG2, QRTR_INSTANCE_MASK, >> + QRTR_INSTANCE_SHIFT, instance); > > You cannot not do this in MHI stack. Why can't you do this in the MHI > controller > specific to QCN9000? And btw, is QCN9000 supported in mainline? > > Thanks, > Mani > >> + >> write_lock_irq(&mhi_cntrl->pm_lock); >> mhi_cntrl->dev_state = MHI_STATE_RESET; >> write_unlock_irq(&mhi_cntrl->pm_lock); >> -- >> 2.7.4 >> As others have stated, please refrain from adding protocol specific code (such as PCIe) in the MHI core driver. Please have this change in your controller. If there is access to BHI registers required prior to power up from MHI core, it is not exposed right now. We can talk about how you can achieve that, so you can do this write in your controller after mhi_prepare_for_power_up(). Thanks, Bhaumik --- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project