From: "Edgecombe, Rick P" <rick.p.edgecombe@intel.com>
To: "minipli@grsecurity.net" <minipli@grsecurity.net>,
"bp@alien8.de" <bp@alien8.de>
Cc: "peterz@infradead.org" <peterz@infradead.org>,
"mingo@redhat.com" <mingo@redhat.com>,
"tglx@kernel.org" <tglx@kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"dave.hansen@linux.intel.com" <dave.hansen@linux.intel.com>,
"x86@kernel.org" <x86@kernel.org>
Subject: Re: [PATCH v3] x86/cpufeatures: Make X86_FEATURE_SHSTK clearcpuid-able
Date: Fri, 15 May 2026 16:21:48 +0000 [thread overview]
Message-ID: <eecd720444bee47013a9a8cc9fc26d3b49622ed8.camel@intel.com> (raw)
In-Reply-To: <a3bf1f73-2f17-4745-8693-c9336e9010d1@grsecurity.net>
On Fri, 2026-05-15 at 18:11 +0200, Mathias Krause wrote:
> >
> > Anyway, "nousershstk" should disable the CR4 bit too.
> >
>
> No, it should not, as that's only for the user portion
> (X86_FEATURE_USER_SHSTK != X86_FEATURE_SHSTK).
>
> Even though there is (currently) no kernel level shadow stack support,
> KVM may still want to pass it down to guests for their usage -- even if
> the host *userland* shouldn't make use of it because of "nousershstk".
Yea, I was thinking on how we would implement this and wondering along these
same lines. We would need to set CR4.CET if we have kernel ibt, user shadow
stack or KVM configured (and also with HW support).
next prev parent reply other threads:[~2026-05-15 16:21 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-14 16:09 [PATCH v3] x86/cpufeatures: Make X86_FEATURE_SHSTK clearcpuid-able Mathias Krause
2026-05-14 16:59 ` Borislav Petkov
2026-05-14 17:07 ` Edgecombe, Rick P
2026-05-14 17:12 ` Borislav Petkov
2026-05-14 17:15 ` Borislav Petkov
2026-05-14 18:23 ` Edgecombe, Rick P
2026-05-14 22:38 ` Borislav Petkov
2026-05-15 16:20 ` Mathias Krause
2026-05-14 17:30 ` Dave Hansen
2026-05-14 18:25 ` Edgecombe, Rick P
2026-05-15 16:11 ` Mathias Krause
2026-05-15 16:21 ` Edgecombe, Rick P [this message]
2026-05-14 17:01 ` Edgecombe, Rick P
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