From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3C150288CA1; Wed, 6 Aug 2025 09:23:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754472211; cv=none; b=SbeGXjyvSddYWJtPPBXN0XUArPb0ONp+ju1RQ8ifPtLJJ9FyV5uZrxbXaAGi7EOAUWN11Xf44GlzOWwDz8ZT4WQfwAw6p3B52FFmCHew6cICmPOOAbu2onRoE3Ee8rhicGLdHcGONkmy9nWfV/Oyg+OezvAHwE7x/AdRJIy8pxs= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754472211; c=relaxed/simple; bh=Hwk7vf4HuAvJ7UE5NKvVA2XssqjK1pHzEDmND+upm+w=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=VEVXopUZC1whf1Ep4dwsY0gac/ojTUMe+ljCGbnwDvecb74hNoaw81X8L34tjcrqamRBwvyUomhRVG6Db+Wr+B5hqGkwFoTEC6JBl1AWsj+1MPK3J1NVfF7JinhNGKaS1TMKb+ygSYoi6+SnadY9ZRyiczsmyRkVfmqoAxDe4VQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=i6GNOto+; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="i6GNOto+" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 538D7C4CEE7; Wed, 6 Aug 2025 09:23:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1754472210; bh=Hwk7vf4HuAvJ7UE5NKvVA2XssqjK1pHzEDmND+upm+w=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=i6GNOto+ufwZENyRkRe/0U2+uH/1sJM9g0wsZ61Ffeoees9k2birWd0oPEd/qr7QX 1tErIhLbKSjseupyE4qMugARknExUz+FDgWq06s5mJgRN+me57kwAzEVm0KZYfg66X JR/AN8nU2UsLuJZ5fJiaHI5tnfKTm7F/R+/2ZfwkjBA/orFv19vzXWuh/lNh6qXWqq KOqOS37KyZXWVmoYqRuvUXX4Okpne/HTVHYwLhGJnGcRx9DR2UCyrdy7sLTroDbI1c VcexKBfRy5HQB8mHPo/seo5c8xMfa9x8ETmEaKwUcoC160BsgykC0u6Ke6n1wA9v7c etW7oMX8cjHZw== Message-ID: Date: Wed, 6 Aug 2025 11:23:21 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 00/16] Add support for the Axis ARTPEC-8 SoC To: Pankaj Dubey , 'SeonGu Kang' , 'Jesper Nilsson' , 'Michael Turquette' , 'Stephen Boyd' , 'Rob Herring' , 'Krzysztof Kozlowski' , 'Conor Dooley' , 'Sylwester Nawrocki' , 'Chanwoo Choi' , 'Alim Akhtar' , 'Linus Walleij' , 'Tomasz Figa' , 'Catalin Marinas' , 'Will Deacon' , 'Arnd Bergmann' Cc: 'kenkim' , 'Jongshin Park' , 'GunWoo Kim' , 'HaGyeong Kim' , 'GyoungBo Min' , 'SungMin Park' , 'Shradha Todi' , 'Ravi Patel' , 'Inbaraj E' , 'Swathi K S' , 'Hrishikesh' , 'Dongjin Yang' , 'Sang Min Kim' , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@axis.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, soc@lists.linux.dev References: <20250710002047.1573841-1-ksk4725@coasia.com> <847e908b-1073-46ea-93f3-1f36cc93d8b8@kernel.org> <99977f38-f055-46ed-8eb0-4b757da2bcdd@kernel.org> <000501dc06ab$37f09440$a7d1bcc0$@samsung.com> <002001dc06b1$540dc980$fc295c80$@samsung.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 06/08/2025 11:05, Pankaj Dubey wrote: > >> Also SAME strict DT compliance profile will be applied. (see more on >> that below) >> >>> >>> Given that ARTPEC-8 is a distinct SoC with its own set of IPs, we believe it's >> reasonable >>> to create a separate directory for it, similar to FSD. >> >> No. It was a mistake for FSD to keep it separate why? Because there is >> no single non-Samsung stuff there. I am afraid exactly the same will >> happen there. >> > > I am not sure, why you are saying this as a mistake, in case next version of FSD My mistake that I agreed on that, based on promise that "there will be non Samsung stuff" and that "non Samsung stuff" never happened. > or ARTPEC is manufactured (ODM) by another vendor in that case, won't it > create problems? No problems here. Non-Samsung Artpec/Axis soc will not go there. It will go the top-level axis directory, just like artpec-6 > > For example ARTPEC-6/7 (ARM based) have their own directories as "arch/arm/boot/dts/axis/" > These were not Samsung (ODM) manufactures SoCs. > > But ARTPEC-8/9 (ARM64) based SoCs are samsung manufactured. What if the next version say > ARTPEC-10 is not samsung manufactured, so different version of products (SoCs) from > same vendor (OEM), in this case Axis, will have code in separate directories and with different maintainers? It will be the same with Google Pixel for whatever they decide in the future. dts/exynos/google/ + dts/google/. I know that this is not ideal, but for me grouping samsung stuff together is far more important, because there is much, much more to share between two SoCs designed by Samsung, than Axis-9 and future non-Samsung Axis-10. And I have `git grep` as argument: git grep compatible -- arch/arm64/boot/dts/tesla/ and point me to any Tesla IP. Zero results. > >> Based on above list of blocks this should be done like Google is done, >> so it goes as subdirectory of samsung (exynos). Can be called axis or >> artpec-8. > > I will suggest to keep axis, knowing the fact that sooner after artpec-8 patches gets approved and merged > we have plan to upstream artpec-9 (ARM64, Samsung manufactured) as well. > >> >> To clarify: Only this SoC, not others which are not Samsung. >> >>> >>> We will remove Samsung and Coasia teams from the maintainers list in v2 >> and only >>> Axis team will be maintainer. >> >> A bit unexpected or rather: just use names of people who WILL be >> maintaining it. If this is Jesper and Lars, great. Just don't add >> entries just because they are managers. > > AFAIK, Jesper will be taking care. > >> >>> >>> Maintainer list for previous generation of Axis chips (ARM based) is already >> present, >>> so this will be merged into that. >> >> Existing Artpec entry does not have tree mentioned, so if you choose >> above, you must not add the tree, since the tree is provided by Samsung SoC. >> > > OK > >> OTOH, how are you going to add there strict DT compliance? Existing axis >> is not following this, but artpec-8, as a Samsung derivative, MUST >> FOLLOW strict DT compliance. And this should be clearly marked in >> maintainer entry, just like everywhere else. >> > > As I said this is tricky situation, though artpec-8 is derivative of samsung, we can't confirm > if future versions (> 9) will be samsung derivative. > > But this would be case for all such custom ASIC manufactured by samsung, so I would like to > understand how this will be handled? I suggest to do the same as Google and when I say Google in this email, I mean Pixel/GS101. Google was easier because there was no prior entry and Axis has, so you will have two Axis entries. But I don't see how we can add clean-dts profiles to the existing Axis entry, if you decide to include Artpec-8 in that one. Best regards, Krzysztof