From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.5 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A, SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 44F50C433E6 for ; Thu, 14 Jan 2021 10:21:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1A16F23A3B for ; Thu, 14 Jan 2021 10:21:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728680AbhANKV3 (ORCPT ); Thu, 14 Jan 2021 05:21:29 -0500 Received: from foss.arm.com ([217.140.110.172]:47212 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728535AbhANKV0 (ORCPT ); Thu, 14 Jan 2021 05:21:26 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4C95D1FB; Thu, 14 Jan 2021 02:20:41 -0800 (PST) Received: from [10.0.0.31] (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9A4E33F70D; Thu, 14 Jan 2021 02:20:39 -0800 (PST) Subject: Re: [PATCH v2 3/4] arm64: mte: Enable async tag check fault To: Catalin Marinas Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kasan-dev@googlegroups.com, Will Deacon , Dmitry Vyukov , Andrey Ryabinin , Alexander Potapenko , Marco Elver , Evgenii Stepanov , Branislav Rankov , Andrey Konovalov References: <20210107172908.42686-1-vincenzo.frascino@arm.com> <20210107172908.42686-4-vincenzo.frascino@arm.com> <20210113181121.GF27045@gaia> From: Vincenzo Frascino Message-ID: Date: Thu, 14 Jan 2021 10:24:25 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20210113181121.GF27045@gaia> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 1/13/21 6:11 PM, Catalin Marinas wrote: > On Thu, Jan 07, 2021 at 05:29:07PM +0000, Vincenzo Frascino wrote: >> diff --git a/arch/arm64/include/asm/mte.h b/arch/arm64/include/asm/mte.h >> index d02aff9f493d..a60d3718baae 100644 >> --- a/arch/arm64/include/asm/mte.h >> +++ b/arch/arm64/include/asm/mte.h >> @@ -39,6 +39,7 @@ void mte_free_tag_storage(char *storage); >> /* track which pages have valid allocation tags */ >> #define PG_mte_tagged PG_arch_2 >> >> +void mte_check_tfsr_el1(void); >> void mte_sync_tags(pte_t *ptep, pte_t pte); >> void mte_copy_page_tags(void *kto, const void *kfrom); >> void flush_mte_state(void); >> @@ -56,6 +57,9 @@ void mte_assign_mem_tag_range(void *addr, size_t size); >> /* unused if !CONFIG_ARM64_MTE, silence the compiler */ >> #define PG_mte_tagged 0 >> >> +static inline void mte_check_tfsr_el1(void) >> +{ >> +} > > I think we should enable this dummy function when !CONFIG_KASAN_HW_TAGS. > It saves us an unnecessary function call in a few places. > Ok, I will add it in v3. >> static inline void mte_sync_tags(pte_t *ptep, pte_t pte) >> { >> } >> diff --git a/arch/arm64/kernel/entry-common.c b/arch/arm64/kernel/entry-common.c >> index 5346953e4382..74b020ce72d7 100644 >> --- a/arch/arm64/kernel/entry-common.c >> +++ b/arch/arm64/kernel/entry-common.c >> @@ -37,6 +37,8 @@ static void noinstr enter_from_kernel_mode(struct pt_regs *regs) >> lockdep_hardirqs_off(CALLER_ADDR0); >> rcu_irq_enter_check_tick(); >> trace_hardirqs_off_finish(); >> + >> + mte_check_tfsr_el1(); >> } >> >> /* >> @@ -47,6 +49,8 @@ static void noinstr exit_to_kernel_mode(struct pt_regs *regs) >> { >> lockdep_assert_irqs_disabled(); >> >> + mte_check_tfsr_el1(); >> + >> if (interrupts_enabled(regs)) { >> if (regs->exit_rcu) { >> trace_hardirqs_on_prepare(); >> @@ -243,6 +247,8 @@ asmlinkage void noinstr enter_from_user_mode(void) >> >> asmlinkage void noinstr exit_to_user_mode(void) >> { >> + mte_check_tfsr_el1(); > > While for kernel entry the asynchronous faults are sync'ed automatically > with TFSR_EL1, we don't have this for exit, so we'd need an explicit > DSB. But rather than placing it here, it's better if we add a bool sync > argument to mte_check_tfsr_el1() which issues a dsb() before checking > the register. I think that's the only place where such argument would be > true (for now). > Good point, I will add the dsb() in mte_check_tfsr_el1() but instead of a bool parameter I will add something more explicit. >> + >> trace_hardirqs_on_prepare(); >> lockdep_hardirqs_on_prepare(CALLER_ADDR0); >> user_enter_irqoff(); >> diff --git a/arch/arm64/kernel/mte.c b/arch/arm64/kernel/mte.c >> index 5d992e16b420..26030f0b79fe 100644 >> --- a/arch/arm64/kernel/mte.c >> +++ b/arch/arm64/kernel/mte.c >> @@ -185,6 +185,34 @@ void mte_enable_kernel(enum kasan_arg_mode mode) >> isb(); >> } >> >> +void mte_check_tfsr_el1(void) >> +{ >> + u64 tfsr_el1; >> + >> + if (!IS_ENABLED(CONFIG_KASAN_HW_TAGS)) >> + return; > > If we define the static inline when !CONFIG_KASAN_HW_TAGS, we could add > the #ifdef here around the whole function. > Ok. I will add it in v3. >> + if (!system_supports_mte()) >> + return; >> + >> + tfsr_el1 = read_sysreg_s(SYS_TFSR_EL1); >> + >> + /* >> + * The kernel should never hit the condition TF0 == 1 >> + * at this point because for the futex code we set >> + * PSTATE.TCO. >> + */ >> + WARN_ON(tfsr_el1 & SYS_TFSR_EL1_TF0); >> + >> + if (tfsr_el1 & SYS_TFSR_EL1_TF1) { >> + write_sysreg_s(0, SYS_TFSR_EL1); >> + isb(); >> + >> + pr_err("MTE: Asynchronous tag exception detected!"); >> + } >> +} >> +NOKPROBE_SYMBOL(mte_check_tfsr_el1); > > Do we need this to be NOKPROBE_SYMBOL? It's not that low level. > It is an inheritance from when I had this code called very early. I will remove it in the next version. >> + >> static void update_sctlr_el1_tcf0(u64 tcf0) >> { >> /* ISB required for the kernel uaccess routines */ >> @@ -250,6 +278,15 @@ void mte_thread_switch(struct task_struct *next) >> /* avoid expensive SCTLR_EL1 accesses if no change */ >> if (current->thread.sctlr_tcf0 != next->thread.sctlr_tcf0) >> update_sctlr_el1_tcf0(next->thread.sctlr_tcf0); >> + >> + /* >> + * Check if an async tag exception occurred at EL1. >> + * >> + * Note: On the context switch patch we rely on the dsb() present > > s/patch/path/ > >> + * in __switch_to() to guaranty that the indirect writes to TFSR_EL1 > > s/guaranty/guarantee/ (well, still valid though I think rarely used). > >> + * are synchronized before this point. >> + */ >> + mte_check_tfsr_el1(); >> } >> >> void mte_suspend_exit(void) >> -- >> 2.30.0 > -- Regards, Vincenzo