Re: [PATCH v5 5/7] arm64: dts: ti: k3-serdes: Add SERDES0/SERDES1 lane-muxing macros for J722S

Roger Quadros
2024-06-06T07:35:53Z

On 04/06/2024 11:52, Siddharth Vadapalli wrote:
> The SERDES0 and SERDES1 instances of SERDES on J722S are single lane
> SERDES which are individually muxed across different peripherals.
>
> LANE0 of SERDES0 is muxed between USB and CPSW while LANE0 of SERDES1 is
> muxed between PCIe and CPSW.
>
> Define the lane-muxing macros to be used as the idle state values.
>
> Co-developed-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
> Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>

Reviewed-by: Roger Quadros <rogerq@kernel.org>