Re: [PATCH v5 4/7] arm64: dts: ti: k3-j722s: Switch to k3-am62p-j722s-common.dtsi

Vignesh Raghavendra
2024-06-06T04:05:41Z

On 04/06/24 14:22, Siddharth Vadapalli wrote:
> Update "k3-j722s.dtsi" to use "k3-am62p-j722s-common.dtsi" which
> contains the nodes shared with AM62P, followed by including the J722S
> specific main domain peripherals contained in "k3-j722s-main.dtsi".
>
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> ---
> v4:
> https://lore.kernel.org/r/20240601121554.2860403-5-s-vadapalli@ti.com/
> No changes since v4.
>
> arch/arm64/boot/dts/ti/k3-j722s.dtsi | 97 +++++++++++++++++++++++++++-
> 1 file changed, 96 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j722s.dtsi b/arch/arm64/boot/dts/ti/k3-j722s.dtsi
> index c75744edb143..9e04e6a5c0fd 100644
> --- a/arch/arm64/boot/dts/ti/k3-j722s.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j722s.dtsi
> @@ -10,12 +10,107 @@
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/soc/ti,sci_pm_domain.h>
>
> -#include "k3-am62p5.dtsi"
> +#include "k3-am62p-j722s-common.dtsi"
> +#include "k3-j722s-main.dtsi"
>
> / {
> model = "Texas Instruments K3 J722S SoC";
> compatible = "ti,j722s";
>
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu-map {
> + cluster0: cluster0 {
> + core0 {
> + cpu = <&cpu0>;
> + };
> +
> + core1 {
> + cpu = <&cpu1>;
> + };
> +
> + core2 {
> + cpu = <&cpu2>;
> + };
> +
> + core3 {
> + cpu = <&cpu3>;
> + };
> + };
> + };
> +
> + cpu0: cpu@0 {
> + compatible = "arm,cortex-a53";
> + reg = <0x000>;
> + device_type = "cpu";
> + enable-method = "psci";
> + i-cache-size = <0x8000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> + next-level-cache = <&l2_0>;
> + clocks = <&k3_clks 135 0>;
> + };
> +
> + cpu1: cpu@1 {
> + compatible = "arm,cortex-a53";
> + reg = <0x001>;
> + device_type = "cpu";
> + enable-method = "psci";
> + i-cache-size = <0x8000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> + next-level-cache = <&l2_0>;
> + clocks = <&k3_clks 136 0>;
> + };
> +
> + cpu2: cpu@2 {
> + compatible = "arm,cortex-a53";
> + reg = <0x002>;
> + device_type = "cpu";
> + enable-method = "psci";
> + i-cache-size = <0x8000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> + next-level-cache = <&l2_0>;
> + clocks = <&k3_clks 137 0>;
> + };
> +
> + cpu3: cpu@3 {
> + compatible = "arm,cortex-a53";
> + reg = <0x003>;
> + device_type = "cpu";
> + enable-method = "psci";
> + i-cache-size = <0x8000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> + next-level-cache = <&l2_0>;
> + clocks = <&k3_clks 138 0>;
> + };
> + };
> +
> + l2_0: l2-cache0 {
> + compatible = "cache";
> + cache-unified;
> + cache-level = <2>;
> + cache-size = <0x80000>;
> + cache-line-size = <64>;
> + cache-sets = <512>;
> + };
> +
> cbass_main: bus@f0000 {
> compatible = "simple-bus";
> #address-cells = <2>;

You would need to move the rest of main domain overrides and cbass_main
definitions to k3-j722s-main.dtsi and limit this file to CPU definitions
similar to k3-am62p5.dtsi

--
Regards
Vignesh