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From: Dragan Simic <dsimic@manjaro.org>
To: Detlev Casanova <detlev.casanova@collabora.com>
Cc: linux-kernel@vger.kernel.org,
	Ulf Hansson <ulf.hansson@linaro.org>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Heiko Stuebner <heiko@sntech.de>,
	Jaehoon Chung <jh80.chung@samsung.com>,
	linux-mmc@vger.kernel.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-rockchip@lists.infradead.org, kernel@collabora.com,
	Shawn Lin <shawn.lin@rock-chips.com>
Subject: Re: [PATCH v4 2/4] mmc: dw_mmc-rockchip: Add internal phase support
Date: Fri, 23 Aug 2024 07:41:44 +0200	[thread overview]
Message-ID: <f0f5dec4a5403616fa25c6ed754f6050@manjaro.org> (raw)
In-Reply-To: <20240822212418.982927-3-detlev.casanova@collabora.com>

Hello Detlev,

Please see a comment below.

On 2024-08-22 23:15, Detlev Casanova wrote:
> From: Shawn Lin <shawn.lin@rock-chips.com>
> 
> Some Rockchip devices put the phase settings into the dw_mmc 
> controller.
> 
> When the feature is present, the ciu-drive and ciu-sample clocks are
> not used and the phase configuration is done directly through the mmc
> controller.
> 
> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
> Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
> Acked-by: Shawn Lin <shawn.lin@rock-chips.com>
> ---
>  drivers/mmc/host/dw_mmc-rockchip.c | 171 +++++++++++++++++++++++++++--
>  1 file changed, 160 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/mmc/host/dw_mmc-rockchip.c
> b/drivers/mmc/host/dw_mmc-rockchip.c
> index b07190ba4b7a..2748f9bf2691 100644
> --- a/drivers/mmc/host/dw_mmc-rockchip.c
> +++ b/drivers/mmc/host/dw_mmc-rockchip.c
> @@ -15,7 +15,17 @@
>  #include "dw_mmc.h"
>  #include "dw_mmc-pltfm.h"
> 
> -#define RK3288_CLKGEN_DIV	2
> +#define RK3288_CLKGEN_DIV		2
> +#define SDMMC_TIMING_CON0		0x130
> +#define SDMMC_TIMING_CON1		0x134
> +#define ROCKCHIP_MMC_DELAY_SEL		BIT(10)
> +#define ROCKCHIP_MMC_DEGREE_MASK	0x3
> +#define ROCKCHIP_MMC_DEGREE_OFFSET	1
> +#define ROCKCHIP_MMC_DELAYNUM_OFFSET	2
> +#define ROCKCHIP_MMC_DELAYNUM_MASK	(0xff << 
> ROCKCHIP_MMC_DELAYNUM_OFFSET)
> +#define ROCKCHIP_MMC_DELAY_ELEMENT_PSEC	60
> +#define HIWORD_UPDATE(val, mask, shift) \
> +		((val) << (shift) | (mask) << ((shift) + 16))
> 
>  static const unsigned int freqs[] = { 100000, 200000, 300000, 400000 
> };
> 
> @@ -24,8 +34,143 @@ struct dw_mci_rockchip_priv_data {
>  	struct clk		*sample_clk;
>  	int			default_sample_phase;
>  	int			num_phases;
> +	int			internal_phase;
>  };

It might be good to declare internal_phase as "unsigned int 
internal_phase:1",
i.e. as a bit field, which isn't going to save some memory in this 
particular
case, but it would show additional attention to detail.

  reply	other threads:[~2024-08-23  5:41 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-08-22 21:15 [PATCH v4 0/4] Add dw_mmc support for rk3576 Detlev Casanova
2024-08-22 21:15 ` [PATCH v4 1/4] dt-bindings: mmc: Add support for rk3576 dw-mshc Detlev Casanova
2024-08-23  7:36   ` Krzysztof Kozlowski
2024-08-22 21:15 ` [PATCH v4 2/4] mmc: dw_mmc-rockchip: Add internal phase support Detlev Casanova
2024-08-23  5:41   ` Dragan Simic [this message]
2024-08-23 13:34     ` Detlev Casanova
2024-08-26 14:39       ` Dragan Simic
2024-08-26 18:44         ` Detlev Casanova
2024-08-22 21:15 ` [PATCH v4 3/4] mmc: dw_mmc-rockchip: Skip all phases bigger than 270 degrees Detlev Casanova
2024-08-23  5:45   ` Dragan Simic
2024-08-23 13:59     ` Detlev Casanova
2024-08-26 14:52       ` Dragan Simic
2024-08-22 21:15 ` [PATCH v4 4/4] mmc: dw_mmc-rockchip: Add support for rk3576 SoCs Detlev Casanova
2024-08-23  7:00   ` Dragan Simic
2024-08-23 13:20     ` Detlev Casanova
2024-08-26 14:07       ` Dragan Simic
2024-08-26 15:45         ` Detlev Casanova

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