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From: Lu Baolu <baolu.lu@linux.intel.com>
To: Jacob Pan <jacob.jun.pan@linux.intel.com>,
	iommu@lists.linux-foundation.org,
	LKML <linux-kernel@vger.kernel.org>,
	Joerg Roedel <joro@8bytes.org>,
	David Woodhouse <dwmw2@infradead.org>
Cc: baolu.lu@linux.intel.com, "Tian, Kevin" <kevin.tian@intel.com>,
	Raj Ashok <ashok.raj@intel.com>, Yi Liu <yi.l.liu@intel.com>,
	Eric Auger <eric.auger@redhat.com>
Subject: Re: [PATCH 05/10] iommu/vt-d: Avoid duplicated code for PASID setup
Date: Mon, 18 Nov 2019 09:33:35 +0800	[thread overview]
Message-ID: <f1f25842-831e-e212-bff2-e1864a944da5@linux.intel.com> (raw)
In-Reply-To: <1573859377-75924-6-git-send-email-jacob.jun.pan@linux.intel.com>

Hi,

On 11/16/19 7:09 AM, Jacob Pan wrote:
> After each setup for PASID entry, related translation caches must be flushed.

nit -  maximum 75 chars per line

Others look good to me.

Acked-by: Lu Baolu <baolu.lu@linux.intel.com>

Best regards,
baolu

> We can combine duplicated code into one function which is less error prone.
> 
> Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
> Reviewed-by: Lu Baolu <baolu.lu@linux.intel.com>
> ---
>   drivers/iommu/intel-pasid.c | 48 +++++++++++++++++----------------------------
>   1 file changed, 18 insertions(+), 30 deletions(-)
> 
> diff --git a/drivers/iommu/intel-pasid.c b/drivers/iommu/intel-pasid.c
> index e7cb0b8a7332..732bfee228df 100644
> --- a/drivers/iommu/intel-pasid.c
> +++ b/drivers/iommu/intel-pasid.c
> @@ -465,6 +465,21 @@ void intel_pasid_tear_down_entry(struct intel_iommu *iommu,
>   		devtlb_invalidation_with_pasid(iommu, dev, pasid);
>   }
>   
> +static void pasid_flush_caches(struct intel_iommu *iommu,
> +				struct pasid_entry *pte,
> +				int pasid, u16 did)
> +{
> +	if (!ecap_coherent(iommu->ecap))
> +		clflush_cache_range(pte, sizeof(*pte));
> +
> +	if (cap_caching_mode(iommu->cap)) {
> +		pasid_cache_invalidation_with_pasid(iommu, did, pasid);
> +		iotlb_invalidation_with_pasid(iommu, did, pasid);
> +	} else {
> +		iommu_flush_write_buffer(iommu);
> +	}
> +}
> +
>   /*
>    * Set up the scalable mode pasid table entry for first only
>    * translation type.
> @@ -518,16 +533,7 @@ int intel_pasid_setup_first_level(struct intel_iommu *iommu,
>   	/* Setup Present and PASID Granular Transfer Type: */
>   	pasid_set_translation_type(pte, 1);
>   	pasid_set_present(pte);
> -
> -	if (!ecap_coherent(iommu->ecap))
> -		clflush_cache_range(pte, sizeof(*pte));
> -
> -	if (cap_caching_mode(iommu->cap)) {
> -		pasid_cache_invalidation_with_pasid(iommu, did, pasid);
> -		iotlb_invalidation_with_pasid(iommu, did, pasid);
> -	} else {
> -		iommu_flush_write_buffer(iommu);
> -	}
> +	pasid_flush_caches(iommu, pte, pasid, did);
>   
>   	return 0;
>   }
> @@ -591,16 +597,7 @@ int intel_pasid_setup_second_level(struct intel_iommu *iommu,
>   	 */
>   	pasid_set_sre(pte);
>   	pasid_set_present(pte);
> -
> -	if (!ecap_coherent(iommu->ecap))
> -		clflush_cache_range(pte, sizeof(*pte));
> -
> -	if (cap_caching_mode(iommu->cap)) {
> -		pasid_cache_invalidation_with_pasid(iommu, did, pasid);
> -		iotlb_invalidation_with_pasid(iommu, did, pasid);
> -	} else {
> -		iommu_flush_write_buffer(iommu);
> -	}
> +	pasid_flush_caches(iommu, pte, pasid, did);
>   
>   	return 0;
>   }
> @@ -634,16 +631,7 @@ int intel_pasid_setup_pass_through(struct intel_iommu *iommu,
>   	 */
>   	pasid_set_sre(pte);
>   	pasid_set_present(pte);
> -
> -	if (!ecap_coherent(iommu->ecap))
> -		clflush_cache_range(pte, sizeof(*pte));
> -
> -	if (cap_caching_mode(iommu->cap)) {
> -		pasid_cache_invalidation_with_pasid(iommu, did, pasid);
> -		iotlb_invalidation_with_pasid(iommu, did, pasid);
> -	} else {
> -		iommu_flush_write_buffer(iommu);
> -	}
> +	pasid_flush_caches(iommu, pte, pasid, did);
>   
>   	return 0;
>   }
> 

  reply	other threads:[~2019-11-18  1:36 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-11-15 23:09 [PATCH 00/10] VT-d Native Shared virtual memory cleanup and fixes Jacob Pan
2019-11-15 23:09 ` [PATCH 01/10] iommu/vt-d: Introduce native SVM capable flag Jacob Pan
2019-11-18  1:19   ` Lu Baolu
2019-11-15 23:09 ` [PATCH 02/10] iommu/vt-d: Fix CPU and IOMMU SVM feature matching checks Jacob Pan
2019-11-18  1:20   ` Lu Baolu
2019-11-15 23:09 ` [PATCH 03/10] iommu/vt-d: Reject SVM bind for failed capability check Jacob Pan
2019-11-18  1:30   ` Lu Baolu
2019-11-15 23:09 ` [PATCH 04/10] iommu/vt-d: Match CPU and IOMMU paging mode Jacob Pan
2019-11-18  1:31   ` Lu Baolu
2019-11-15 23:09 ` [PATCH 05/10] iommu/vt-d: Avoid duplicated code for PASID setup Jacob Pan
2019-11-18  1:33   ` Lu Baolu [this message]
2019-11-15 23:09 ` [PATCH 06/10] iommu/vt-d: Fix off-by-one in PASID allocation Jacob Pan
2019-11-18  1:34   ` Lu Baolu
2019-11-15 23:09 ` [PATCH 07/10] iommu/vt-d: Replace Intel specific PASID allocator with IOASID Jacob Pan
2019-11-18  1:43   ` Lu Baolu
2019-11-18 18:50     ` Jacob Pan
2019-11-15 23:09 ` [PATCH 08/10] iommu/vt-d: Fix PASID cache flush Jacob Pan
2019-11-18  1:43   ` Lu Baolu
2019-11-15 23:09 ` [PATCH 09/10] iommu/vt-d: Avoid sending invalid page response Jacob Pan
2019-11-18  1:54   ` Lu Baolu
2019-11-15 23:09 ` [PATCH 10/10] iommu/vt-d: Misc macro clean up for SVM Jacob Pan
2019-11-18  2:23   ` Lu Baolu
2019-11-18 18:36     ` Jacob Pan

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