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[42.3.109.144]) by smtp.gmail.com with ESMTPSA id i18-20020a170902c95200b001e3f148ffb8sm4121481pla.21.2024.04.13.01.04.18 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 13 Apr 2024 01:04:20 -0700 (PDT) Message-ID: Date: Sat, 13 Apr 2024 16:04:12 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] arm64: dts: qcom: Split PMU nodes for heterogeneous CPUs To: Rob Herring , Bjorn Andersson , Konrad Dybcio , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20240412222942.3874269-1-robh@kernel.org> Content-Language: en-US From: Xilin Wu In-Reply-To: <20240412222942.3874269-1-robh@kernel.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 2024/4/13 6:29, Rob Herring wrote: > Arm heterogeneous configurations should have separate PMU nodes for each > CPU uarch as the uarch specific events can be different. The > "arm,armv8-pmuv3" compatible is also intended for s/w models rather than > specific uarch implementations. > > All the kryo CPUs are missing PMU compatibles, so they can't be fixed. > > Signed-off-by: Rob Herring > --- > arch/arm64/boot/dts/qcom/msm8956.dtsi | 4 ++-- > arch/arm64/boot/dts/qcom/msm8976.dtsi | 10 ++++++++++ > arch/arm64/boot/dts/qcom/sm4450.dtsi | 11 ++++++++--- > arch/arm64/boot/dts/qcom/sm8350.dtsi | 14 ++++++++++++-- > arch/arm64/boot/dts/qcom/sm8550.dtsi | 19 +++++++++++++++++-- > arch/arm64/boot/dts/qcom/sm8650.dtsi | 14 ++++++++++++-- > 6 files changed, 61 insertions(+), 11 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/msm8956.dtsi b/arch/arm64/boot/dts/qcom/msm8956.dtsi > index 668e05185c21..fa36b62156bb 100644 > --- a/arch/arm64/boot/dts/qcom/msm8956.dtsi > +++ b/arch/arm64/boot/dts/qcom/msm8956.dtsi > @@ -8,8 +8,8 @@ > > #include "msm8976.dtsi" > > -&pmu { > - interrupts = ; > +&pmu_a72 { > + interrupts = ; > }; > > &tsens { > diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi > index d2bb1ada361a..1ad102b1633c 100644 > --- a/arch/arm64/boot/dts/qcom/msm8976.dtsi > +++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi > @@ -226,6 +226,16 @@ pmu: pmu { > compatible = "arm,armv8-pmuv3"; > interrupts = ; > }; > + pmu-a53 { > + compatible = "arm,cortex-a53-pmu"; > + interrupts = ; > + }; > + > + pmu_a72: pmu-a72 { > + compatible = "arm,cortex-a72-pmu"; > + interrupts = ; > + }; > + > > psci { > compatible = "arm,psci-1.0"; > diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qcom/sm4450.dtsi > index 603c962661cc..411eb7577407 100644 > --- a/arch/arm64/boot/dts/qcom/sm4450.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi > @@ -268,9 +268,14 @@ memory@a0000000 { > reg = <0x0 0xa0000000 0x0 0x0>; > }; > > - pmu { > - compatible = "arm,armv8-pmuv3"; > - interrupts = ; > + pmu-a55 { > + compatible = "arm,cortex-a55-pmu"; > + interrupts = ; > + }; > + > + pmu-a78 { > + compatible = "arm,cortex-a78-pmu"; > + interrupts = ; > }; > > psci { > diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi > index a5e7dbbd8c6c..127fa9a935da 100644 > --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi > @@ -300,8 +300,18 @@ memory@80000000 { > reg = <0x0 0x80000000 0x0 0x0>; > }; > > - pmu { > - compatible = "arm,armv8-pmuv3"; > + pmu-a55 { > + compatible = "arm,cortex-a55-pmu"; > + interrupts = ; > + }; > + > + pmu-a78 { > + compatible = "arm,cortex-a78-pmu"; > + interrupts = ; > + }; > + > + pmu-x1 { > + compatible = "arm,cortex-x1-pmu"; > interrupts = ; > }; > > diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi > index 3904348075f6..8e7d0ac17a12 100644 > --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi > @@ -357,8 +357,23 @@ memory@a0000000 { > reg = <0 0xa0000000 0 0>; > }; > > - pmu { > - compatible = "arm,armv8-pmuv3"; > + pmu-a510 { > + compatible = "arm,cortex-a510-pmu"; > + interrupts = ; > + }; > + > + pmu-a710 { > + compatible = "arm,cortex-a710-pmu"; > + interrupts = ; > + }; > + > + pmu-a720 { > + compatible = "arm,cortex-a720-pmu"; > + interrupts = ; > + }; > + > + pmu-x3 { > + compatible = "arm,cortex-x3-pmu"; > interrupts = ; > }; > I believe SM8550 uses cortex-a715 instead of a720. > diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi > index ba72d8f38420..90102a41489d 100644 > --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi > @@ -394,8 +394,18 @@ memory@a0000000 { > reg = <0 0xa0000000 0 0>; > }; > > - pmu { > - compatible = "arm,armv8-pmuv3"; > + pmu-a520 { > + compatible = "arm,cortex-a520-pmu"; > + interrupts = ; > + }; > + > + pmu-a720 { > + compatible = "arm,cortex-a720-pmu"; > + interrupts = ; > + }; > + > + pmu-x4 { > + compatible = "arm,cortex-x4-pmu"; > interrupts = ; > }; >