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From: "Sagar, Vishal" <vishal.sagar@amd.com>
To: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>,
	Anatoliy Klymenko <anatoliy.klymenko@amd.com>,
	Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
	Maxime Ripard <mripard@kernel.org>,
	Thomas Zimmermann <tzimmermann@suse.de>,
	David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
	Laurent Pinchart <laurent.pinchart@ideasonboard.com>,
	Michal Simek <michal.simek@amd.com>
Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	Geert Uytterhoeven <geert@linux-m68k.org>,
	Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>,
	Pekka Paalanen <ppaalanen@gmail.com>
Subject: Re: [PATCH v5 09/11] drm: xlnx: zynqmp: Add support for Y8 and Y10_P32
Date: Wed, 3 Sep 2025 16:01:02 +0200	[thread overview]
Message-ID: <f377f304-395c-4c51-ae03-df76da3344b2@amd.com> (raw)
In-Reply-To: <20250425-xilinx-formats-v5-9-c74263231630@ideasonboard.com>

Hi Tomi,

Thanks for the patch.

On 4/25/2025 1:01 PM, Tomi Valkeinen wrote:
> Add support for Y8 and Y10_P32 formats. We also need to add new csc
> matrices for the y-only formats.
> 
> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
> ---
>   drivers/gpu/drm/xlnx/zynqmp_disp.c | 26 +++++++++++++++++++++++++-
>   1 file changed, 25 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp.c b/drivers/gpu/drm/xlnx/zynqmp_disp.c
> index 1dc77f2e4262..fe111fa8cc13 100644
> --- a/drivers/gpu/drm/xlnx/zynqmp_disp.c
> +++ b/drivers/gpu/drm/xlnx/zynqmp_disp.c
> @@ -307,6 +307,16 @@ static const struct zynqmp_disp_format avbuf_vid_fmts[] = {
>   		.buf_fmt	= ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI_10,
>   		.swap		= false,
>   		.sf		= scaling_factors_101010,
> +	}, {
> +		.drm_fmt	= DRM_FORMAT_Y8,
> +		.buf_fmt	= ZYNQMP_DISP_AV_BUF_FMT_NL_VID_MONO,
> +		.swap		= false,
> +		.sf		= scaling_factors_888,
> +	}, {
> +		.drm_fmt	= DRM_FORMAT_Y10_P32,
> +		.buf_fmt	= ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YONLY_10,
> +		.swap		= false,
> +		.sf		= scaling_factors_101010,
>   	},
>   };
>   
> @@ -697,6 +707,16 @@ static const u32 csc_sdtv_to_rgb_offsets[] = {
>   	0x0, 0x1800, 0x1800
>   };
>   
> +static const u16 csc_sdtv_to_rgb_yonly_matrix[] = {
> +	0x0, 0x0, 0x1000,
> +	0x0, 0x0, 0x1000,
> +	0x0, 0x0, 0x1000,
> +};
> +
> +static const u32 csc_sdtv_to_rgb_yonly_offsets[] = {
> +	0x0, 0x0, 0x0
> +};
> +
>   /**
>    * zynqmp_disp_blend_set_output_format - Set the output format of the blender
>    * @disp: Display controller
> @@ -846,7 +866,11 @@ static void zynqmp_disp_blend_layer_enable(struct zynqmp_disp *disp,
>   				ZYNQMP_DISP_V_BLEND_LAYER_CONTROL(layer->id),
>   				val);
>   
> -	if (layer->drm_fmt->is_yuv) {
> +	if (layer->drm_fmt->format == DRM_FORMAT_Y8 ||
> +	    layer->drm_fmt->format == DRM_FORMAT_Y10_P32) {
> +		coeffs = csc_sdtv_to_rgb_yonly_matrix;
> +		offsets = csc_sdtv_to_rgb_yonly_offsets;
> +	} else if (layer->drm_fmt->is_yuv) {
>   		coeffs = csc_sdtv_to_rgb_matrix;
>   		offsets = csc_sdtv_to_rgb_offsets;
>   	} else {
> 


This looks good. Feel free to add -

Reviewed-by: Vishal Sagar <vishal.sagar@amd.com>

Regards
Vishal Sagar

  reply	other threads:[~2025-09-03 14:01 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-04-25 11:01 [PATCH v5 00/11] drm: Add new pixel formats for Xilinx Zynqmp Tomi Valkeinen
2025-04-25 11:01 ` [PATCH v5 01/11] drm/fourcc: Add warning for bad bpp Tomi Valkeinen
2025-04-25 11:01 ` [PATCH v5 02/11] drm/fourcc: Add DRM_FORMAT_XV15/XV20 Tomi Valkeinen
2025-09-03 13:59   ` Sagar, Vishal
2025-04-25 11:01 ` [PATCH v5 03/11] drm/fourcc: Add DRM_FORMAT_Y8 Tomi Valkeinen
2025-04-25 11:59   ` Pekka Paalanen
2025-09-03 13:59   ` Sagar, Vishal
2025-04-25 11:01 ` [PATCH v5 04/11] drm/fourcc: Add DRM_FORMAT_Y10_P32 Tomi Valkeinen
2025-09-03 13:59   ` Sagar, Vishal
2025-04-25 11:01 ` [PATCH v5 05/11] drm/fourcc: Add DRM_FORMAT_X403 Tomi Valkeinen
2025-04-26  2:14   ` Dmitry Baryshkov
2025-09-03 13:59   ` Sagar, Vishal
2025-04-25 11:01 ` [PATCH v5 06/11] drm/fourcc: Add DRM_FORMAT_XVUY2101010 Tomi Valkeinen
2025-09-03 14:00   ` Sagar, Vishal
2025-04-25 11:01 ` [PATCH v5 07/11] drm: xlnx: zynqmp: Use drm helpers when calculating buffer sizes Tomi Valkeinen
2025-04-25 11:01 ` [PATCH v5 08/11] drm: xlnx: zynqmp: Add support for XV15 & XV20 Tomi Valkeinen
2025-09-03 14:00   ` Sagar, Vishal
2025-04-25 11:01 ` [PATCH v5 09/11] drm: xlnx: zynqmp: Add support for Y8 and Y10_P32 Tomi Valkeinen
2025-09-03 14:01   ` Sagar, Vishal [this message]
2025-04-25 11:01 ` [PATCH v5 10/11] drm: xlnx: zynqmp: Add support for X403 Tomi Valkeinen
2025-09-03 14:01   ` Sagar, Vishal
2025-04-25 11:01 ` [PATCH v5 11/11] drm: xlnx: zynqmp: Add support for XVUY2101010 Tomi Valkeinen
2025-09-03 14:01   ` Sagar, Vishal
2025-08-08 11:15 ` [PATCH v5 00/11] drm: Add new pixel formats for Xilinx Zynqmp Tomi Valkeinen

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