RE: [PATCH] PCI/P2PDMA: Update device table with 3rd gen Xeon platform information

Ruhl, Michael J
2022-02-25T15:49:56Z

Hi,

I see that this patch is in the Linux PCI development patchwork.

I am not sure what the timeline for this process is.

Will this be accepted or rejected "officially"?

Do I need to do anything else to move this patch forward?

Thanks,

Mike

>-----Original Message-----
>From: Ruhl, Michael J <michael.j.ruhl@intel.com>
>Sent: Wednesday, February 9, 2022 11:28 AM
>To: linux-pci@vger.kernel.org; linux-kernel@vger.kernel.org;
>bhelgaas@google.com; logang@deltatee.com; Ruhl, Michael J
><michael.j.ruhl@intel.com>
>Cc: Williams, Dan J <dan.j.williams@intel.com>
>Subject: [PATCH] PCI/P2PDMA: Update device table with 3rd gen Xeon
>platform information
>
>In order to do P2P communication the bridge ID of the platform
>must be in the P2P device table.
>
>Update the P2P device table with a device id for the 3rd Gen
>Intel Xeon Scalable Processors.
>
>Reviewed-by: Dan Williams <dan.j.williams@intel.com>
>Signed-off-by: Michael J. Ruhl <michael.j.ruhl@intel.com>
>---
> drivers/pci/p2pdma.c | 1 +
> 1 file changed, 1 insertion(+)
>
>diff --git a/drivers/pci/p2pdma.c b/drivers/pci/p2pdma.c
>index 1015274bd2fe..30b1df3c9d2f 100644
>--- a/drivers/pci/p2pdma.c
>+++ b/drivers/pci/p2pdma.c
>@@ -321,6 +321,7 @@ static const struct pci_p2pdma_whitelist_entry {
> {PCI_VENDOR_ID_INTEL, 0x2032, 0},
> {PCI_VENDOR_ID_INTEL, 0x2033, 0},
> {PCI_VENDOR_ID_INTEL, 0x2020, 0},
>+ {PCI_VENDOR_ID_INTEL, 0x09a2, 0},
> {}
> };
>
>--
>2.31.1